CN101825683B - Integrated circuit device and measurement system and method thereof - Google Patents
Integrated circuit device and measurement system and method thereof Download PDFInfo
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- CN101825683B CN101825683B CN200910004643A CN200910004643A CN101825683B CN 101825683 B CN101825683 B CN 101825683B CN 200910004643 A CN200910004643 A CN 200910004643A CN 200910004643 A CN200910004643 A CN 200910004643A CN 101825683 B CN101825683 B CN 101825683B
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Abstract
The invention relates to an integrated circuit device and a measurement system and method thereof. The integrated circuit device at least contains a substrate and a first chip, wherein the first chip can be stacked on the substrate through a plurality of bumps and the first chip comprises a plurality of first via holes. In addition, a plurality of first conductive elements can be respectively formed on one of the first via holes and respectively electrically connected with the corresponding first bump. In particular, a first sensor can be configured on the first chip to sense the resistance value of the first chip and generate the first group of sense signals. Furthermore, a first wire pair can be used to ensure that the first sensor is electrically connected with the first conductive elements, thus the first group of sense signals can be transmitted to the first output end of the substrate through the first wire pair, the corresponding first conductive element and the corresponding first bump.
Description
Technical field
The present invention relates to a kind of IC apparatus, particularly relate to a kind of measuring system and method.
Background technology
Along with the downsizing gradually of electronic system product, from the various elements that traditional circuit-board has been covered with, becoming gradually contracts is contained in the single encapsulating structure, and then come in the heterogeneous integration one chip.And in this integration process, possess system multifunctional, heterogeneous one chip structure, need need different processes in response to different materials.Yet, this problem be overcome and great time and investment must be spent, in the face of present production life cycle is short, the market kenel of low-cost production, as if development system is integrated heterogeneous chip, and slow action cannot save a critical situation.Therefore, will have the difference in functionality chip and be incorporated in the encapsulating structure, just become the direction that is worth development.
At present to the technology that different chips is incorporated into same encapsulating structure, include System on Chip/SoC (System on Chip, SoC) with system in package (System in Package, SiP) wait technological.In these technology, normally multiple chips is packaged into a potted element.Wherein, chip can be distributed on the substrate, or the mode that adopts chip directly to pile up.In addition, also have a solution, the mode of piling up different chips with projection fully exactly is stacked into whole core assembly sheet (the wafer thinning of can arranging in pairs or groups usually).
In the structure that projection piles up,, therefore just increased the complexity of structure owing to be that multilayer chiop is stacked through bump bond.And in order to observe after each chip piles up with projection; For example because of the thermal expansion coefficient difference of various different chips to thermal stress/strain regime that each chip and projection caused; Or external force or the gravity mechanical stress/strain of drawing; Must develop and some new measuring methods, can effectively, immediately learning the stress/strain strain regime of chip internal, and utilize time-histories that these instant messages accelerate design or process improving to promote competitive power.
Summary of the invention
Therefore in an embodiment, the present invention can provide a kind of measuring method, can measure the chip in the semiconductor device with stacked structure, the stress/strain that in its two dimensional surface and three-dimensional, is born.
The present invention provides a kind of IC apparatus, comprises the substrate and first chip at least.First chip can be stacked on the substrate through a plurality of first projections, and first chip has a plurality of first vias.In addition, a plurality of first transport elements correspondence respectively are formed on first via in one of them, and can electrically connect the first corresponding projection.Specifically, first sensor can be configured on first chip, with the resistance value of sensing first chip, and produces first group of sensing signal.In addition, first lead is to being electrically connected to the first corresponding transport element with first sensor.Thus, first group of sensing signal can be sent to a plurality of first output terminals on the substrate to, corresponding first transport element and the first corresponding projection through first lead.
From another viewpoint, the present invention also provides a kind of measuring system, goes for having the IC apparatus of stacked structure, and it has substrate and chip at least.And measuring system provided by the present invention comprises first sensor, a plurality of first lead and analysis module.First sensor can electrically connect chip, with the resistance value of sensor chip, and produces first group of sensing signal.Wherein, chip has a plurality of first vias, and a plurality of transport element respectively correspondence be formed on first via in one of them so that chip can see through first transport element and a plurality of projection electrically connects substrate.In addition, first lead can be connected to corresponding transport element with the first sensor correspondence, is sent to first output terminal on the substrate first group of sensing signal seen through corresponding transport element with corresponding projection.Analysis module then can electrically connect first output terminal, receiving and to analyze first group of sensing signal being exported from first output terminal, and can change according to the stress/strain that first group of sensing signal detected chip.
From another viewpoint, the present invention also provides a kind of measuring method, can measure the inner stress/strain that chip bore of IC apparatus.Wherein, chip can see through a plurality of projections and be stacked on the substrate, and chip has a plurality of vias.In addition, in each via, all dispose transport element, be electrically connected to corresponding projection respectively.And measuring method provided by the present invention comprises the resistance value of the first surface of measured chip, and produces first group of sensing signal.In addition, the present invention can see through corresponding transport element and with corresponding projection first group of sensing signal is sent to a plurality of first output terminals on the substrate.Thus, the present invention just can be according to the variation of the resistance value of first surface, and measures the stress/strain that first surface bore.
Because the present invention can sensors configured on chip, with the resistance value on the measured chip.Therefore, the present invention's stress/strain that can come measured chip to afford according to measured resistance value.In addition, because the lead among the present invention is to be connected on the transport element, so the present invention directly utilizes transport element and projection to transmit signal, and needn't lean on extra lead-in wire to transmit signal.
For letting above-mentioned and other feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Fig. 1 illustrates the system block diagrams into a kind of measuring system that accordings to the preferred embodiments of the present invention.
Fig. 2 illustrates the encapsulating structure figure that adorns into according to a kind of integrated circuit of first embodiment of the invention.
Fig. 3 A and 3B illustrate the encapsulating structure figure into a kind of integrated circuit of accordinging to second embodiment of the invention.
Fig. 4 A illustrates to a kind of chip and in three-dimensional, meets with stresses/synoptic diagram of strain.
Fig. 4 B illustrates the geometric figure into a kind of equivalence.
Fig. 5 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to third embodiment of the invention.
Fig. 6 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to fourth embodiment of the invention.
Fig. 7 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to fifth embodiment of the invention.
Fig. 8 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to sixth embodiment of the invention.
Description of reference numerals
100: measuring system
102,200,300,500,600,700,800: IC apparatus
104: analysis module
202: substrate
204,802: chip
206,804: projection
210,212,214,216,706,718,720,808: transport element
210a: conductor pin
210b: contact mat
222,702: output terminal
224,710: weld pad
226,236,240,504,606,610,708,714: lead
232,234,502,602,604,712,814: sensor
S1+, S1-: sensing signal
TSV1, TSV2, TSV3, TSV4, TSV5, TSV6, TSV7, TSV8, TSV9: via
Embodiment
Fig. 1 illustrates the system block diagrams into a kind of measuring system that accordings to the preferred embodiments of the present invention.Please with reference to Fig. 1, the measuring system 100 that present embodiment provided can be measured the IC apparatus 102 with stacked structure.Wherein, dispose sensor (below have detailed explanation) in the IC apparatus 102 at least, can measure the resistance value of integrated circuit 102 inside chips, and can produce one group of sensing signal S1+ and S1-.Sensing signal S1+ and S1-can be sent to analysis module 104 via the output terminal of IC apparatus 102.Thus, analysis module 104 just can be detected the internal stress/strain variation of IC apparatus 102 according to sensing signal S1+ and S1-.
Wherein, R is the resistance value of IC apparatus 102 inside chips, and Δ R then is the change amount of resistance value.In addition, A '
IjBe transition matrix, and σ '
IjThen be stress value, it also can utilize the form of matrix to represent.In addition, α is the material coefficient of thermal expansion coefficient, and T then is a temperature.
Can know by above (1) formula,, just can calculate the stress/strain that IC apparatus 102 is born as long as analysis module 104 obtains the resistance value and the variable quantity of IC apparatus 102 inside chips.And, the inner structure of IC apparatus provided by the present invention is described with next several embodiment that provides.
First embodiment
Fig. 2 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to first embodiment of the invention.Please with reference to Fig. 2, the IC apparatus 200 that present embodiment provided comprises substrate 202 and chip 204.Wherein, chip 204 can pass through a plurality of projections 206, and is stacked on the substrate 202.
And therefore the present invention also comprises at least one sensor in order to measure the stress/strain that chip bore in the integrated circuit in IC apparatus provided by the present invention.And in the present embodiment, just disposing sensor 232 and 234 on the chip 204, it can be installed in the upper surface of chip 204.Wherein, sensor 232 and 234 is to be used for the resistance value of upper surface of sensor chip 204, and produces corresponding sense signals, for example the sensing signal S1 among Fig. 1.In the present embodiment, sensor 232 and 234 can utilize conductor and semiconductor material, or utilizes technologies such as wafer thick film and semiconductor to accomplish, the material that its material for example is copper, aluminium, polysilicon constant resistance value is bigger.
In addition, it is right on chip 204, can also to dispose a plurality of leads, and for example 236 and 240.Wherein, lead 236 [1] and 236 [2] can be electrically connected to contiguous transport element 210 and 212 respectively with sensor 232, and lead 240 [1] and 240 [2] then can be electrically connected to transport element 214 and 216 with sensor 234.Thus, many groups sensing signal that sensor 232 and 234 is produced can see through corresponding lead, corresponding transport element and corresponding projection is connected to the weld pad 224 on the substrate 202, and delivers to outside analysis module from output terminal 222.For example, one group of sensing signal that sensor 232 is exported can see through transport element 210 and 212, projection 206 [1] and 206 [2], lead 226 [1] and 226 [2] and deliver to the weld pad 224 [1] and 224 [2] on the output terminal 222 respectively.Relatively, one group of sensing signal that sensor 234 is exported then can see through transport element 214 and 216, projection 206 [3] and 206 [4], lead 226 [3] and 226 [4] and deliver to the weld pad 224 [3] and 224 [4] on the output terminal 222 respectively.
Second embodiment
Fig. 3 A and Fig. 3 B illustrate the encapsulating structure figure into a kind of integrated circuit of accordinging to second embodiment of the invention.Because in the present invention, sensor can see through sensing element and projection, and sensing signal is delivered to output terminal.Therefore, sensor can also be configured in any position of chip in present embodiments more of the present invention.For example in Fig. 3 A, sensor 232 and 234 can be configured in respectively on the different surfaces of chip 204.And select among the embodiment at some, sensor 234 can be with respect to the position of sensor 232 at chip 204 upper surfaces in the position of chip 204 lower surfaces, and for example Fig. 3 B illustrates.
Because present embodiment can be distinguished sensors configured 232 and 234 in relative position on the upper and lower surface of chip 204.Therefore, the stress/strain that present embodiment not only can sensor chip 204 be born on the plane of upper surface or lower surface, the stress/strain that more can analysis chip 204 in three-dimensional, be produced.Only in the present embodiment, sensor 232 and 234 looks like in Fig. 3 B through identical projection 206 [1] and 206 [2] delivers to output terminal 222 with sensing signal, in fact but not so.Those of ordinary skill in the art should be known in the sensing signal that sensor 232 and 234 is produced, and is to be sent to output terminal 222 through different transmission paths.
Fig. 4 A illustrates to a kind of chip and in three-dimensional, meets with stresses/synoptic diagram of strain.Can clearly be seen that from Fig. 4 A, born stress, therefore on X-Y plane, produce strain, and its displacement is assumed to be u1 at the upper surface of chip 204.In addition, the lower surface of chip 204 produces strain because of stress equally on X-Y plane, and its displacement then can be u2.And in the upper surface and lower surface generation strain of chip 204, also can make chip 204 produce strain in the Z direction.Can find out clearly that from Fig. 4 A the length of chip 204 on the Z direction becomes z2 from z1.
And if to try to achieve the length of z2, then can adopt Pythagorean theorem to ask for, its mathematical expression can be represented as follows:
And its equivalent geometric figure can be with reference to Fig. 4 B.Hence one can see that, and present embodiment only need calculate chip 204 upper surfaces and lower surface meets with stresses/situation of strain, just can analyze chip 204 simultaneously and in three-dimensional, meet with stresses/situation of strain.
Yet,, also can adopt the structure of following the 3rd embodiment if only need analysis chip 204 to meet with stresses in the Z direction/situation of strain.
The 3rd embodiment
Fig. 5 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to third embodiment of the invention.Please with reference to Fig. 5, as previously mentioned, sensor can be configured in any position of chip.For example in the IC apparatus 500 that present embodiment provided, sensor 502 can be configured in the side of chip 204.In addition, sensor 502 can also see through lead 504 [1] and 504 [2] and be electrically connected to transport element 210 and 212.With aforementioned similar, the resistance value of sensor 502 on equally also can the side of sensor chip 204, and produce one group of sensing signal.And this group sensing signal can pass through lead 504 [1] and 504 [2], transport element 210 and 212, projection 206 [1] and 206 [2] and be sent to the weld pad 224 [1] and 224 [2] on the output terminal 222 of substrate 202.Thus, the stress/strain that just can measured chip bears of present embodiment in vertical direction.
In addition, the above advantage of additional feedthrough structure that do not need is extended application, the present invention also provides the structure of following the 4th embodiment.
The 4th embodiment
Fig. 6 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to fourth embodiment of the invention.Please with reference to Fig. 6; The IC apparatus 600 that present embodiment provided; Be with the difference of IC apparatus in the previous embodiment; In the present embodiment, sensor 602 and 604 can be installed in the chip, and can be electrically connected at transport element 210,212,214 and 216 through corresponding lead 606 [1], 606 [2], 610 [1] and 610 [2] respectively.Likewise, the resistance value that sensor 602 and 604 can sensor chip 204 inner a certain specific directions.Thus, present embodiment just can measure the stress/strain that chip 204 inner these specific directions are born.
The 5th embodiment
Fig. 7 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to fifth embodiment of the invention.Please with reference to Fig. 7; The IC apparatus that the IC apparatus 700 that present embodiment provided and aforementioned several embodiment are provided is close, and different is, in the present embodiment; Substrate 202 not only disposes output terminal 222 at upper surface, can also dispose other output terminal 702 at lower surface.Therefore, for can be with sensor, for example the sensing signal of generations such as 712 and 714 be delivered to output terminal 702, then in substrate 202, just need dispose a plurality of vias, for example TSV5, TSV6, TSV7 and TSV8.
Likewise, in these vias, also can form transport element 706 [1:4] respectively.In addition, on output terminal 702, can dispose weld pad (for example 710 [1:4]) and many leads 708 [1:4] too.In the present embodiment, each lead 708 [1:4] can distinguish corresponding electrically connect transport element 706 [1:4] one of them.And, just can respectively weld pad 710 [1:4] correspondence be electrically connected to transport element 706 [1:4] through these leads 708 [1:4].
In the present embodiment, sensor 712 can see through lead 714 [1] and 714 [2] and be electrically connected to transport element 718 and 720.And transport element 718 and 720 can be respectively see through projection 206 [5] and 206 [6] and lead 722 [1] and 722 [2] be coupled to transport element 706.Thus, the sensing signal that sensor 712 is exported just can pass through transport element 706 and different leads 708 [1] and 708 [2], and deliver to the weld pad on the output terminal 702, and for example 710 [1] and 710 [2].
The 6th embodiment
Fig. 8 illustrates the encapsulating structure figure into a kind of integrated circuit of accordinging to sixth embodiment of the invention.Please with reference to Fig. 8, the IC apparatus 800 that present embodiment provided is the multiple-level stack structure.In other words, IC apparatus 800 not only has chip 204, also comprises chip 802.And in the present embodiment, chip 802 is through a plurality of projections 804, and is stacked on the chip 204.
Likewise, chip 802 has a plurality of vias, TSV9 for example, and wherein can form similarly is 808 and 810 transport element.And these transport elements 808 can be electrically connected to corresponding projection 804 [1] and 804 [2].In addition, also can sensors configured on the chip 802, for example 814, it can be installed in the upper surface of chip 802.The resistance value same, that sensor 814 can sensor chip 802 upper surfaces, and produce sensing signal.And this sensing signal can to see through similarly be 816 [1] and 816 [2] lead, and be sent to contiguous transport element 808 and 810.Thus, sensing signal just can see through transport element and projection corresponding on chip 802, and sees through transport element and projection corresponding on chip 204, and is sent to the output terminal 222 or 702 of substrate 202.And detailed principle can no longer be given unnecessary details for literary composition at this with reference to above narration.
In sum, in above several embodiment, all be the resistance value when utilizing sensor to come measured chip deformation, and produce corresponding sense signals.And this sensing signal can see through transport element and projection and be sent to the output terminal of substrate.Thus, the present invention just can come the suffered stress/strain of analytical calculation chip according to these sensing signals.
In addition, because sensing signal is to see through transport element and projection transmits, so present embodiment need not utilize extra lead-in wire mode to transmit signal, and this position that makes sensor put can be more flexible.Further, because the position that the present invention can let sensor put is more flexible, so the present invention can measure chip suffered stress/strain in three-dimensional.
Though the present invention discloses as above with preferred embodiment; Right its is not that any those of ordinary skill in the art is not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (25)
1. IC apparatus comprises:
Substrate has a plurality of first output terminals;
First chip is stacked on this substrate through a plurality of first projections, and this chip has a plurality of first vias;
A plurality of first transport elements, correspondence is formed on these a plurality of first vias in one of them respectively, and electrically connects these a plurality of first projections respectively;
First sensor is configured on this first chip, in order to the resistance value of this first chip of sensing, and produces first group of sensing signal; And
First lead is right, respectively this first sensor is electrically connected to the first corresponding transport element, so that this first group of sensing signal is sent to this a plurality of first output terminals through first transport element of correspondence and first projection of correspondence.
2. IC apparatus as claimed in claim 1, wherein this first sensor is disposed at the upper surface of this first chip.
3. IC apparatus as claimed in claim 1, wherein this first sensor is disposed at the lower surface of this first chip.
4. IC apparatus as claimed in claim 1, wherein this first sensor is disposed at the inside of this first chip.
5. IC apparatus as claimed in claim 1, wherein this first sensor is disposed at the side of this first chip.
6. IC apparatus as claimed in claim 1 also comprises:
Second sensor is configured in the lower surface and the upper surface of this chip respectively with this first sensor, and this second sensor is also in order to the resistance value of this first chip of sensing, and produces second group of sensing signal; And
Second lead is right, respectively this second sensor is coupled to the first corresponding transport element, is sent to this a plurality of first output terminals this second group of sensing signal seen through the first corresponding transport element with the first corresponding projection.
7. IC apparatus as claimed in claim 6, wherein this second sensor is with respect to the position of this first sensor at this first chip upper surface in the position of this first chip lower surface.
8. IC apparatus as claimed in claim 1 also comprises:
Second chip has a plurality of second vias, and is stacked on this first chip through a plurality of second projections, wherein each this a plurality of second projections corresponding respectively electrically connect these a plurality of first transport elements one of them;
A plurality of second transport elements, correspondence is formed on these a plurality of second vias in one of them respectively, and electrically connects these a plurality of second projections;
The 3rd sensor is configured on this second chip, in order to the resistance value of this second chip of sensing, and produces the 3rd group of sensing signal;
Privates is right; The 3rd sensor electrically is connected to the second corresponding transport element, is sent to this a plurality of first output terminals with second projection that the 3rd group of sensing signal is seen through the second corresponding transport element, correspondence, corresponding first transport element and the first corresponding projection.
9. IC apparatus as claimed in claim 1, wherein these a plurality of first output terminals are configured on this substrate and this identical surface of a plurality of first projections.
10. IC apparatus as claimed in claim 1 also comprises:
A plurality of first weld pads are configured in respectively on these a plurality of first output terminals; And
A plurality of privates should be electrically connected to this a plurality of first projections by a plurality of first weld pads respectively.
11. IC apparatus as claimed in claim 1 also comprises:
A plurality of second output terminals are configured on this substrate and these a plurality of first projection different surface; And
A plurality of second weld pads are configured in respectively on these a plurality of second output terminals.
12. IC apparatus as claimed in claim 11, wherein this substrate also has:
A plurality of the 3rd vias;
A plurality of the 3rd transport elements, correspondence is formed on these a plurality of the 3rd vias in one of them respectively, and respectively the 3rd transport element respectively correspondence couple these a plurality of first projections one of them; And
A plurality of the 5th leads should be electrically connected to this a plurality of second weld pads by a plurality of the 3rd transport elements respectively.
13. a measuring system is applicable to the IC apparatus with stacked structure, it has substrate and a plurality of chip, and these a plurality of chips are stacked on this substrate in regular turn, and this measuring system comprises:
First sensor; Electrically connect these a plurality of chips one of them; In order to the resistance value of the corresponding chip of sensing, and produce first group of sensing signal, wherein each these a plurality of chip has a plurality of first vias; A plurality of first transport elements then respectively correspondence be formed on these a plurality of first vias in one of them, make this a plurality of chips see through these a plurality of first transport elements and this substrate of a plurality of projection electric connection;
First lead is right, and this first sensor is electrically connected to the first corresponding transport element, is sent to a plurality of first output terminals on this substrate this first group of sensing signal seen through the first corresponding transport element with corresponding projection; And
Analysis module electrically connects this a plurality of first output terminals, and receives and analyze first group of sensing signal exporting from this output terminal.
14. measuring system as claimed in claim 13 is the stress/strain measuring system.
15. measuring system as claimed in claim 13, wherein this first sensor is disposed at the upper surface of corresponding chip.
16. measuring system as claimed in claim 13, wherein this first sensor is disposed at the lower surface of corresponding chip.
17. measuring system as claimed in claim 13, wherein this first sensor is disposed at the inside of corresponding chip.
18. measuring system as claimed in claim 13, wherein this first sensor is disposed at the side of corresponding chip.
19. measuring system as claimed in claim 13, wherein this analysis module changes in order to the stress/strain of detecting this chip.
20. measuring system as claimed in claim 13 wherein also has on this substrate:
A plurality of first weld pads are configured in this a plurality of first output terminals; And
A plurality of privates should be electrically connected to this a plurality of projections by a plurality of first weld pads.
21. measuring method; Be applicable to and measure the inner chip of IC apparatus; This chip then sees through a plurality of projections and is stacked on the substrate, and this chip has a plurality of vias, and disposes transport element in each these a plurality of via respectively; And respectively corresponding electrically connect these a plurality of projections one of them, and this measuring method comprises the following steps:
Measure the resistance value of the first surface of this chip, and produce first group of sensing signal;
See through corresponding transport element and this first group of sensing signal is sent to a plurality of first output terminals on this substrate with corresponding projection;
Receive this first group of sensing signal through these a plurality of first output terminals, to obtain the resistance value of this first surface.
22. measuring method as claimed in claim 21 also comprises the variation according to the resistance value of this first surface, and measures the stress/strain that this first surface bears.
23. measuring method as claimed in claim 21 also comprises the following steps:
Measure the resistance value of the second surface of this chip, and produce second group of sensing signal;
See through corresponding transport element and this second group of sensing signal is sent to these a plurality of first output terminals on this substrate with corresponding projection;
Receive this second group of sensing signal through these a plurality of first output terminals, to obtain the resistance value of this second surface.
24. measuring method as claimed in claim 23 also comprises the variation according to the resistance value of this second surface, and measures the stress/strain that this second surface bears.
25. measuring method as claimed in claim 23 also comprises the variation according to the resistance value of this first surface and this second surface, and measure the stress/strain that this chip is born in three-dimensional.
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| TWI439704B (en) * | 2011-04-22 | 2014-06-01 | Univ Nat Chiao Tung | Structure for measuring bump resistance and package substrate comprising the same |
| US8779553B2 (en) * | 2011-06-16 | 2014-07-15 | Xilinx, Inc. | Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone |
| US9502390B2 (en) * | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
| JP6198804B2 (en) * | 2015-12-01 | 2017-09-20 | 日本写真印刷株式会社 | Strain sensor for multipoint measurement and its manufacturing method |
| CN116359715B (en) * | 2023-05-26 | 2023-11-03 | 南京芯驰半导体科技有限公司 | Multi-chip testing method and device, electronic equipment and storage medium |
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Non-Patent Citations (2)
| Title |
|---|
| Jeffrey C. etc..Silicon Piezoresistive Stress Sensors and Their.《IEEE SENSORS JOURNAL》.2001,第1卷(第1期),第14-30页. |
| Silicon Piezoresistive Stress Sensors and Their;Jeffrey C. etc.;《IEEE SENSORS JOURNAL》;20010630;第1卷(第1期);第14-30页 * |
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