GB2353401A - An integrated circuit package incorporating a capacitive sensor probe - Google Patents

An integrated circuit package incorporating a capacitive sensor probe Download PDF

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Publication number
GB2353401A
GB2353401A GB9927423A GB9927423A GB2353401A GB 2353401 A GB2353401 A GB 2353401A GB 9927423 A GB9927423 A GB 9927423A GB 9927423 A GB9927423 A GB 9927423A GB 2353401 A GB2353401 A GB 2353401A
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GB
Grant status
Application
Patent type
Prior art keywords
probe
integrated circuit
conductive
layer
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9927423A
Other versions
GB9927423D0 (en )
Inventor
Nigel Stuart Priest
William Thomas Phillips
Emsley Douglas Dacres
Graham Brian Hollands
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3Com Corp
Original Assignee
3Com Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • G01R31/312Contactless testing by capacitive methods
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

A probe (18) for capacitative sensing is provided within a semiconductor package, thereby enhancing sensitivity and improving 'line of sight' for capacitative testing. The probe may be formed as part of a signal layer in a multi-layer package or as part of any layer that is electrically insulated from those elements to be tested by capacitative coupling.

Description

ELECTRONIC CIRCUIT INCLUDING CAPACITATIVE SENSING PROBE AND 1NIPROVED

N1ETHODS OF TESTING.

Field of the Invention

This invention relates to packages for semiconductor die elements and to electronic circuits. The invention has particular, but not exclusive, application to multi-layer electronic devices comprising at least one signal layer constituted by a printed or integrated circuit. Typically such devices include insulating layers, power layers and a heat sink or heat spreader The present invention concerns an improved construction of such a multi-layer device to render it more easily testable, and the technique may also be applied more generally to other package types.

Z_ BackRround to the Invention Fabrication of semiconductor components falls broadly into two stages. First is the fabrication of the semiconductor die and its associated metallisation. This is followed by mounting and electrical connection of the die to some kind of package that is suitable for handling and incorporation into larger circuit structures. Packages may include lead frames or other structures that have leads or terminals extending outwardly from the package. Other structures may have the outer terminals in the form of a grid of balls I Packages may include other elements of circuitry, for example as in a multi-layer electronic device package in which a semiconductor die is mounted alongside a multi layer stack that includes printed or integrated circuit layers (often called 'sio'nal' lavers), a ground and/or power plane and a ball grid array. These various conductive layers are separated by insulating layers and the balls of the array interconnect by way of vertical traces extending through vias to the individual parts or layers to which they make predetermined contact.

Testing is a customary and important adjunct to the manufacturing and packaging Z process for electronic circuits. Different methods of testing have been devised and are in -2 use at the present time. One method, generally known as vector testing, requires tile 1 application of a large multiplicity of sets of binary signals (the vectors) to the input terminals of the circuit and the obtaining of the relevant sets of outputs. For circuits of any complexity, the vector testing mode is complex and often lengthy, and has the general -5 n _:1 disadvantage that the output vectors do not necessarily indicate directly the nature and location of a fault that causes them to depart from the vector values which would be produced if the circuit were operative in a fully correct manner.

Another known form of testing, described for example in United States patent US Z 52743-36, is a capacitative jnethod wherein a plurality of spring loaded conductive probes (known as a 'bed of nails') make selective ohmic contact directly with a device's input and output pins on one surface of a multi-layer device. A capacitative probe is constituted by an external plate, suspended over or otherwise separated from the circuit. The capacitance between a selected pin and the probe can be measured by stimulation from an AC source. Such a technique is useful for in circuit testing because if a terminal pin is not properly soldered to its trace on the printed circuit board, there is a reduction in capacitance in series with the capacitance formed with the capacitative probe. This change in capacitance may readily be detected and used to determine whether pins make proper connection (by means of adequate soldering) with the printed circuit, by for example discriminating between the actual measured capacitance and an expected or computed value.

One advantage of a capacitative sensing technique of this nature is that no knowledge of the core functionality of the device is required. The technique depends only on the physical properties of the packaging. It is simpler and in general much more rapid than vector' testing. Nevertheless, there are practical difficulties which render such a capacitative measuring technique potentially unsuitable. In particular, increasing miniaturization renders the technique less suitable, owing to the difficulty of determining the precise location of the fault. Furthermore, if the device includes a ground plane or for example a heat spreader which is not electrically isolated from other planes in the device, the obtaining of accurate results or occasionally any meaningful results from a capacitatively coupled test probe are difficult. This is particularly the case with mUlti-layer structures having ball arid array external connection where 'line of sight' from the probe to the desired conductive element is more likely to be obscured by virtue of tile vertical stacking arrangement. Thus despite its convenience and rapidity, capacitatively coupled probe testing appears to be unavailable for a variety of circuits owing to their construction.

Summary of the Invention

The present invention has as its main object a new construction for packages and circuits so as to make them better adapted for vectorless test techniques in general and capacitatively coupled testijig in particular.

1 The invention is based on the location within a device package of a capacitative sensor probe such as a conductive sensing plane or plate which is not electrically utilised in the t) 1 circuits of the device and is very preferably isolated conductively ftom any other plates, planes or circuits in the device. Such a probe can be disposed anywhere within the package, including as part of or adjacent any signal plane of the device and accordingly not be blocked by a ground or power plane or a heat spreader. The probe can be connected or tracked internally within the device to an externally accessible connection, such as a solder ball or lead, on an external face of the package in order to enable its connection to the circuit required for the application and sensing of a signal intended for measurement of capacitative values between the probe and other heads or terminals connected to the device. The probe may be a sensing plane that is part of a multi-layer stack, or be laterally displaced with respect to such a stack.

Brief Description of the Drawin

The invention is now described by way of example, with reference to the accompanying drawings in which..

Figure 1, illustrates in simplified form, and not to scale, a crosssection through a multilayer electronic circuit device embodying the present invention.

Figure 2 is a schematic diagram of a plan layout of a device as shown in Figure 1 1 W C) Figure 3) is a schematic diagram of a lead frame incorporating a sensor probe., Figure 4 is an alternative embodiment of lead frame package; and Figure 5 is a further alternative lead frame embodiment.

Detailed Description of Preferred Embodiment

Figures 1 and 2 illustrate, by way of example, the general structure of a multi-layer electronic circuit package which is particularly adapted in accordance with the invention for capacitative testing. The invention is described in the context of this type of package as they exhibit particular testin... problems. The package illustrated is an example only, the is package shape, detail and layer construction may vary according to design requirements.

Multi-die packages may also be constructed and the technique described can be applied in any situation or type of packaging with a variety of external connecting means such as balls, pins or leads.

The device 1 has an uppermost insulating layer 2 which is the support for a ball Orld array composed of a multiplicity of solder balls which are connected by 'vertical' traces, extending through vias in the relevant layers, to underlying layers of the device These traces should be without electrical contact to any conductive layer except with the respective layer to which they make predetermined connection Beneath the insulating layer 2 is a conductive ground layer or plane 4. Beneath this.layer is a further insulating layer 5. The next underlying layer 6 is a 'signal' layer constituted by a printed or integrated circuit. The functionality of this circuit is of no particular importance to the invention.

Underlying the signal layer 6 is a further insulating layer 7. A conductive layer 8, hereinafter called 'sensing layer' is disposed below the insulating layer 7, the sensing layer 8 being thereby isolated conductively from the signal layer 6 but being capacitatively 1 coupled to it. Although there could be a respective sensing layer for each signal layer, in this example the sensing layer also serves for capacitative sensing of a second signal layer which underlies the insulating layer 8 and is separated from it by an insulating layer 9.

A yet further insulating layer 11 is disposed between the second signal layer 10 and a power layer 12 (which has a layout of the power rail VCC for the various circuits).

Beneath the power layer is another insulating layer 133 which is in this example substantially co-planer with a power ring 14. Layer 13) and ring 14 are disposed on a 1 cavity layer 15 made for example of copper. This layer is separated by an insulating layer 16 from a conductive heat preader 17.

Also on the heat spreader in this example is a semiconductor die 18, which is secured to the heat spreader by an adhesive layer 19, in this instance the heat spreader constituting a die attachment location or pad.

Conductive leads in the lead frame of the die are, in this example, connected, according to the requirements of the circuit device, to the power ring 14, the power layer 12 and the signal layers 6 and 10 by means of bond wires 20.

The foregoing is given by way of example only. It is not necessary that there be a multiplicity of signal layers. Moreover, the sense layer 8 need not be, as shown, in the middle of the layers making up the device but may, in general, be anywhere in the layers provided that, very preferably, it is adjacent, apart from separating insulation, to one or more of the signal layers. It follows that for complex devices having a multiplicity of 25 signal layers there may be more than one sense layer such as the layer 8 or the sense layer may be part of a split layer, i.e. one having separate insulated sections on the same level. The power ring 14 could be split or reassigned to constitute a probe. The layer 8 or each such layer is provided with external access by means of a wire or 30 conductive trace which extends to at least one accessible terminal, herein constituted by one or more of the solder balls (3a) in the ball grid array (3).

It will be apparent that the sense layer 8 may be used for capacitative testing of, for example, the terminal connections such as the connection of solder ball 3b to signal layer 6, taking the place of the capacitative probe which is used in conjunction with the 'bed of nails' described in the aforementioned US patent. The usefulness of the known method is not thereby limited by the disposition of the ground plane or the heat spreader. However, the invention is not, obviously, limited to that method of testing.

Conventional features such as encapsulation have been omitted for the sake of brevity and simplicity.

In a modification, an amplifier which may be required for the performance of a capacitative test could be incorporated into the device (such as on die 18) to minimize the external components required for such a test.

It will be appreciated that the probe may be located in or on any part of the package where I real estate' permits, which may include surfaces not normally utlilised and can vary depending upon the type of package. It is possible, as described later with reference to Figures 3) to 5, to include the probe as part of a lead frame, for example as a separate pad provided and supported similarly to a die attachment pad, or as a separate component such as an insulated supporting ring mounted beneath the lead ends. The important feature whatever the package type is that the signals or traces to be verified using capacitative sensing have a clear 'sight' of the probe without an intervening (conductive) ground or power plane or the like.

Figures 3 3 to 5 illustrate schematically how the invention may. be applied in a simple lead -:1 frame package. In many instances lead frames are more complex and may include several attachment pads for multiple die assemblies or for use as heat sinks.

In Figure 33 a lead frame, illustrated generally by references 30 has a die attachment pad 1 31, a plurality of leads '32 and a capacitative sensor probe 33, surrounding the die attachment pad. As illustrated the capacitative sensor probe is shown directly connected in an integral manner with a lead part 34, but this is not essential, the probe could be wire bonded to any lead. However, integral lead may enable utilisation as a heat sink. Dotted outline 35 shows the location of encapsulation that normally follows a wire bonding process.

Figure 4 is similar to Figure 33, but shows a different confi uration for the probe. In this W 11) 9 instance the probe does not completely surround the die attachment pad and has a form i ilar to an adjacent pad. To maximise wire crossings, the probe extends around more simi three sides of the die attachment pad.

Figure 5 illustrates a further alternative structure where the probe 313 is in the form of a ring beneath the leads 32. An insulating layer is disposed over the probe to prevent contact with the leads. As an alternative the probe could be positioned over the top of the leads and also optionally utilised as a spacer to inhibit wire sweep.

In the embodiments of Figures 33 and 4, and variations of that general type, the sensor probe may be part of a multi-layer structure on overlie such a structure.

Having described the incorporation of a probe into multi-layer and lead frame type packages, it will be appreciated that any package may be modified in this way or have its existing structures reassigned and suitably connected. As any fabrication stage has an attendant overhead, inclusion of the probe as part of other structures may be desirable.

Apart from heat sinks and support structures other suitable parts that can be modified in this way include protective, shielding or anti-tamper layers.

Location of the probe within the package provides good capacitative linkage. Two factors which assist in this are the line of sight being unlikely to be completely obscured and the relatively close proximity of the probe to other parts of the package being tested. Typically when utilising the prior art external probes, capacitative measurements are of the general order, say, of around 20 to 200 femtofarads. In the present invention, when testing to a comparable conductive route, the reduced line of sight distance will render a large 1 measurement raising the previous 20 femtofarads to 40 femtofarads, and putting within C.

resolution linkages that previously were below a useful or measurable level. The value of the capacitance measurement, compared with the expected value, can also be indicative of the nature and location of a fault.

A further modification of the technique described in detail in our copending application, is to incorporate the probe into the semiconductor die or its metallisation.

-g-

Claims (13)

Clainis
1. An integrated circuit package comprising:
a mounting for a semiconductor die; a plurality of exposed terminal conductors (3:)); a plurality of conductive linkages extending into the package from the exposed terminal conductors; and a conductive, capacitative sensing probe disposed in the package and electrically connected to at least one (3a) of said terminal conductors, the sensing probe being capacitatively related to at least some of the conductive linkages.
2. An integrated circuit package according to claim 1 in which the conductive linkages include a multiplicity of stacked conductive layers (4, 6, 8, 10, 12) including at least one signal layer (6) and the sensing probe is capacitatiVely coupled to the signal layer.
-33. An integrated circuit package according to claim 2 in which the sensing probe is a conductive layer (8) disposed as one of the stacked conductive layers.
4. An integrated circuit package according to claim 2 in which the sensing probe is a conductive layer disposed laterally adjacent the stacked conductive layers
5. An integrated circuit package according to claim 1 in which the probe forms part of a C> lead frame assembly.
6. An integrated circuit package according to claim 1 in which the probe is formed as a ring, 1
7. An integrated circuit package according to claim 6 in which the probe is disposed W adjacent the die mounting area.
8. An integrated circuit package according to claim 1 in which the probe forms part of a die mountine, assembly.
n
9. An integrated circuit package in which the probe is disposed such that bonding wires connecting a die to the conductive linkages pass over at least a part of the probe.
1. 1
10. An integrated circuit package in which the probe also comprises a protective or tamper 1 1 resistant structure.
11. An integrated circuit comprising:
a semiconductor die; a package for the semiconductor die., a plurality of exposed terminal conductors (3), a plurality of conductive linkages extending into the package and to the die from the exposed terminal conductors; and a conductive capacitative sensing probe disposed in the package and electrically connected 1 to at least one (35a) of the terminal conductors, the sensing probe being capacitatively related to at least some of the conductive linkages.
12. An inte(.),rated circuit according to claim 11 in which the probe is part of the package.
1
13. An integrated circuit according to claim 11 in which the probe is part of the die.
1
GB9927423A 1999-08-20 1999-11-20 An integrated circuit package incorporating a capacitive sensor probe Withdrawn GB2353401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9919626A GB2353399A (en) 1999-08-20 1999-08-20 Testing printed or integrated circuits

Publications (2)

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GB9927423D0 true GB9927423D0 (en) 2000-01-19
GB2353401A true true GB2353401A (en) 2001-02-21

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Family Applications (3)

Application Number Title Priority Date Filing Date
GB9919626A Withdrawn GB2353399A (en) 1999-08-20 1999-08-20 Testing printed or integrated circuits
GB9927423A Withdrawn GB2353401A (en) 1999-08-20 1999-11-20 An integrated circuit package incorporating a capacitive sensor probe
GB9927426A Withdrawn GB2353402A (en) 1999-08-20 1999-11-20 A semiconductor die structure incorporating a capacitive sensing probe

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB9919626A Withdrawn GB2353399A (en) 1999-08-20 1999-08-20 Testing printed or integrated circuits

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB9927426A Withdrawn GB2353402A (en) 1999-08-20 1999-11-20 A semiconductor die structure incorporating a capacitive sensing probe

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2405215A (en) * 2003-08-21 2005-02-23 Micron Technology Inc Testing integrated circuits using capacitive coupling
US6937067B2 (en) 2003-05-20 2005-08-30 Micron Technology, Inc. System and method for balancing capacitively coupled signal lines
US7462935B2 (en) 2003-10-13 2008-12-09 Micron Technology, Inc. Structure and method for forming a capacitively coupled chip-to-chip signaling interface
EP2108150A1 (en) * 2007-01-25 2009-10-14 Verifone, Inc. Anti-tamper protected enclosure
US8988233B2 (en) 2010-03-02 2015-03-24 Verifone, Inc. Point of sale terminal having enhanced security
US9013336B2 (en) 2008-01-22 2015-04-21 Verifone, Inc. Secured keypad devices
US9595174B2 (en) 2015-04-21 2017-03-14 Verifone, Inc. Point of sale terminal having enhanced security
US9691066B2 (en) 2012-07-03 2017-06-27 Verifone, Inc. Location-based payment system and method

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Publication number Priority date Publication date Assignee Title
CN100340864C (en) * 2001-08-10 2007-10-03 马尼亚发展有限公司 Apparatus and method for testing circuit board
US6734681B2 (en) 2001-08-10 2004-05-11 James Sabey Apparatus and methods for testing circuit boards
US6933730B2 (en) 2003-10-09 2005-08-23 Agilent Technologies, Inc. Methods and apparatus for testing continuity of electrical paths through connectors of circuit assemblies

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EP0277764A2 (en) * 1987-01-28 1988-08-10 Westinghouse Electric Corporation Test system for electronic devices
EP0805356A2 (en) * 1996-04-29 1997-11-05 Hewlett-Packard Company Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry

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US4229693A (en) * 1978-11-24 1980-10-21 Honeywell Information Systems Inc. Method and apparatus for capacitance testing printed circuit boards
US4565966A (en) * 1983-03-07 1986-01-21 Kollmorgen Technologies Corporation Method and apparatus for testing of electrical interconnection networks
US5124660A (en) * 1990-12-20 1992-06-23 Hewlett-Packard Company Identification of pin-open faults by capacitive coupling through the integrated circuit package

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Publication number Priority date Publication date Assignee Title
EP0277764A2 (en) * 1987-01-28 1988-08-10 Westinghouse Electric Corporation Test system for electronic devices
EP0805356A2 (en) * 1996-04-29 1997-11-05 Hewlett-Packard Company Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937067B2 (en) 2003-05-20 2005-08-30 Micron Technology, Inc. System and method for balancing capacitively coupled signal lines
US7075330B2 (en) 2003-05-20 2006-07-11 Micron Technology, Inc. System and method for balancing capacitively coupled signal lines
GB2405215A (en) * 2003-08-21 2005-02-23 Micron Technology Inc Testing integrated circuits using capacitive coupling
GB2405215B (en) * 2003-08-21 2005-09-28 Micron Technology Inc System and method for testing devices utilizing capacitively coupled signalling
US7112980B2 (en) 2003-08-21 2006-09-26 Micron Technology, Inc. System and method for testing devices utilizing capacitively coupled signaling
US7183790B2 (en) 2003-08-21 2007-02-27 Micron Technology, Inc. System and method for testing devices utilizing capacitively coupled signaling
US7274204B2 (en) 2003-08-21 2007-09-25 Micron Technology, Inc. System and method for testing devices utilizing capacitively coupled signaling
US7274205B2 (en) 2003-08-21 2007-09-25 Micron Technology, Inc. System and method for testing devices utilizing capacitively coupled signaling
US7276928B2 (en) 2003-08-21 2007-10-02 Micron Technology, Inc. System and method for testing devices utilizing capacitively coupled signaling
US7352201B2 (en) 2003-08-21 2008-04-01 Micron Technology, Inc. System and method for testing devices utilizing capacitively coupled signaling
US8049331B2 (en) 2003-10-13 2011-11-01 Micron Technology, Inc. Structure and method for forming a capacitively coupled chip-to-chip signaling interface
US7462935B2 (en) 2003-10-13 2008-12-09 Micron Technology, Inc. Structure and method for forming a capacitively coupled chip-to-chip signaling interface
US7763497B2 (en) 2003-10-13 2010-07-27 Micron Technology, Inc. Structure and method for forming a capacitively coupled chip-to-chip signaling interface
EP2108150A4 (en) * 2007-01-25 2013-12-11 Verifone Inc Anti-tamper protected enclosure
EP2108150A1 (en) * 2007-01-25 2009-10-14 Verifone, Inc. Anti-tamper protected enclosure
US9779270B2 (en) 2008-01-22 2017-10-03 Verifone, Inc. Secured keypad devices
US9013336B2 (en) 2008-01-22 2015-04-21 Verifone, Inc. Secured keypad devices
US9436293B2 (en) 2008-01-22 2016-09-06 Verifone, Inc. Secured keypad devices
US9275528B2 (en) 2010-03-02 2016-03-01 Verifone, Inc. Point of sale terminal having enhanced security
US8988233B2 (en) 2010-03-02 2015-03-24 Verifone, Inc. Point of sale terminal having enhanced security
US9691066B2 (en) 2012-07-03 2017-06-27 Verifone, Inc. Location-based payment system and method
US9595174B2 (en) 2015-04-21 2017-03-14 Verifone, Inc. Point of sale terminal having enhanced security

Also Published As

Publication number Publication date Type
GB2353399A (en) 2001-02-21 application
GB9927423D0 (en) 2000-01-19 application
GB9927426D0 (en) 2000-01-19 application
GB9919626D0 (en) 1999-10-20 application
GB2353402A (en) 2001-02-21 application

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