CN116457936A - 具有直接接合的微电子组件中的屏蔽结构 - Google Patents

具有直接接合的微电子组件中的屏蔽结构 Download PDF

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Publication number
CN116457936A
CN116457936A CN202180077797.3A CN202180077797A CN116457936A CN 116457936 A CN116457936 A CN 116457936A CN 202180077797 A CN202180077797 A CN 202180077797A CN 116457936 A CN116457936 A CN 116457936A
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China
Prior art keywords
microelectronic
shielding structure
interposer
microelectronic component
coupled
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CN202180077797.3A
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Inventor
A·A·埃尔谢尔比尼
G·S·帕斯达斯特
K·俊
钱治国
J·M·斯旺
A·阿列克索夫
S·M·利夫
M·E·卡比尔
F·艾德
K·P·奥布莱恩
H·W·田
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Intel Corp
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Intel Corp
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Publication of CN116457936A publication Critical patent/CN116457936A/zh
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Abstract

本文公开了微电子组件以及相关的设备和方法。在一些实施例中，微电子组件可以包括第一微电子部件，具有第一表面和相反的第二表面，所述第一微电子部件包括在第二表面处的第一直接接合区域，所述第一直接接合区域具有第一金属触点和在第一金属触点中的相邻第一金属触点之间的第一电介质材料；第二微电子部件，具有第一表面和相反的第二表面，所述第二微电子部件包括在第一表面处的第二直接接合区域，所述第二直接接合区域具有第二金属触点和在所述第二金属触点中的相邻第二金属触点之间的第二电介质材料，其中，所述第二微电子部件通过所述第一直接接合区域和所述第二直接接合区域耦接到所述第一微电子部件；以及在第一直接接合电介质材料中的屏蔽结构，至少部分地围绕所述第一金属触点中的一个或多个第一金属触点。

Description

具有直接接合的微电子组件中的屏蔽结构
相关申请的交叉引用
本申请要求享有于2020年12月18日提交的题为“SHIELD STRUCTURES INMICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING”的美国非临时专利申请序列号No.17/127,382的权益和优先权，其由此通过引用的方式整体并入本文。
背景技术
集成电路(IC)管芯通过直接接合彼此耦接，以改善互连间距和减小z高度。通过直接接合可实现的较小的互连间距和z高度增加了信号串扰并降低了信号性能。
附图说明
通过结合附图的以下具体实施方式，将容易理解实施例。为了便于描述，相同的附图标记表示相同的结构元件。在附图的各图中，通过示例而非限制的方式示出了各实施例。
图1是根据各种实施例的在直接接合区域中包括屏蔽结构的示例微电子组件的侧视截面图。
图2是根据各种实施例的图1的微电子组件的一部分的侧视截面分解图。
图3是根据各种实施例的在直接接合区域中包括屏蔽结构的示例微电子组件的侧视截面图。
图4A-4D是根据各种实施例的微电子部件的示例直接接合界面的俯视图。
图5A-5B是根据各种实施例的微电子组件中围绕直接接合互连的屏蔽结构的示例布置的放大三维透视图。
图6A-6G是示出根据各种实施例的微电子组件中的屏蔽直接接合互连的示例布置的俯视示意图。
图7A-7D是根据各种实施例的用于制造图3的微电子组件的示例工艺中的各个阶段的侧视截面图。
图8是根据本文公开的任何实施例的可以包括在微电子组件中的晶圆和管芯的俯视图。
图9是根据本文公开的任何实施例的可以包括在微电子组件中的IC设备的截面侧视图。
图10是根据本文公开的任何实施例的可以包括微电子组件的IC设备组件的截面侧视图。
图11是根据本文公开的任何实施例的可以包括微电子组件的示例电气设备的框图。
具体实施方式
本文公开了微电子组件以及相关的设备和方法。例如，在一些实施例中，微电子组件可以包括：第一微电子部件，具有第一表面和相反的第二表面，所述第一微电子部件包括在第二表面处的第一直接接合区域，所述第一直接接合区域具有第一金属触点和在第一金属触点中的相邻第一金属触点之间的第一电介质材料；第二微电子部件，具有第一表面和相反的第二表面，所述第二微电子部件包括在第一表面处的第二直接接合区域，所述第二直接接合区域具有第二金属触点和在所述第二金属触点中的相邻第二金属触点之间的第二电介质材料，其中，所述第二微电子部件通过所述第一直接接合区域和所述第二直接接合区域耦接到所述第一微电子部件；以及在第一直接接合电介质材料中的屏蔽结构，至少部分地围绕所述第一金属触点中的一个或多个第一金属触点。
在多管芯IC封装中经由直接接合耦接的两个或更多个管芯之间传送大量信号是具有挑战性的，这是由于这些管芯的尺寸越来越小并且管芯之间的接合界面的厚度减小(例如，管芯到管芯间隔的z高度)等。这对于具有不同操作电压和频率的管芯的堆叠以及对于混合信号管芯的堆叠(例如，射频(RF)管芯与数字管芯的堆叠)变得更加困难。常规方法试图通过增加接地连接与信号连接的比率来减少信号串扰、信号耦接和插入损耗，这可能降低带宽密度、增加管芯面积、并且由于增加的信号距离而增加延迟。其他常规方法包括在管芯上添加附加的隔离接地层，这增加了管芯的成本、尺寸和良率，或者增加了管芯到管芯间隔的z高度，这增加了成本并限制了互连间距。尽管可针对性能对堆叠管芯的所有组合进行建模，但大量可能组合是时间和成本过高的。本文公开的微电子组件中的各种微电子组件通过提供隔离接地平面来抑制管芯到管芯信号耦接，可以表现出更好的信号性能和更少的串扰，同时相对于常规方法减小封装的尺寸。本文公开的微电子组件对于计算机、平板电脑、工业机器人和消费电子产品(例如，可穿戴设备)中的小型和薄型应用可能是特别有利的。
在下面的具体实施方式中，参考了形成其一部分的附图，其中，相同的附图标记始终表示相同的部件，并且其中，通过图示的方式示出了可以实践的实施例。应当理解，可以利用其他实施例，并且可以在不脱离本公开内容的范围的情况下进行结构或逻辑改变。因此，以下具体实施方式不应被视为具有限制意义。
可以以最有助于理解所要求保护的主题的方式将各种操作依次描述为多个分立的动作或操作。然而，描述的顺序不应被解释为暗示这些操作必须是顺序相关的。特别地，这些操作可以不以呈现的顺序来执行。所描述的操作可以以与所描述的实施例不同的顺序来执行。在附加实施例中，可以执行各种附加操作，和/或可以省略所描述的操作。
为了本公开内容的目的，短语“A和/或B”意指(A)、(B)或(A和B)。为了本公开内容的目的，短语“A、B和/或C”意指(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。附图不一定按比例绘制。尽管许多附图示出了具有平坦壁和直角拐角的直线结构，但这仅仅是为了便于说明，并且使用这些技术制成的实际设备将表现出圆角、表面粗糙度和其他特征。
本描述使用短语“在一实施例中”或“在实施例中”，其可以各自指代相同或不同实施例中的一个或多个。此外，如关于本公开内容的实施例所使用的术语“包括”、“包含”、“具有”等是同义的。当用于描述尺寸范围时，短语“在X和Y之间”表示包括X和Y的范围。本文可以使用术语“顶部”、“底部”等来解释附图的各种特征，但是这些术语仅仅是为了便于讨论，并不意味着期望或要求的取向。如本文所使用的，术语“厚度”是指沿z轴测量的某个元件或层的尺寸，术语“宽度”是指沿y轴测量的某个元件或层的尺寸，而术语“长度”是指沿x轴测量的某个元件或层的尺寸。尽管本文中可以单数形式提及某些元件，但此类元件可以包括多个子元件。例如，“电介质材料”可以包括一种或多种电介质材料。如本文所使用的，“导电触点”可以指代用作不同部件之间的电接口的导电材料(例如，金属)的一部分；导电触点可以凹入部件的表面中、与部件的表面齐平或远离部件的表面延伸，并且可以采用任何合适的形式(例如，导电焊盘或插座，或者导电线或过孔的一部分)。为了便于讨论，图4A-4D的附图在本文中可以被称为“图4”，并且图5A-5B的附图在本文中可以被称为“图5”等。
图1是根据各种实施例的在直接接合区域处包括屏蔽结构的微电子组件100的侧视截面图。微电子组件100可以包括具有有机材料106的中介层150、经由第一直接接合区域130-1耦接到中介层150的第一微电子部件102-1、经由第二直接接合区域130-2耦接到中介层150的第二微电子部件102-2、经由具有屏蔽结构115-1的直接接合区域130-3耦接到第一微电子部件102-1的第三微电子部件102-3，以及经由具有屏蔽结构115-2的直接接合区域130-4耦接到第二微电子部件102-2的第四微电子部件102-4。微电子组件100还可以包括模制材料126、支撑部件182、底部填充材料138、热传递结构152和热界面材料(TIM)154。在图1中示出了包括在微电子组件100中的多个元件，但是在微电子组件100中可以不存在多个这些元件。例如，在各实施例中，可不包括模制材料126、底部填充材料138、支撑部件182、底部填充材料138、热传递结构152、和/或热界面材料(TIM)154。此外，图1示出了为了便于说明而从后续附图中省略的多个元件，但是这些元件可以包括在本文公开的任何微电子组件100中。此类元件的示例包括模制材料126、底部填充材料138、支撑部件182、底部填充材料138、热传递结构152、和/或热界面材料(TIM)154。图1的微电子组件100的许多元件包括在附图中的其他附图中；在讨论这些附图时不重复对这些元件的讨论，并且这些元件中的任何元件可以采用本文公开的任何形式。在一些实施例中，本文公开的微电子组件100中的各个微电子组件可以用作系统级封装(SiP)，其中，包括具有不同功能的多个微电子部件102。在这样的实施例中，微电子组件100可以被称为SiP。
微电子组件100可以包括通过直接接合(DB)区域130-1耦接到微电子部件102-1的中介层150。特别地，如图2所示，DB区域130-1可以包括在中介层150的顶表面处的DB界面180-1A，其中，DB界面180-1A包括一组导电DB触点110和在DB界面180-1A的DB触点110周围的DB电介质108。DB区域130-1还可以包括在微电子部件102-1的底表面处的DB界面180-1B，其中，DB界面180-1B包括一组DB触点110和在DB界面180-1B的DB触点110周围的DB电介质108。中介层150的DB界面180-1A的DB触点110可以与微电子部件102-1的DB界面180-1B的DB触点110对准，使得在微电子组件100中，微电子部件102-1的DB触点110与中介层150的DB触点110接触。在图1的微电子组件100中，中介层150的DB界面180-1A可以与微电子部件102-1的DB界面180-1B接合(例如，电气地和机械地)，以形成将中介层150和微电子部件102-1耦接的DB区域130-1，如下面进一步讨论的。更一般地，本文公开的DB区域130可以包括接合在一起的两个互补DB界面180；为了便于说明，许多后续附图可以省略DB界面180的标识以提高附图的清晰度。
如本文所使用的，术语“直接接合”用于包括金属-金属接合技术(例如，铜-铜接合，或其中首先使相对的DB界面180的DB触点110接触，然后经受加热和/或压缩的其他技术)和混合接合技术(例如，其中首先使相对的DB界面180的DB电介质108接触，然后经受加热并且有时经受压缩的技术，或者其中使相对的DB界面180的DB触点110和DB电介质108基本上同时接触，然后经受加热和压缩的技术)。在这种技术中，使一个DB界面180处的DB触点110和DB电介质108分别与另一个DB界面180处的DB触点110和DB电介质108接触，并且可以施加升高的压力和/或温度以使接触的DB触点110和/或接触的DB电介质108接合。在一些实施例中，可以在不使用中间焊料或各向异性导电材料的情况下实现这种接合，而在一些其他实施例中，可以在DB互连中使用薄的焊料帽以适应平面性，并且这种焊料可以在处理期间变成DB区域130中的金属间化合物(IMC)。DB互连能够可靠地传导比其他类型的互连更高的电流；例如，当电流流动时，一些常规焊料互连可能形成大量脆性IMC，并且可以约束通过这样的互连提供的最大电流以减轻机械故障。尽管图1和图2将DB电介质108示出为完全沿着中介层150的整个第二表面151-2延伸，但是在一些实施例中，DB电介质108可以仅沿着中介层150的第二表面151-2的一部分延伸，使得DB电介质108仅在DB区域130内。
DB电介质108可以包括一种或多种电介质材料，例如一种或多种无机电介质材料。例如，DB电介质108可以包括硅和氮(例如，以氮化硅的形式)；硅和氧(例如，以氧化硅的形式)；硅、碳和氮(例如，以碳氮化硅的形式)；碳和氧(例如，以碳掺杂氧化物的形式)；硅、氧和氮(例如，以氮氧化硅的形式)；铝和氧(例如，以氧化铝的形式)；钛和氧(例如，以氧化钛的形式)；铪和氧(例如，以氧化铪的形式)；硅、氧、碳和氢(例如，以原硅酸四乙酯(TEOS)的形式)；锆和氧(例如，以氧化锆的形式)；铌和氧(例如，以氧化铌的形式)；钽和氧(例如，以氧化钽的形式)；以及它们的组合。
DB触点110可以包括柱、焊盘或其他结构。尽管在附图中以相同的方式在DB区域130的两个DB界面180处示出的DB触点110在两个DB界面180处可以具有相同的结构，或者在不同的DB界面180处的DB触点110可以具有不同的结构。例如，在一些实施例中，一个DB界面180中的DB触点110可以包括金属柱(例如，铜柱)，并且互补DB界面180中的互补DB触点110可以包括凹入电介质中的金属焊盘(例如，铜焊盘)。DB触点110可以包括任何一种或多种导电材料，诸如铜、锰、钛、金、银、钯、镍、铜和铝(例如，以铜铝合金的形式)、钽(例如，钽金属、或以氮化钽的形式的钽和氮)、钴、钴和铁(例如，以钴铁合金的形式)、或任何前述的任何合金(例如，以锰镍铜合金的形式的铜、锰和镍)。在一些实施例中，DB界面180的DB电介质108和DB触点110可以使用低温沉积技术(例如，在低于250摄氏度或低于200摄氏度的温度下进行沉积的技术)来制造，诸如低温等离子体增强化学气相沉积(PECVD)。
图1和图2还示出了通过DB区域130-2(经由DB界面180-2A和180-2B，如图2所示)耦接到中介层150的微电子部件102-2。图1还示出了通过DB区域130-3耦接到微电子部件102-1的微电子部件102-3和通过DB区域130-4耦接到微电子部件102-2的微电子部件102-4，其包括类似的DB界面(未标记)。尽管图1示出了通过DB区域130耦接到中介层150和其他微电子部件102的特定数量的微电子部件102，但是该数量和布置仅仅是说明性的，并且微电子组件100可以包括通过DB区域130耦接到中介层150和其他微电子部件102的任何期望数量和布置的微电子部件102。尽管单个附图标记“108”用于指代多个不同DB界面180(和不同DB区域130)的DB电介质，但这仅仅是为了便于说明，并且不同DB界面180(甚至在单个DB区域130内)的DB电介质108可以具有不同的材料和/或结构。类似地，尽管单个附图标记“110”用于指代多个不同DB界面180(和不同DB区域130)的DB触点，但这仅仅是为了便于说明，并且不同DB界面180(甚至在单个DB区域130内)的DB触点110可以具有不同的材料和/或结构。
图1示出了在单个DB接合区域130内具有两个屏蔽结构115的微电子组件100(例如，DB接合区域130-3内的微电子部件102-1上的屏蔽结构115-1A和微电子部件102-3上的屏蔽结构115-1B，以及DB接合区域130-4内的微电子部件102-2上的屏蔽结构115-2A和微电子部件102-4上的屏蔽结构115-2B)，DB接合区域130可包括单个屏蔽结构115(例如，屏蔽结构115-1A或115-1B、或屏蔽结构115-2A或115-2B)。例如，屏蔽结构115可以由任何适当的导电材料形成，例如，铜、银、镍、金、铝、或其他金属或合金。屏蔽结构115可以使用任何合适的工艺来形成，包括例如参考图7描述的工艺。屏蔽结构115可以形成为至少部分地围绕DB触点110。在一些实施例中，屏蔽结构115可以形成为完全围绕单个DB触点110。如下面参考图6详细描述的，屏蔽结构115可以是连续结构或非连续结构。屏蔽结构115可耦接到微电子部件102上的接地连接部(例如，到耦接到微电子部件102上的接地连接部的DB触点110)。屏蔽结构115可以具有任何合适的尺寸和形状以屏蔽DB触点110，以减少经由微电子部件102传输的信号之间的插入损耗和/或串扰，并且可以减少信号性能的劣化。在一些实施例中，微电子部件102可以以高速信令频率(例如，50GHz或更高的高速信令频率，或100GHz或更高的超高速信令频率)操作。高速信令可能更容易发生信号耦合和串扰，这可以通过接地屏蔽来减少。尽管图1示出了两个屏蔽结构，但是微电子组件100可以在一个DB接合区域内包括一个或多个屏蔽结构。
中介层150可以包括绝缘材料106(例如，在多层中形成的一种或多种电介质材料，如本领域中已知的)和穿过绝缘材料106的一个或多个导电通路112(例如，包括导电线114和/或导电过孔116，如图所示)。在一些实施例中，中介层150的绝缘材料106包括无机电介质材料，诸如硅和氮(例如，以氮化硅的形式)；硅和氧(例如，以氧化硅的形式)；硅和碳(例如，以碳化硅的形式)；硅、碳和氧(例如，以碳氧化硅的形式)；硅、碳和氮(例如，以碳氮化硅的形式)；碳和氧(例如，以碳掺杂氧化物的形式)；硅、氧和氮(例如，以氮氧化硅的形式)；或硅、氧、碳和氢(例如，以原硅酸四乙酯(TEOS)的形式)；以及它们的组合。在一些实施例中，中介层150的绝缘材料106包括绝缘金属氧化物，诸如铝和氧(例如，以氧化铝的形式)；钛和氧(例如，以氧化钛的形式)；铪和氧(例如，以氧化铪的形式)；锆和氧(例如，以氧化锆形式)；铌和氧(例如，以氧化铌的形式)；或钽和氧(例如，以氧化钽的形式)；以及它们的组合。在一些实施例中，中介层150可以是基于半导体的(例如，基于硅的)或基于玻璃的。在一些实施例中，中介层150是硅晶圆或管芯。在一些实施例中，中介层150可以是绝缘体上硅(SOI)，并且还可以包括硅和锗(例如，以硅锗的形式)、镓和氮(例如，以氮化镓的形式)、铟和磷(例如，以磷化铟的形式)等的层。在一些实施例中，中介层150的绝缘材料106可以是有机材料，诸如聚酰亚胺或聚苯并恶唑，或者可以包括具有填充材料(其可以是无机的，诸如氮化硅、氧化硅或氧化铝)的有机聚合物基质(例如，环氧化物)。在一些这样的实施例中，中介层150可以被称为“有机中介层”。在一些实施例中，中介层150的绝缘材料106可以设置在多层有机堆积膜中。制造有机中介层150可以比基于半导体或基于玻璃的中介层更便宜，并且由于有机绝缘材料106的低介电常数和可以使用的较粗的线(允许改善的功率输送、信令和潜在的热益处)，有机中介层150可以具有电性能优点。有机中介层150还可以具有比基于半导体的中介层(其受到用于图案化的掩模版(reticle)的尺寸的限制)可以实现的更大的覆盖区。此外，与约束基于半导体或玻璃的中介层的设计规则相比，有机中介层150可能受到较少限制的设计规则，从而允许使用诸如非曼哈顿(non-Manhattan)布线的设计特征(例如，不限于使用一层用于水平互连并且使用另一层用于垂直互连)并且避免诸如穿硅过孔或穿玻璃过孔的穿衬底过孔(TSV)(其可能在可实现的间距方面受到限制，并且可能导致不太期望的功率输送和信令性能)。包括有机中介层的常规集成电路封装已经受限于基于焊料的附接技术，其可能对可实现的间距具有下限，这排除了使用常规基于焊料的互连来实现下一代设备所需的精细间距。如本文所公开的，在具有直接接合的微电子组件100中利用有机中介层150可以利用有机中介层的这些优点与通过直接接合可实现(并且先前仅在使用基于半导体的中介层时可实现)的超细间距(例如，下面讨论的间距128)的组合，并且因此可以支持可以实现常规方法无法实现的封装系统竞争性能和能力的大型和复杂的管芯复合体的设计和制造。
在其他实施例中，中介层150的绝缘材料106可以包括阻燃等级4材料(FR-4)、双马来酰亚胺三嗪(BT)树脂、或低k或超低k电介质(例如，碳掺杂电介质、氟掺杂电介质、和多孔电介质)。当使用标准印刷电路板(PCB)工艺形成中介层150时，绝缘材料106可以包括FR-4，并且中介层150中的导电通路112可以由通过FR-4的堆积层分离的图案化铜片来形成。在一些这样的实施例中，中介层150可以被称为“封装衬底”或“电路板”。
在一些实施例中，中介层150中的一个或多个导电通路112可以在中介层150的顶表面处的导电触点(例如，DB触点110之一)和中介层150的底表面处的导电触点118之间延伸。在一些实施例中，中介层150中的一个或多个导电通路112可以在中介层150的顶表面处的不同导电触点之间(例如，在潜在地在不同DB区域130中的不同DB触点110之间，如下面进一步讨论的)延伸。在一些实施例中，中介层150中的一个或多个导电通路112可以在中介层150的底表面处的不同导电触点118之间延伸。
在一些实施例中，中介层150可以仅包括导电通路112，并且可以不包含有源或无源电路。在其他实施例中，中介层150可以包括有源或无源电路(例如，晶体管、二极管、电阻器、电感器和电容器等)。在一些实施例中，中介层150可以包括包含晶体管的一个或多个设备层。
尽管图1和图2(以及附图中的其他附图)示出了中介层150中导电通路112的特定数量和布置，但是这些仅仅是说明性的，并且可以使用任何合适的数量和布置。例如，本文公开的导电通路112(例如，包括线114和/或过孔116)可以由任何适当的导电材料形成，例如，铜、银、镍、金、铝、其他金属或合金、或材料的组合。
在一些实施例中，微电子部件102可以包括IC管芯(封装的或未封装的)或IC管芯的堆叠体(例如，高带宽存储器管芯堆叠体)。在一些这样的实施例中，微电子部件102的绝缘材料可以包括二氧化硅、氮化硅、氮氧化物、聚酰亚胺材料、玻璃增强环氧树脂基质材料、或低k或超低k电介质(例如，碳掺杂电介质、氟掺杂电介质、多孔电介质、有机聚合物电介质、光可成像电介质、和/或基于苯并环丁烯的聚合物)。在一些另外的实施例中，微电子部件102的绝缘材料可以包括诸如硅、锗、或III-V族材料(例如，氮化镓)的半导体材料、以及一种或多种附加材料。例如，微电子部件102的绝缘材料可以包括氧化硅或氮化硅。微电子部件102中的导电通路可以包括导电线和/或导电过孔，并且可以以任何合适的方式连接微电子部件102中的任何导电触点(例如，连接微电子部件102的相同表面上或不同表面上的多个导电触点)。下面参考图9讨论可以被包括在本文公开的微电子部件102中的示例结构。特别地，微电子部件102可以包括有源和/或无源电路(例如，晶体管、二极管、电阻器、电感器和电容器等)。在一些实施例中，微电子部件102可以包括包含晶体管的一个或多个设备层。当微电子部件102包括有源电路时，功率和/或接地信号可以通过中介层150传送，并且通过DB区域130(并且进一步通过中间微电子部件102)传送到微电子部件102/从微电子部件102传送。在一些实施例中，微电子部件102可以采用本文中的中介层150的任何实施例的形式。尽管图1的微电子组件100的微电子部件102是单面部件(在单个微电子部件102仅在单个微电子部件102的单个表面上具有导电触点(例如，DB触点110)的意义上)，但是在一些实施例中，微电子部件102可以是在部件的多个表面上具有导电触点的双面(或“多级”或“全向”)部件(例如，图1的微电子部件102-1、102-2)。
诸如表面安装电阻器、电容器和/或电感器的附加部件(未示出)可以设置在中介层150的顶表面或底表面上，或者嵌入在中介层150中。图1的微电子组件100还包括耦接到中介层150的支撑部件182。在图1的特定实施例中，支撑部件182包括导电触点118，导电触点118通过中间焊料120(例如，球栅阵列(BGA)布置中的焊球)电耦接到中介层150的互补导电触点118，但是可以使用任何合适的互连结构(例如，针栅阵列布置中的针、连接盘栅格阵列布置中的连接盘、柱、焊盘和柱等)。在本文公开的微电子组件100中使用的焊料120可以包括任何合适的材料，诸如铅/锡、锡/铋、共晶锡/银、三元锡/银/铜、共晶锡/铜、锡/镍/铜、锡/铋/铜、锡/铟/铜、锡/锌/铟/铋、或其他合金。在一些实施例中，中介层150与支撑部件182之间的耦接可以被称为第二级互连(SLI)或多级互连(MLI)。
在一些实施例中，支撑部件182可以是封装衬底(例如，可以使用PCB工艺来制造，如上所讨论的)。在一些实施例中，支撑部件182可以是电路板(例如，主板)，并且可以具有附接到其的其他部件(未示出)。支撑部件182可以包括导电通路和其他导电触点(未示出)以用于通过支撑部件182传送电力、接地和信号，如本领域中已知的。在一些实施例中，支撑部件182可以包括另一IC封装、中介层、或任何其他合适的部件。底部填充材料138可被设置在将中介层150耦接至支撑部件182的焊料120周围。在一些实施例中，底部填充材料138可以包括环氧树脂材料。
在一些实施例中，支撑部件182可以是较低密度的部件，而中介层150和/或微电子部件102可以是较高密度的部件。如本文所使用的，术语“较低密度”和“较高密度”是相对术语，其指示较低密度部件中的导电通路(例如，包括导电线和导电过孔)比较高密度部件中的导电通路更大和/或具有更大的间距。在一些实施例中，微电子部件102可以是较高密度的部件，并且中介层150可以是较低密度的部件。在一些实施例中，可以使用双镶嵌或单镶嵌工艺来制造较高密度部件(例如，当较高密度部件是管芯时)，而可以使用半增材或修改的半增材工艺来制造较低密度部件(具有通过先进的激光或光刻工艺形成的小的垂直互连特征)(例如，当较低密度部件是封装衬底或中介层时)。在一些其他实施例中，可以使用半加成(semi-additive)或修改的半加成工艺来制造较高密度部件(例如，当较高密度部件是封装衬底或中介层时)，而可以使用半加成或减材工艺来制造较低密度部件(使用蚀刻化学剂来去除不需要的金属的区域，并且具有通过标准激光工艺形成的粗糙垂直互连特征)(例如，当较低密度部件是PCB时)。
图1的微电子组件100还可以包括模制材料126。模制材料126可以在中介层150上的微电子部件102中的一个或多个周围延伸。在一些实施例中，模制材料126可以在中介层150上和DB区域130周围的多个微电子部件102之间延伸。在一些实施例中，模制材料126可以在中介层150上的微电子部件102中的一个或多个的上方延伸(未示出)。模制材料126可以是绝缘材料，诸如适当的环氧树脂材料。可以选择模制材料126以具有可以减轻或最小化由微电子组件100中的不均匀热膨胀引起的微电子部件102和中介层150之间的应力的热膨胀系数(CTE)。在一些实施例中，模制材料126的CTE可以具有介于中介层150的CTE(例如，中介层150的绝缘材料106的CTE)和微电子部件102的CTE之间的值。在一些实施例中，可以至少部分地针对其热性质来选择微电子组件100中使用的模制材料126。例如，微电子组件100中使用的一种或多种模制材料126可以具有低热导率(例如，常规模制化合物)以延迟热传递，或者可以具有高热导率(例如，包括具有高热导率的金属或陶瓷颗粒的模制材料，诸如铜、银、金刚石、碳化硅、氮化铝、和氮化硼等)以促进热传递。本文中所提及的模制材料126中的任一个可以包括具有不同材料组成的一种或多种不同材料。
图1的微电子组件100还可以包括TIM 154。TIM 154可以包括聚合物或其他粘结剂中的导热材料(例如，金属颗粒)。TIM 154可以是热界面材料糊剂或导热环氧树脂(其在施加时可以是流体，并且可以在固化时硬化，如本领域中已知的)。TIM 154可以为微电子部件102产生的热量提供路径，以容易地流到热传递结构152，热量可以在热传递结构152处扩散和/或消散。图1的微电子组件100的一些实施例可以包括跨模制材料126和微电子部件102的顶表面的溅射金属化部(未示出)；TIM 154(例如，焊料TIM)可以设置在该金属化部上。
图1的微电子组件100还可以包括热传递结构152。热传递结构152可以用于将热量从微电子部件102中的一个或多个移开(例如，使得热量可以更容易地消散)。热传递结构152可以包括任何合适的导热材料(例如，金属、适当的陶瓷等)，并且可以包括任何合适的特征(例如，散热器、包括鳍片的散热器、冷板等)。在一些实施例中，热传递结构152可以是或可以包括集成散热器(IHS)。
微电子组件100的元件可以具有任何合适的尺寸。仅附图的子集用表示尺寸的附图标记来标记，但是这仅仅是为了清楚说明，并且本文公开的任何微电子组件100可以具有拥有本文讨论的尺寸的部件。在一些实施例中，中介层150的厚度184可以在20微米与200微米之间。在一些实施例中，DB区130的厚度188可以在50纳米与5微米之间。在一些实施例中，微电子部件102的厚度190可以在5微米与800微米之间。在一些实施例中，DB区域130中的DB触点110的间距128可以小于20微米(例如，在0.1微米与20微米之间)。
图3是根据各种实施例的在直接接合区域处包括屏蔽结构的微电子组件100的侧视截面图。微电子组件100可以包括具有有机材料106的中介层150、经由具有屏蔽结构115-3的第一直接接合区域130-1耦接到中介层150的第一微电子部件102-1、以及经由具有屏蔽结构115-4的第二直接接合区域130-2耦接到中介层150的第二微电子部件102-2。屏蔽结构115可以耦接到微电子部件102中的接地连接部(未示出)，或者可以耦接到中介层150中的接地连接部(例如，如关于屏蔽结构115-4所示)。尽管图3示出了中介层150和微电子部件102的DB界面(例如，DB界面180-1A和180-1B以及DB界面180-2A和180-2B，如图2所示)中的屏蔽结构115，但是在一些实施例中，屏蔽结构115可以在单个DB界面(例如，DB界面180-1A或180-1B以及DB界面180-2A或180-2B，如图2所示)中，如下面参考图6所述。
DB界面180中的DB触点110的覆盖区可以具有任何期望的形状，并且多个DB触点110可以以任何期望的方式布置在DB界面180内(例如，通过使用光刻图案化技术来形成DB触点110)。例如，图4A-4D是DB界面180的DB电介质108中的DB触点110的各种布置的俯视图。在图4A的实施例中，DB触点110具有矩形(例如，正方形)覆盖区，并且以矩形阵列布置。在图4B的实施例中，DB触点110具有十字形覆盖区，并且以三角形阵列布置。在图4C的实施例中，DB触点110以矩形阵列布置，并且DB触点110的交替行具有十字形覆盖区和三角形覆盖区。在图4D的实施例中，DB触点110以矩形阵列布置，DB触点110具有圆形覆盖区，并且DB触点110的覆盖区的直径以棋盘图案变化。DB界面180中包括的DB触点110可以具有这些和其他覆盖区形状、尺寸和布置(例如，六边形阵列、椭圆形覆盖区等)的任何合适的组合。在一些特定实施例中，DB界面180中的DB触点110可以具有形状为凸多边形(例如，正方形、矩形、八边形、十字形等)或圆形的覆盖区。
图5A是根据各种实施例的微电子组件100中的示例屏蔽结构的一部分的放大三维透视图。图5A示出了耦接到第二微电子部件(例如，图1的微电子部件102-3)(未示出)的第二DB触点110B-1、110B-2的第一微电子部件(例如，图1的微电子部件102-1)(未示出)的第一DB触点110A-1、110A-2，其中，屏蔽结构115至少部分地围绕第一DB触点110A-1、110A-2。如图5A所示，屏蔽结构115通过屏蔽结构部分158耦接到第一DB触点110A-2。在一些实施例中，第一DB触点110A-2耦接到第一微电子部件上的接地连接部。在一些实施例中，第一DB触点110A-2经由第二DB触点110B-2耦接到第二微电子部件上的接地连接部。在一些实施例中，屏蔽结构115可经由多个第一DB触点110A耦接到第一微电子部件102上的多个接地连接部(未示出)。如上文参考图1所述，屏蔽结构115可以由任何适当的导电材料形成，并且可以使用任何合适的工艺形成。屏蔽结构115可以具有任何合适的尺寸和形状。如下面参考图6详细描述的，屏蔽结构115可以是连续结构，例如网格或带状结构，或者可以是非连续结构，例如壁，其可以是例如平面的、Z字形的、或L形的。例如，屏蔽结构115可以是具有在50纳米和5微米之间的高度(z维度，在本文中也称为z高度或厚度)的栅格形状，并且在一些实施例中可以是与DB触点110相同的z高度(例如，可以延伸DB触点的整个高度)。尽管图5示出了具有与DB触点110相同厚度(例如，z维度)的屏蔽结构115的厚度(例如，z维度)，但是屏蔽结构115的厚度可以小于DB触点110的厚度。屏蔽结构115可以具有任何合适的宽度(x维度)，例如，在0.05微米和5微米之间的宽度。屏蔽结构115可以具有到DB触点110的间隔(s维度)，该间隔可以基于特性阻抗和/或可用间隔而变化。屏蔽结构115到DB触点110的间隔可以进一步取决于DB触点直径(x维度)。例如，对于相同的屏蔽结构间隔，较小的DB触点110直径可以导致较高的特性阻抗。
]图5B是根据各种实施例的微电子组件100中的示例屏蔽结构的一部分的放大三维透视图。图5B示出了耦接到第二微电子部件(例如，图1的微电子部件102-3)(未示出)的第二DB触点110B-1、110B-2的第一微电子部件(例如，图1的微电子部件102-1)(未示出)的第一DB触点110A-1、110A-2，其中，第一屏蔽结构115A至少部分地围绕第一DB触点110A-1、110A-2，并且第二屏蔽结构115B至少部分地围绕第二DB触点110B-1、110B-2，并且其中，第一屏蔽结构115A耦接到第二屏蔽结构115B。如图5B所示，第二屏蔽结构115B通过屏蔽结构部分158耦接到第二DB触点110B-2。在一些实施例中，第一屏蔽结构115A可以包括耦接到DB触点110A-2的屏蔽结构部分158(例如，其中，屏蔽结构部分158沿着DB触点110A-2和110B-2延伸)(未示出)。在一些实施例中，第二DB触点110B-2耦接到第二微电子部件上的接地连接部。在一些实施例中，第二DB触点110B-2经由第一DB触点110A-2耦接到第一微电子部件上的接地连接部。在一些实施例中，第一屏蔽结构115A和第二屏蔽结构115B可经由多个第一DB触点110A和/或第二DB触点110B耦接到第一微电子部件102和/或第二微电子部件102上的多个接地连接部(未示出)。尽管第一DB触点110A和第二DB触点110B以及第一屏蔽结构115A和第二屏蔽结构115B被示出为在耦接界面处完全对准，但是在一些实施例中，第一DB触点110A和第二DB触点110B和/或第一屏蔽结构115A和第二屏蔽结构115B可以在耦接界面处未对准或偏移。
图6A-6F是示出可以包括在图1的微电子组件100中的DB触点110和屏蔽结构115的示例布置的俯视图，然而，这些布置仅仅是示例性的，并且可以使用任何合适的布置。图6A是DB触点110的俯视图，该DB触点110具有矩形形状并且包括由屏蔽结构115A围绕的信号互连652A和接地互连653A。尽管屏蔽结构115A被示出为具有到接地DB触点653A的多个连接部的连续网格结构，但是屏蔽结构115A可以具有任何合适的几何形状(例如，圆形、三角形、矩形、六边形、八边形等)。尽管图6A将DB触点110(例如，信号互连652A和接地互连653A)示出为以矩形阵列布置，但是DB触点110可以以任何合适的图案(例如，三角形、六边形、矩形等)布置。尽管图6A示出了9:1的信号与接地连接比，但是可以使用任何合适的信号与接地比来维持良好的接地性能，这取决于整个互连通道的操作频率和期望性能。
图6B示出了DB触点110，其具有圆形覆盖区并且包括布置在具有连续屏蔽结构115B的偏移网格中的信号互连652B和接地互连653B。屏蔽结构115B以菱形形状围绕每个单独的DB触点110(例如，信号互连652B和接地互连653B)，并且耦接到三个接地互连653B。
图6C示出了用于差分信令的屏蔽结构布置，其中，DB触点110包括正端子652C-1和负端子652C-2，并且共享屏蔽结构115C。屏蔽结构115C可以围绕带正电荷的端子652C-1和带负电荷的端子652C-2两者，并且可以围绕并耦接到接地互连653C。
图6D示出了用于包括信号互连652D和接地互连653D的DB触点110的屏蔽结构，其中，一组信号互连652D共享屏蔽结构115D(例如，多个信号互连652D被屏蔽结构115D围绕)，以更容易地适应DB界面(例如，图2中的DB界面180)处的任何未对准公差。
图6E示出了围绕具有信号互连652E和接地互连653E的DB触点110的非连续或穿孔屏蔽结构115E。屏蔽结构115E具有开口109，开口109可提供用于DB接合区域130的连续DB电介质108界面(例如，图2的DB界面180)。如上面参考图1和5所述，尽管图6A-6E示出了单个屏蔽结构115，但是DB接合区域130可以包括多于一个屏蔽结构115。屏蔽可以通过接合界面下方的连接部(例如，通过到下层的过孔)来维持电连续性。
图6F示出了包括两个隔离的网格形状(例如，第一屏蔽结构115F-1和第二屏蔽结构115F-2)的双参考屏蔽结构115F的示例实施方式，其中，第一屏蔽结构115F-1连接到接地端子653F并且第二屏蔽结构115F-2连接到参考电压连接部或电源端子655F(例如，高电压端子)。双参考屏蔽结构115F可有助于布线和功率完整性以及信号完整性，且进一步可有助于一些管芯到管芯互连电路设计。
图6G示出了围绕DB触点(例如，信号互连652G和接地互连653G)的交织屏蔽结构115G。交织屏蔽结构115G包括在第一微电子部件(未示出)上的第一屏蔽结构部分115G-1(例如，如垂直线所示)和在第二微电子部件(未示出)上的第二屏蔽结构部分115G-2(例如，如水平线所示)，其中，第一屏蔽结构部分115G-1和第二屏蔽结构部分115G-2耦接到接地互连653G。
可以使用任何合适的技术来制造本文公开的微电子组件。图7A-7D是根据各种实施例的用于制造图3的微电子组件的示例过程中的各种阶段的侧视截面图。尽管下面参考图7A-7D(以及附图中的表示制造过程的其他附图)讨论的操作以特定顺序示出，但是这些操作可以以任何合适的顺序执行。图7A示出了包括安装在载体104上的中介层150的组件。中介层150包括两个暴露的DB界面180-1和180-2，DB界面180-1和180-2包括DB触点110和相应的屏蔽结构115-1和115-2。载体104可以包括任何合适的材料，并且在一些实施例中，可以包括半导体晶圆(例如，硅晶圆)或玻璃(例如，玻璃面板)。当中介层150是有机中介层时，中介层150可以有利地在载体104上制造，这可以提供机械稳定的表面，中介层150的层可以形成在该表面上。
图7B示出了在将微电子部件102-1和102-2直接接合到图7A的中介层150/载体104之后的组件。特别地，可以使微电子部件102的DB界面180(未标记)与中介层150的DB界面180接触，并且施加热和/或压力以接合接触的DB界面180以形成DB区域130(其中，DB区域130-1和130-2分别对应于DB界面180-1和180-2)，其中，DB区域130-1和130-2分别包括屏蔽结构115-1和115-2。
图7C示出了在图7B的组件的微电子部件102周围和中介层150的表面上提供模制材料126之后的组件。在一些实施例中，模制材料126可以在微电子部件102上方延伸并保持在微电子部件102上方，而在其他实施例中，模制材料126可以被抛光回去，以暴露微电子部件102的顶表面，如图所示。
图7D示出了在从图7C的组件去除载体104并在新暴露的导电触点118上提供焊料120之后的组件。图7D的组件本身可以是微电子组件100，如图所示。可以在图7D的微电子组件100上执行进一步的制造操作以形成其他微电子组件100；例如，焊料120可用于将图7D的微电子组件100耦接到支撑部件182，并且TIM 154和热传递结构152可设置在图7D的微电子组件100的顶表面上，类似于图1的微电子组件100。
包括多层级的微电子部件102的微电子组件100可以以上面参考图7A-7D讨论的方式形成，其中，在沉积模制材料126之前将附加层级的微电子部件102(例如，图1的微电子部件102-3、102-4)耦接到前面的组件。在一些其他实施例中，包括多层级的微电子部件102的微电子组件100可以通过首先组装微电子部件102的层级，然后将组装的层级耦接到中介层150来形成，如上面参考图7B所讨论的。微电子组件100可以不限于两层级的微电子部件102，而是可以根据需要包括三或更多层级。此外，尽管图1中的单个层级中的微电子部件102被示出为具有相同的高度，但这仅仅是为了便于说明，并且微电子组件100中的任何单个层级中的微电子部件102可以具有不同的高度。此外，并非微电子组件100中的每个微电子部件102都可以是多个微电子部件102的堆叠体的一部分；例如，在图1的微电子组件100的一些变型中，在微电子部件102-2的顶部上可以不存在微电子部件102-4。
本文公开的微电子部件102和微电子组件100可以包括在任何合适的电子部件中。图8-11示出了装置的各种示例，该装置可以适当地包括本文公开的微电子部件102和微电子组件100中的任一个，或者被包括在本文公开的微电子部件102和微电子组件100中的任一个中。
图8是可以被包括在本文公开的任何微电子部件102中的晶圆1500和管芯1502的俯视图。例如，管芯1502可以用作微电子部件102，或者可以被包括在微电子部件102中。晶圆1500可以由半导体材料构成，并且可以包括具有形成在晶圆1500的表面上的IC结构的一个或多个管芯1502。管芯1502中的每一个可以是包括任何合适IC的半导体产品的重复单元。在半导体产品的制造完成之后，晶圆1500可以经历单切(singulation)工艺，在该单切工艺中，管芯1502被彼此分离以提供半导体产品的分立“芯片”。管芯1502可以包括一个或多个晶体管(例如，下面讨论的图9的晶体管1640中的一些)和/或用于将电信号传送到晶体管的支持电路，以及任何其他IC部件。在一些实施例中，晶圆1500或管芯1502可以包括存储器设备(例如，随机存取存储器(RAM)设备，诸如静态RAM(SRAM)设备、磁RAM(MRAM)设备、电阻式RAM(RRAM)设备、导电桥接RAM(CBRAM)设备等)、逻辑设备(例如，AND、OR、NAND、或NOR门)、或任何其他合适的电路元件。这些设备中的多个设备可以被组合在单个管芯1502上。例如，由多个存储器设备形成的存储器阵列可以与处理设备(例如，图11的处理设备1802)或被配置为将信息存储在存储器设备中或执行存储在存储器阵列中的指令的其他逻辑部形成在相同的管芯1502上。
图9是可以被包括在本文公开的任何微电子部件102中的IC设备1600的侧视截面图。例如，IC设备1600(例如，作为管芯1502的一部分，如以上参考图8所讨论的)可用作微电子部件102，或者可被包括在微电子部件102中。IC设备1600中的一个或多个可以被包括在一个或多个管芯1502(图8)中。IC设备1600可形成在衬底1602(例如，图8的晶圆1500)上并且可被包括在管芯(例如，图8的管芯1502)中。衬底1602可以是由包括例如n型或p型材料系统(或两者的组合)的半导体材料系统组成的半导体衬底。衬底1602可以包括例如使用块状硅或绝缘体上硅(SOI)子结构形成的晶体衬底。在一些实施例中，衬底1602可以使用替代材料形成，该替代材料可以与硅组合或可以不与硅组合，包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、或锑化镓。分类为II-VI、III-V或IV族的其他材料也可用于形成衬底1602。尽管本文描述了可形成衬底1602的材料的几个示例，但可使用可用作IC设备1600的基础的任何材料。衬底1602可以是经单切的管芯(例如，图8的管芯1502)或晶圆(例如，图8的晶圆1500)的一部分。
IC设备1600可以包括设置在衬底1602上的一个或多个设备层1604。设备层1604可以包括形成在衬底1602上的一个或多个晶体管1640(例如，金属氧化物半导体场效应晶体管(MOSFET))的特征。设备层1604可以包括例如一个或多个源极和/或漏极(S/D)区1620、用于控制S/D区1620之间的晶体管1640中的电流流动的栅极1622、以及用于将电信号传送到S/D区1620/从S/D区1620传送电信号的一个或多个S/D触点1624。晶体管1640可以包括为了清楚起见而未示出的附加特征，诸如设备隔离区域、栅极触点等。晶体管1640不限于图9中示出的类型和配置，并且可以包括各种各样的其他类型和配置，例如，平面晶体管、非平面晶体管、或两者的组合。平面晶体管可以包括双极结晶体管(BJT)、异质结双极晶体管(HBT)、或高电子迁移率晶体管(HEMT)。非平面晶体管可以包括FinFET晶体管(诸如双栅极晶体管或三栅极晶体管)、以及环栅或全环栅晶体管(诸如纳米带和纳米线晶体管)。
每个晶体管1640可以包括由至少两层(栅极电介质和栅电极)形成的栅极1622。栅极电介质可以包括一层或层的堆叠体。一个或多个层可以包括氧化硅、二氧化硅、碳化硅和/或高k电介质材料。高k电介质材料可以包括诸如铪、硅、氧、钛、钽、镧、铝、锆、钡、锶、钇、铅、钪、铌和锌的元素。可以在栅极电介质中使用的高k材料的示例包括但不限于氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铌酸锌铅。在一些实施例中，当使用高k材料时，可以对栅极电介质执行退火工艺以提高其质量。
栅电极可以形成在栅极电介质上，并且可以包括至少一种p型功函数金属或n型功函数金属，这取决于晶体管1640是p型金属氧化物半导体(PMOS)还是n型金属氧化物半导体(NMOS)晶体管。在一些实施方式中，栅电极可由两个或更多个金属层的堆叠体组成，其中，一个或多个金属层是功函数金属层并且至少一个金属层是填充金属层。出于其他目的，可以包括另外的金属层，诸如阻挡层。对于PMOS晶体管，可被用于栅电极的金属包括但不限于钌、钯、铂、钴、镍、导电金属氧化物(例如，氧化钌)、以及以下参考NMOS晶体管讨论的任何金属(例如，用于功函数调节)。对于NMOS晶体管，可用于栅电极的金属包括但不限于铪、锆、钛、钽、铝、这些金属的合金、这些金属的碳化物(例如，碳化铪、碳化锆、碳化钛、碳化钽和碳化铝)、以及以上参考PMOS晶体管讨论的任何金属(例如，用于功函数调节)。
在一些实施例中，当沿源极-沟道-漏极方向观察晶体管1640的截面时，栅电极可以由U形结构组成，该U形结构包括基本上平行于衬底表面的底部部分和基本上垂直于衬底顶表面的两个侧壁部分。在其他实施例中，形成栅电极的金属层中的至少一个可以简单地是基本上平行于衬底的顶表面的平面层，并且不包括基本上垂直于衬底的顶表面的侧壁部分。在其他实施例中，栅电极可以由U形结构和平面非U形结构的组合组成。例如，栅电极可以由形成在一个或多个平面的非U形层顶上的一个或多个U形金属层组成。
在一些实施例中，可在栅极堆叠体的相对侧上形成一对侧壁间隔物，以将栅极堆叠体括在其间。侧壁间隔物可以由诸如氮化硅、氧化硅、碳化硅、碳掺杂氮化硅、和氮氧化硅的材料形成。用于形成侧壁间隔物的工艺在本领域中是公知的，并且通常包括沉积和蚀刻工艺步骤。在一些实施例中，可以使用多个间隔物对；例如，可以在栅极堆叠体的相对侧上形成两对、三对或四对侧壁间隔物。
可在衬底1602内邻近每个晶体管1640的栅极1622形成S/D区1620。例如，可以使用注入/扩散工艺或蚀刻/沉积工艺来形成S/D区1620。在前一工艺中，可以将诸如硼、铝、锑、磷或砷的掺杂剂离子注入到衬底1602中以形成S/D区1620。激活掺杂剂并使它们进一步扩散到衬底1602中的退火工艺可以在离子注入工艺之后。在后一工艺中，可以首先蚀刻衬底1602以在S/D区1620的位置处形成凹槽。然后可以执行外延沉积工艺以使用用于制造S/D区1620的材料填充凹槽。在一些实施方式中，S/D区1620可使用硅合金(诸如硅锗或碳化硅)来制造。在一些实施例中，外延沉积的硅合金可以用诸如硼、砷或磷的掺杂剂原位掺杂。在一些实施例中，可以使用一种或多种替代半导体材料(诸如锗或III-V族材料或合金)来形成S/D区1620。在进一步的实施例中，可以使用一层或多层金属和/或金属合金来形成S/D区1620。
可以通过设置在设备层1604上的一个或多个互连层(在图9中示出为互连层1606-1610)向和/或从设备层1604的设备(例如，晶体管1640)传送诸如电力和/或输入/输出(I/O)信号的电信号。例如，设备层1604的导电特征(例如，栅极1622和S/D触点1624)可以与互连层1606-1610的互连结构1628电耦接。一个或多个互连层1606-1610可以形成IC设备1600的金属化堆叠体(也称为“ILD堆叠体”)1619。
互连结构1628可以布置在互连层1606-1610内，以根据各种各样的设计来传送电信号(特别地，该布置不限于图9中示出的互连结构1628的特定配置)。尽管在图9中示出了特定数量的互连层1606-1610，但是本公开内容的实施例包括具有比所示出的更多或更少的互连层的IC设备。
在一些实施例中，互连结构1628可以包括填充有诸如金属的导电材料的线1628a和/或过孔1628b。线1628a可以被布置为在与衬底1602的表面基本上平行的平面的方向上传送电信号，设备层1604形成在衬底1602的表面上。例如，线1628a可以从图9的视角在进出页面的方向上传送电信号。过孔1628b可以被布置为在基本上垂直于衬底1602的表面的平面的方向上传送电信号，设备层1604形成在衬底1602的表面上。在一些实施例中，过孔1628b可以将不同互连层1606-1610的线1628a电耦接在一起。
互连层1606-1610可以包括设置在互连结构1628之间的电介质材料1626，如图9所示。在一些实施例中，设置在互连层1606-1610中的不同互连层中的互连结构1628之间的电介质材料1626可以具有不同的组成；在其他实施例中，不同互连层1606-1610之间的电介质材料1626的组成可以是相同的。
可以在设备层1604上方形成第一互连层1606。在一些实施例中，第一互连层1606可以包括线1628a和/或过孔1628b，如图所示。第一互连层1606的线1628a可以与设备层1604的触点(例如，S/D触点1624)耦接。
可以在第一互连层1606上方形成第二互连层1608。在一些实施例中，第二互连层1608可以包括过孔1628b，以将第二互连层1608的线1628a与第一互连层1606的线1628a耦接。尽管为了清楚起见，线1628a和过孔1628b在结构上用每个互连层内(例如，在第二互连层1608内)的线来示出，但是在一些实施例中，线1628a和过孔1628b可以在结构上和/或材料上连续(例如，在双镶嵌工艺期间同时填充)。
根据结合第二互连层1608或第一互连层1606描述的类似技术和配置，可以在第二互连层1608上连续形成第三互连层1610(以及根据需要的附加互连层)。在一些实施例中，在IC设备1600中的金属化堆叠体1619中“更高”(即，更远离设备层1604)的互连层可以更厚。
IC设备1600可以包括形成在互连层1606-1610上的阻焊材料1634(例如，聚酰亚胺或类似材料)和一个或多个导电触点1636。在图9中，导电触点1636被示出为采用接合焊盘的形式。导电触点1636可以与互连结构1628电耦接，并且被配置为将(一个或多个)晶体管1640的电信号传送到其他外部设备。例如，焊料接合可被形成在一个或多个导电触点1636上以将包括IC设备1600的芯片与另一部件(例如，电路板)机械地和/或电气地耦接。IC设备1600可以包括附加或替换结构以传送来自互连层1606-1610的电信号；例如，导电触点1636可以包括将电信号传送到外部部件的其他类似特征(例如，柱)。
图10是IC设备组件1700的侧视截面图，该IC设备组件1700可以包括本文公开的任何微电子部件102和/或微电子组件100。IC设备组件1700包括设置在电路板1702(其可以是例如主板)上的多个部件。IC设备组件1700包括设置在电路板1702的第一面1740和电路板1702的相反的第二面1742上的部件；通常，部件可以设置在一个或两个面1740和1742上。下面参考IC设备组件1700讨论的任何IC封装可以包括本文公开的微电子组件100的任何实施例(例如，可以包括通过直接接合耦接在一起的多个微电子部件102)。
在一些实施例中，电路板1702可以是包括多个金属层的PCB，所述多个金属层通过电介质材料层彼此分离并且通过导电过孔互连。金属层中的任何一个或多个可以以期望的电路图案形成，以在耦接到电路板1702的部件之间传送电信号(可选地结合其他金属层)。在其他实施例中，电路板1702可以是非PCB衬底。
图10所示的IC设备组件1700包括通过耦接部件1716耦接到电路板1702的第一面1740的中介层上封装(package-on-interposer)结构1736。耦接部件1716可以将中介层上封装结构1736电气地和机械地耦接到电路板1702，并且可以包括焊球(如图10所示)、插座的凸出和凹入部分、粘合剂、底部填充材料、和/或任何其他合适的电气和/或机械耦接结构。
中介层上封装结构1736可以包括通过耦接部件1718耦接到封装中介层1704的IC封装1720。耦接部件1718可以采用用于应用的任何合适的形式，诸如上面参考耦接部件1716讨论的形式。尽管在图10中示出了单个IC封装1720，但是多个IC封装可以耦接到封装中介层1704；实际上，附加中介层可以耦接到封装中介层1704。封装中介层1704可以提供用于桥接电路板1702和IC封装1720的中间衬底。IC封装1720可以是或包括例如管芯(图8的管芯1502)、IC设备(例如，图9的IC设备1600)、或任何其他合适的部件。通常，封装中介层1704可以将连接扩展到更宽的间距或者将连接重新布线到不同的连接。例如，封装中介层1704可以将IC封装1720(例如，管芯)耦接到耦接部件1716的一组BGA导电触点，以用于耦接到电路板1702。在图10所示的实施例中，IC封装1720和电路板1702附接到封装中介层1704的相反侧；在其他实施例中，IC封装1720和电路板1702可以附接到封装中介层1704的同一侧。在一些实施例中，三个或更多个部件可以通过封装中介层1704互连。
在一些实施例中，封装中介层1704可以形成为PCB，包括通过电介质材料层彼此分离并通过导电过孔互连的多个金属层。在一些实施例中，封装中介层1704可以由环氧树脂、玻璃纤维增强环氧树脂、具有无机填料的环氧树脂、陶瓷材料、或聚合物材料(诸如聚酰亚胺)形成。在一些实施例中，封装中介层1704可以由交替的刚性或柔性材料形成，该刚性或柔性材料可以包括上述用于半导体衬底的相同材料，例如硅、锗、和其他III-V族和IV族材料。封装中介层1704可以包括金属线1710和过孔1708，包括但不限于TSV 1706。封装中介层1704还可以包括嵌入式设备1714，其包括无源设备和有源设备两者。这样的设备可以包括但不限于电容器、去耦电容器、电阻器、电感器、熔丝、二极管、变压器、传感器、静电放电(ESD)设备、和存储器设备。还可以在封装中介层1704上形成更复杂的设备，诸如射频设备、功率放大器、功率管理设备、天线、阵列、传感器、和微机电系统(MEMS)设备。中介层上封装结构1736可以采用本领域已知的任何中介层上封装结构的形式。
IC设备组件1700可以包括通过耦接部件1722耦接到电路板1702的第一面1740的IC封装1724。耦接部件1722可以采用上面参考耦接部件1716讨论的任何实施例的形式，并且IC封装1724可以采用上面参考IC封装1720讨论的任何实施例的形式。
图10所示的IC设备组件1700包括通过耦接部件1728耦接到电路板1702的第二面1742的堆叠式封装(package-on-package)结构1734。堆叠式封装结构1734可以包括通过耦接部件1730耦接在一起的IC封装1726和IC封装1732，使得IC封装1726设置在电路板1702和IC封装1732之间。耦接部件1728和1730可以采用上面讨论的耦接部件1716的任何实施例的形式，并且IC封装1726和1732可以采用上面讨论的IC封装1720的任何实施例的形式。堆叠式封装结构1734可以根据本领域中已知的堆叠式封装结构中的任一种来配置。
图11是可以包括本文公开的任何微电子部件102和/或微电子组件100的示例电气设备1800的框图。例如，电气设备1800的部件中的任何合适的部件可以包括本文公开的IC设备组件1700、IC设备1600、或管芯1502中的一个或多个。多个部件在图11中被示出为包括在电气设备1800中，但是这些部件中的任何一个或多个可以被省略或复制，以适合于应用。在一些实施例中，包括在电气设备1800中的部件中的一些或全部可以附接到一个或多个主板。在一些实施例中，在单个片上系统(SoC)管芯上制造这些部件中的一些或全部。
另外，在各种实施例中，电气设备1800可以不包括图11所示的一个或多个部件，但是电气设备1800可以包括用于耦接到一个或多个部件的接口电路。例如，电气设备1800可不包括显示设备1806，但可以包括显示设备1806可耦接到的显示设备接口电路(例如，连接器和驱动器电路)。在另一组示例中，电气设备1800可以不包括音频输入设备1824或音频输出设备1808，但是可以包括音频输入设备1824或音频输出设备1808可以耦接到的音频输入或输出设备接口电路(例如，连接器和支持电路)。
电气设备1800可以包括处理设备1802(例如，一个或多个处理设备)。如本文所使用的，术语“处理设备”或“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换为可以存储在寄存器和/或存储器中的其他电子数据的任何设备或设备的一部分。处理设备1802可以包括一个或多个数字信号处理器(DSP)、专用集成电路(ASIC)、中央处理单元(CPU)、图形处理单元(GPU)、密码处理器(在硬件内执行密码算法的专用处理器)、服务器处理器、或任何其他合适的处理设备。电气设备1800可以包括存储器1804，存储器1804本身可以包括一个或多个存储器设备，诸如易失性存储器(例如，动态随机存取存储器(DRAM))、非易失性存储器(例如，只读存储器(ROM))、闪存、固态存储器、和/或硬盘驱动器。在一些实施例中，存储器1804可以包括与处理设备1802共享管芯的存储器。该存储器可以用作高速缓存存储器，并且可以包括嵌入式动态随机存取存储器(eDRAM)或自旋转移矩磁随机存取存储器(STT-MRAM)。
在一些实施例中，电气设备1800可以包括通信芯片1812(例如，一个或多个通信芯片)。例如，通信芯片1812可以被配置用于管理用于向电气设备1800和从电气设备1800传输数据的无线通信。术语“无线”及其派生词可以用于描述可通过使用经调制的电磁辐射、经由非固体介质来通信数据的电路、设备、系统、方法、技术、通信信道等。该术语并不意味着相关联的设备不包含任何导线，尽管在一些实施例中它们可能不包含。
通信芯片1812可以实现多种无线标准或协议中的任何一种，包括但不限于电气和电子工程师协会(IEEE)标准，包括Wi-Fi(IEEE 802.11系列)、IEEE 802.16标准(例如，IEEE802.16-2005修订版)、长期演进(LTE)项目以及任何修订版、更新版和/或修正版(例如，高级LTE项目、超移动宽带(UMB)项目(也称为“3GPP2”)等)。兼容IEEE 802.16的宽带无线接入(BWA)网络通常被称为WiMAX网络，WiMAX是代表微波接入全球互操作的首字母缩写词，其是通过IEEE 802.16标准的一致性和互操作性测试的产品的认证标志。通信芯片1812可以根据全球移动通信系统(GSM)、通用分组无线业务(GPRS)、通用移动电信系统(UMTS)、高速分组接入(HSPA)、演进HSPA(E-HSPA)、或LTE网络来操作。通信芯片1812可以根据增强型数据GSM演进(EDGE)、GSM EDGE无线接入网(GERAN)、通用陆地无线接入网(UTRAN)、或演进型UTRAN(E-UTRAN)来操作。通信芯片1812可以根据码分多址(CDMA)、时分多址(TDMA)、数字增强无绳电信(DECT)、演进数据优化(EV-DO)、及其派生物、以及被指定为3G、4G、5G及之后的任何其他无线协议来操作。在其他实施例中，通信芯片1812可以根据其他无线协议进行操作。电气设备1800可以包括天线1822，以便于无线通信和/或接收其他无线通信(例如AM或FM无线电传输)。
在一些实施例中，通信芯片1812可以管理有线通信，诸如电、光或任何其他合适的通信协议(例如，以太网)。如上所述，通信芯片1812可以包括多个通信芯片。例如，第一通信芯片1812可以专用于诸如Wi-Fi或蓝牙的较短距离无线通信，并且第二通信芯片1812可以专用于诸如全球定位系统(GPS)、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO或其他的较长距离无线通信。在一些实施例中，第一通信芯片1812可以专用于无线通信，并且第二通信芯片1812可以专用于有线通信。
电气设备1800可以包括电池/电源电路1814。电池/电源电路1814可以包括一个或多个能量存储设备(例如，电池或电容器)和/或用于将电气设备1800的部件耦接到与电气设备1800分离的能量源(例如，AC线路电源)的电路。
电气设备1800可以包括显示设备1806(或对应的接口电路，如上所讨论的)。显示设备1806可包括任何视觉指示器，例如平视显示器、计算机监视器、投影仪、触摸屏显示器、液晶显示器(LCD)、发光二极管显示器、或平板显示器。
电气设备1800可以包括音频输出设备1808(或对应的接口电路，如上所讨论的)。音频输出设备1808可以包括生成可听指示符的任何设备，诸如扬声器、耳机或耳塞。
电气设备1800可以包括音频输入设备1824(或对应的接口电路，如上所讨论的)。音频输入设备1824可包括产生表示声音的信号的任何设备，例如麦克风、麦克风阵列、或数字乐器(例如，具有乐器数字接口(MIDI)输出的乐器)。
电气设备1800可以包括GPS设备1818(或对应的接口电路，如上所讨论的)。GPS设备1818可以与基于卫星的系统通信，并且可以接收电气设备1800的位置，如本领域已知的。
电气设备1800可以包括其他输出设备1810(或对应的接口电路，如上所讨论的)。其他输出设备1810的示例可以包括音频编解码器、视频编解码器、打印机、用于向其他设备提供信息的有线或无线发射机、或附加存储设备。
电气设备1800可包括其他输入设备1820(或对应的接口电路，如上所讨论的)。其他输入设备1820的示例可包括加速计、陀螺仪、罗盘、图像捕捉设备、键盘、诸如鼠标、指示笔、触摸板之类的光标控制设备、条形码读取器、快速响应(QR)码读取器、任何传感器、或射频识别(RFID)读取器。
电气设备1800可以具有任何期望的形状因子，诸如手持式或移动电气设备(例如，蜂窝电话、智能电话、移动互联网设备、音乐播放器、平板计算机、膝上型计算机、上网本计算机、超级本计算机、个人数字助理(PDA)、超移动个人计算机等)、台式电气设备、服务器设备、或其他联网计算部件、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、车辆控制单元、数码相机、数字视频记录器、或可穿戴电气设备。在一些实施例中，电气设备1800可以是处理数据的任何其他电子设备。
以下段落提供了本文所公开的实施例的各种示例。
示例1是一种微电子组件，包括：第一微电子部件，具有第一表面和相反的第二表面，所述第一微电子部件包括在第二表面处的第一直接接合区域，所述第一直接接合区域具有第一金属触点和在第一金属触点中的相邻第一金属触点之间的第一电介质材料；第二微电子部件，具有第一表面和相反的第二表面，所述第二微电子部件包括在第一表面处的第二直接接合区域，所述第二直接接合区域具有第二金属触点和在所述第二金属触点中的相邻第二金属触点之间的第二电介质材料，其中，所述第二微电子部件通过所述第一直接接合区域和所述第二直接接合区域耦接到所述第一微电子部件；以及在第一电介质材料中的屏蔽结构，至少部分地围绕所述第一金属触点中的一个或多个第一金属触点。
示例2可以包括示例1的主题，并且还可以指定所述屏蔽结构耦接到所述第一微电子部件或第二微电子部件上的接地连接部。
示例3可以包括示例1的主题，并且还可以指定所述屏蔽结构耦接到所述第一微电子部件或第二微电子部件上的参考电压连接部或电源端子。
示例4可以包括示例1的主题，并且还可以指定所述第一金属触点包括差分信令互连的正端子和差分信令互连的负端子，并且其中，所述屏蔽结构围绕正端子和负端子。
示例5可以包括示例1的主题，并且还可以指定所述屏蔽结构具有环绕所述第一金属触点中的一个或多个第一金属触点形成矩形的截面。
示例6可以包括示例1的主题，并且还可以指定所述屏蔽结构的厚度小于所述第一金属触点的厚度。
示例7可以包括示例1的主题，并且还可以指定所述屏蔽结构是第一屏蔽结构，并且还可以包括在所述第二电介质材料中的第二屏蔽结构，所述第二屏蔽结构至少部分地围绕所述第二金属触点中的一个或多个第二金属触点。
示例8可以包括示例7的主题，并且还可以指定所述第一屏蔽结构的至少一部分耦接到所述第二屏蔽结构的至少一部分。
示例9可以包括示例7的主题，并且还可以指定所述第一屏蔽结构耦接到所述第一微电子部件上的接地连接部，并且所述第二屏蔽结构耦接到所述第二微电子部件上的参考电压连接部或电源端子。
示例10是一种微电子组件，包括：中介层；以及微电子部件，通过直接接合区域耦接到所述中介层，其中，所述直接接合区域包括金属触点、在金属触点中的相邻金属触点之间的直接接合电介质材料、以及在所述直接接合电介质材料中的至少部分地围绕所述金属触点中的一个或多个金属触点的屏蔽结构。
示例11可以包括示例10的主题，并且还可以指定所述屏蔽结构耦接到所述微电子部件上的接地连接部。
示例12可以包括示例10的主题，并且还可以指定所述屏蔽结构耦接到所述中介层上的接地连接部。
示例13可以包括示例10的主题，并且还可以指定所述金属触点包括差分信令互连的正端子和差分信令互连的负端子，并且其中，所述屏蔽结构围绕正端子和负端子。
示例14可以包括示例10的主题，并且还可以指定所述屏蔽结构的至少一部分与个体金属触点接触。
示例15可以包括示例10的主题，并且还可以指定所述屏蔽结构的至少一部分围绕三个或更多个金属触点。
示例16可以包括示例10的主题，并且还可以指定所述屏蔽结构的厚度小于所述金属触点的厚度。
示例17是一种微电子组件，包括：中介层；第一微电子部件；以及第二微电子部件，所述第二微电子部件具有第一表面和相反的第二表面，所述第二微电子部件在所述第一表面处通过第一直接接合区域耦接到所述中介层并且在所述第二表面处通过第二直接接合区域耦接到所述第一微电子部件，其中，所述第一直接接合区域包括第一金属触点、在所述第一金属触点中的相邻第一金属触点之间的第一电介质材料、以及在所述第一电介质材料中的至少部分地围绕所述第一金属触点中的一个或多个第一金属触点的第一屏蔽结构，并且其中，所述第二直接接合区域包括第二金属触点、所述第二金属触点中的相邻第二金属触点之间的第二电介质材料、以及所述第二电介质材料中的至少部分地围绕所述第二金属触点中的一个或多个第二金属触点的第二屏蔽结构。
示例18可以包括示例17的主题，并且还可以指定所述第一微电子部件是射频(RF)管芯，并且所述第二微电子部件是数字管芯。
示例19可以包括示例17的主题，并且还可以指定所述中介层是封装衬底。
示例20可以包括示例17的主题，并且还可以指定所述中介层具有第一表面和相反的第二表面，并且所述第二微电子部件耦接到所述中介层的第二表面，并且还可以包括耦接到所述中介层的第一表面的电路板。

Claims (20)

1.一种微电子组件，包括：
第一微电子部件，具有第一表面和相反的第二表面，所述第一微电子部件包括在所述第二表面处的第一直接接合区域，所述第一直接接合区域具有第一金属触点和在所述第一金属触点中的相邻第一金属触点之间的第一电介质材料；
第二微电子部件，具有第一表面和相反的第二表面，所述第二微电子部件包括在所述第一表面处的第二直接接合区域，所述第二直接接合区域具有第二金属触点和在所述第二金属触点中的相邻第二金属触点之间的第二电介质材料，其中，所述第二微电子部件通过所述第一直接接合区域和所述第二直接接合区域耦接到所述第一微电子部件；以及
在所述第一电介质材料中的屏蔽结构，至少部分地围绕所述第一金属触点中的一个或多个第一金属触点。
2.根据权利要求1所述的微电子组件，其中，所述屏蔽结构耦接到所述第一微电子部件或所述第二微电子部件上的接地连接部。
3.根据权利要求1所述的微电子组件，其中，所述屏蔽结构耦接到所述第一微电子部件或所述第二微电子部件上的参考电压连接部或电源端子。
4.根据权利要求1所述的微电子组件，其中，所述第一金属触点包括差分信令互连的正端子和所述差分信令互连的负端子，并且其中，所述屏蔽结构围绕所述正端子和所述负端子。
5.根据权利要求1-4中任一项所述的微电子组件，其中，所述屏蔽结构具有环绕所述第一金属触点中的一个或多个第一金属触点形成矩形的截面。
6.根据权利要求1-4中任一项所述的微电子组件，其中，所述屏蔽结构的厚度小于所述第一金属触点的厚度。
7.根据权利要求1-4中任一项所述的微电子组件，其中，所述屏蔽结构是第一屏蔽结构，并且所述微电子组件还包括：
在所述第二电介质材料中的第二屏蔽结构，至少部分地围绕所述第二金属触点中的一个或多个第二金属触点。
8.根据权利要求7所述的微电子组件，其中，所述第一屏蔽结构的至少一部分耦接到所述第二屏蔽结构的至少一部分。
9.根据权利要求7所述的微电子组件，其中，所述第一屏蔽结构耦接到所述第一微电子部件上的接地连接部，并且所述第二屏蔽结构耦接到所述第二微电子部件上的参考电压连接部或电源端子。
10.一种微电子组件，包括：
中介层；以及
微电子部件，通过直接接合区域耦接到所述中介层，其中，所述直接接合区域包括金属触点、在所述金属触点中的相邻金属触点之间的直接接合电介质材料、以及在所述直接接合电介质材料中的至少部分地围绕所述金属触点中的一个或多个金属触点的屏蔽结构。
11.根据权利要求10所述的微电子组件，其中，所述屏蔽结构耦接到所述微电子部件上的接地连接部。
12.根据权利要求10所述的微电子组件，其中，所述屏蔽结构耦接到所述中介层上的接地连接部。
13.根据权利要求10所述的微电子组件，其中，所述金属触点包括差分信令互连的正端子和所述差分信令互连的负端子，并且其中，所述屏蔽结构围绕所述正端子和所述负端子。
14.根据权利要求10-12中任一项所述的微电子组件，其中，所述屏蔽结构的至少一部分与个体金属触点接触。
15.根据权利要求10-12中任一项所述的微电子组件，其中，所述屏蔽结构的至少一部分围绕三个或更多个金属触点。
16.根据权利要求10-13中任一项所述的微电子组件，其中，所述屏蔽结构的厚度小于所述金属触点的厚度。
17.一种微电子组件，包括：
中介层；
第一微电子部件；以及
第二微电子部件，所述第二微电子部件具有第一表面和相反的第二表面，所述第二微电子部件在所述第一表面处通过第一直接接合区域耦接到所述中介层并且在所述第二表面处通过第二直接接合区域耦接到所述第一微电子部件，其中，所述第一直接接合区域包括第一金属触点、在所述第一金属触点中的相邻第一金属触点之间的第一电介质材料、以及在所述第一电介质材料中的至少部分地围绕所述第一金属触点中的一个或多个第一金属触点的第一屏蔽结构，并且其中，所述第二直接接合区域包括第二金属触点、所述第二金属触点中的相邻第二金属触点之间的第二电介质材料、以及所述第二电介质材料中的至少部分地围绕所述第二金属触点中的一个或多个第二金属触点的第二屏蔽结构。
18.根据权利要求17所述的微电子组件，其中，所述第一微电子部件是射频(RF)管芯，并且所述第二微电子部件是数字管芯。
19.根据权利要求17或18所述的微电子组件，其中，所述中介层是封装衬底。
20.根据权利要求17或18所述的微电子组件，其中，所述中介层具有第一表面和相反的第二表面，并且所述第二微电子部件耦接到所述中介层的所述第二表面，并且所述微电子组件还包括：
耦接到所述中介层的所述第一表面的电路板。
CN202180077797.3A 2020-12-18 2021-09-24 具有直接接合的微电子组件中的屏蔽结构 Pending CN116457936A (zh)

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