TWI328277B - Stacked structures and methods of forming the same - Google Patents

Stacked structures and methods of forming the same Download PDF

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Publication number
TWI328277B
TWI328277B TW096105458A TW96105458A TWI328277B TW I328277 B TWI328277 B TW I328277B TW 096105458 A TW096105458 A TW 096105458A TW 96105458 A TW96105458 A TW 96105458A TW I328277 B TWI328277 B TW I328277B
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TW
Taiwan
Prior art keywords
wafer
conductive
substrate
rti
support
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TW096105458A
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English (en)
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TW200818439A (en
Inventor
Chao Clinton
Yuan Tsorng-Dih
Hsin Yu Pan
Chen Kim
Peng Mark-Shane
Winata Karta Tjandra
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Taiwan Semiconductor Mfg
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Publication of TW200818439A publication Critical patent/TW200818439A/zh
Application granted granted Critical
Publication of TWI328277B publication Critical patent/TWI328277B/zh

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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0657Stacked arrangements of devices
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Description

1328277 九、發明說明: 【發明所屬之技術領域】 本發明係關於半導體結構(semiconductor structures) 及其製造方法,且特別是關於一種堆疊結構及其製造方 法。 v 【先前技術】 隨著電子產品的發展,半導體技術已廣泛地應用於 • 記憶體、中央處理器(CPU)、液晶顯示器(LCD)、發光二 極體(LED)、雷射二極體以及其他裝置或晶片組之製作。 為了達成高積集度與高速之目標,半導體積體電路之尺 寸持續地微縮。為了達成如此積集度與速度上目標,便 發展出多種不同之材料與技術,以克服製造上之相關問 題。為了達成前述目標,便發展出了包含複合基板 (multiple substrates)之堆疊結構,藉以改善電路之操作速 率。 • 第1圖顯示了習知之一堆疊結構的剖面圖式。 請參照第1圖,顯示了一堆疊結構100,其包括依序 設置於一基板110上之晶片120、130與140,堆疊結構 100亦包括凸塊(bump)結構105。一般而言,晶片120、 130與140具有不同之電路因而具有不同之功能。因此, 晶片120、130、140間尺寸可能互不相同。在此,晶片 120係透過凸塊結構115而耦接於基板110。於晶片120 與基板110間則填入有底膠117。晶月120則包括穿透其 0503-A32632TWF/ShawnChang 5 $身之導電結構123。晶片13〇亦包括穿透其本身之導電 結構133。晶片120與13〇則藉由位於晶片12〇與13〇間 之銲墊125而相互耦接。晶片14〇則包括穿透其本身^ 導電結構143。晶片140經由銲墊135而耦接於晶片13〇。 • 於結合之前,晶片120、130與140需先行通過判別 故障晶片之電性測試。若晶片12〇、13〇與14〇通過此些 '電性測試,其便接著安裝至基板100上。倘若晶片12〇-、 _ 130與140無法通過上述電性測試,晶片12〇、與 將被丟棄。晶片120、130與140則分別包括一主動區(未 顯示),此主動區内含有分別形成於表面121、131與ΐ4ι 上之電晶體、二極體與電路等元件。而於此些主動區操 作時,將於其表面處產生熱能,例如分別於晶片12〇、13〇 與140上之表面121、131與141上之a、b及/或c等處 產生熱能。於部份情形中,產生於此些埶 藉由表面122、⑶及/或142處所逸散。若此些熱能無^ • 逸散時,縱使晶片120、130與HO於安裝前已分別通過 電性測試,此些累積於堆疊結構内之主動區之熱能仍將 • 導致晶片120、130與140之失效情形。 • 此外,於鄰近a處之所產生之電子訊號可透過形成 於晶片120之表面121上之一金屬圖案(未圖式)以及透過 ‘電結構123、125、133與135而傳輪至晶片14〇。上述 傳輸訊號之金屬圖案結構非常複雜。如此之複雜結構的 金屬圖案將增加金屬圖案内相鄰金屬線路間之寄生電容 值。此些寄生電容值將負面地影響堆疊結構之電性表現。 〇503-A32632TWF/ShawnChang 6 1328277 基於前述理由,便需要較為改善之堆疊結構與其製 造方法。 【發明内容】 有鑑於此,本發明提供了一種堆疊結構及其製造方 法。 依據一實施例,本發明提供了 一種堆疊結構,包括: 一第一晶片,耦接於一第一基板,該第一晶片包括 穿透該第一晶片之一第一導電結構;一第二晶片,安裝 於該第一晶片上,該第二晶片經由該第一導電結構而耦 接該第一基板;至少一第一支撐結構,由形成於該第一 基板上之一第二基板所製成,該第一支撐結構至少鄰近 該第一晶片與該第二晶片其中之一,該第一支撐結構之 一頂面大體與其鄰近之該第一晶片與第二晶片其中之一 共平面;以及一散熱片,安裝於該第二晶片上。 依據又一實施例,本發明提供了一種堆疊結構之製 造方法,包括下列步驟: 於一第一基板上依序安裝一第一晶片與一第二晶 片;於該第一晶片上形成至少一第一支撐結構,該第一 支撐結構係鄰近至少該第一晶片與該第二晶片其中之一 且具有大體與其鄰近之至少該第一晶片與該第二晶片之 一共平面之一頂面,其中該第一支撐結構之頂面具有不 少於該第一與第二晶片之較大者内之一晶片區20%之一 區;以及於該第二晶片上安裝一散熱片。 0503-A32632TWF/ShawnChang 1328277 為了讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂,下文特舉一較佳實施例,並配合所附圖示, 作詳細說明如下: 【實施方式】 於下文之較佳實施例及相關圖式中,如”較低”、” 較高”、”水平的”、”垂直的”、”之上”、”之下”、” 上’’、”下”、”頂”與”底”等描述及其衍生之相關描述係 用於指出所欲描述之方位與圖式中所出現之情形。上述 描述係用於解說之用,而非限定實際裝置需要一定需按 照如此之方位設置之用。 第2A-2D圖為一系列剖面圖式,分別顯示了依據不 同實施例中之堆疊結構。 請參照第2A圖,於一實施例中,堆疊結構200包括 依序設置於基板210上之晶片220與230,基板210則例 如為一印刷電路板(PCB)。於部分實施例中,安裝晶片220 與230之方法與晶片220與230之結構可參照同屬本案 讓渡人之申請中美國專利申請案(申請號為11/563,973, 申請日為11/28/2006),並以提及方式將其内文併入於本 文中。 於基板210下方設置有複數個凸塊結構205。凸塊結 構205係用於機械地與電性地連結基板210與如另一印 刷電路板之另 一基板(未顯不)。於部分貫施例中5晶片 220藉由如球柵陣列封裝(BGA)程序或打線結合(wire 0503-A32632TWF/ShawnChang 8 1328277 bonding)程序而安裝於基板210上。晶片220可藉由複數 個凸塊結構215而安裝於晶片220上。再者,基板210 與晶片220間可填入如環氧樹脂之底膠層217,藉以絕緣 此些凸塊結構215並增進如第2A圖所示結構之機械強 度。 晶片220可包括P或N型矽基板、III-V族化合物基 板、如液晶顯示器、電漿顯示器、電激發光顯示器之顯 示基板或發光二極體基板。於部分實施例中,晶片220 包括如記憶體、數位電路、類比電路、晶片上系統(SOC)、 繪圖處理單元(GPU)或者包含多種類型之二極體、電晶體 與電路之其他類型晶片。晶片220亦包括形成並穿透晶 片220之至少一導電結構,例如為導電結構223。導電結 構223形成了黏著於凸塊結構215之晶片220之表面221 以及黏著於晶片230之晶片220之一對應表面222間的 電性連結關係及/或熱連結關係。導電結構223將藉由下 文中第4A-4B圖及相關描述做一詳細描述。晶片220亦 可包括一主動區(未顯示),於主動區内形成有電晶體、裝 置及或電路。晶片220之主動區可位於上黏著於凸塊結 構215之晶片220的表面221上或位於黏著於晶片230 之晶片220的表面222上。透過凸塊結構215,則可形成 位於表面221或表面222上之主動區則可藉由電性耦接 於藉由一導電結構(未顯示),例如形成於基板210之内或 之上之一金屬圖案,而電性搞接於凸塊結構205。 於部分實施例中,晶片220係由分割如晶圓之一基 0503-A32632TWF/ShawnChang 9 1328277 板而形成,此基板包括複數個相同或相似於晶片220之 晶片。於分割程序進行前,將先行基板針對施行電性測 試,即施行晶圓可靠度測試(WAT)或其他電性測試,藉以 判定基板上晶片之可靠度。於完成電性測試後,上述基 板接著經由一後側研磨程序以於進行分割之前薄化基 板。並於分割程序完成後,通過電性測試之晶片220將 安裝於基板210上。 晶片230係安裝於晶片220上並介於隔離結構245 間,在此隔離結構245係採用斜線圖示表示,以如第2A 圖之導電結構235與223之導電結構產生區隔。隔離結 構245可包括如環氧樹脂或其他適用於作為底膠之用之 材料。隔離結構245可為分離區域,或可為延伸並圍繞 晶片230之連續環狀物之一部份。晶片230可藉由如金 屬連結程序、氧化連結程序或黏著連結程序而安裝於晶 片220上。於部分實施例中,晶片230係覆晶安裝於晶 片220上。於其他實施例中,晶片係直接安裝於晶片220 上而無經過覆晶程序。於晶片220與散熱片250間則形 成有複數個支撐結構240。此些支撐結構240將於下文中 詳細描述。 於部分實施例中,晶片230之尺寸少於晶片220之 尺寸,晶片230至少於如第2A圖所示之一長度(即水平) 方向上尺寸少於晶片220之尺寸。晶片230可包括P或N 型石夕基板、III-V族化合物基板、如液晶顯示器、電漿顯 示器、電激發光顯示器之顯示基板或發光二極體基板。 0503-A32632TWF/ShawnChang 10 1328277 於部分之實施例中,晶片230可包括穿透其之至少一導 電構件,例如導電構件235。導電構件235形成了黏著於 一散熱片250之晶片230之表面232與黏著於晶片220 之晶片230之另一表面231間的電性耦接關係及/或熱能 上耦接關係。於部分實施例中,導電結構235相同或相 似於前述之導電結構223。再者,晶片230可包括設置有 電晶體、裝置及或電路(皆未顯示)之主動區(未顯示)。晶 片230之主動區則可形成於黏著於散熱片250之晶片230 的表面232上或黏著於晶片220之晶片230的表面231 上。再者,晶片230之主動區則可藉由如銲墊或凸塊之 至少一導電結構225而耦接於晶片220之主動區。形成 於表面231或表面232上之主動區可猎由導電結構223 與225而耦接於凸塊結構215。導電結構225可包括如鋁 層、銅層、铭銅層、金層、錫錯層或其他導電材料層。 於部分實施例中,於晶片220與230間形成有如環氧樹 脂層之一隔離層227,以隔離晶片220與230上之主動區 與導電結構225。於部分實施例中,隔離層227與隔離結 構245係由相同或不同材料所形成且可為如分散或塗佈 程序等相同程序所形成。值得注意的是,當晶片230與 支撐結構240間之絕緣或導電結構225間絕緣問題不重 要時則可省略隔離層227及/或隔離結構245。 於部分貫施例中’導電結構2 2 5係首先形成於晶片 220上,而晶片230之導電結構235則接著與之相黏結。 於其他實施例中,導電結構225係形成於晶片230之表 0503-A32632TWF/ShawnChang 11 1328277 面231上,而晶片230之導電結構225則接著相黏於晶 片220之導電結構223。而於其他實施例中,當晶片220 與230之導電結構為相互黏著時,晶片220與230則分 別由導電結構235所分別設置而成之導電結構(未顯示)。 於部分實施例中,晶片230係藉由分割如晶圓之一 基板(未顯示)所形成,上述基板包括複數個相同或相似於 晶片230之晶片。形成晶片230之程序則相似於關於晶 片220之先前描述。於經過電性測試、晶圓研磨程序與 晶片分割程序後,晶片230將可安裝於晶片220上。 於如第2A圖所示之實施例中,支撐結構240係形成 於晶片220上。支撐結構240係鄰近或緊貼於晶片230, 其擴展至隔離結構245處並具有大體相同於晶片230高 度之高度。換句話說,支撐結構240之頂面大體與晶片 230之頂面232共平面。於部分實施例中,支撐結構240 之頂面之區域佔晶片220與230中車父大者之晶片區約 20%或更多。舉例來說,如第2A圖所示,晶片220係大 於晶片230,而支撐結構240之頂面區域則佔晶片220之 晶片區之20%或更多。晶片220之晶片區可為環繞晶片 之一切割道(未顯示)所定義出之一實際區域。於部分實施 例中,支撐結構240可由如第2G圖所示之一基板270所 形成,例如為矽基底、III-V族化合物基底、印刷電路板、 導電基板、塑膠基板或其他可形成有導電結構之基板。 於基板270内形成支撐結構240後,基板270可經過一 後側研磨程序處理並沿著支撐結構240間之凹陷處(未標 0503-A32632TWF/ShawnChang 12 1328277 號)施行一切割程序而分割開來。於如第2A圖所示之實 施例中,於支撐結構240内不具有穿透支撐結構240之 導電結構。於上述實施例中,當散熱片250係安裝於晶 片240上時,支撐結構240係位於散熱片250與晶片220 之間,以形成期望之機械支撐作用。 於部分之實施例中,支撐結構240係經由分割包括 複數個結構相同或相似於支撐結構240之一基板所形 成。包括複數個支撐結構240之基板(未顯示)於經過切割 後可獲得具有特定尺寸之元件。於切割基板以得到支撐 結構240之前,基板先需經過後側研磨程序以薄化之。 於其他實施例中,支撐結構240與晶片230可為形 成於相同基板上且藉由相同程序所形成之數個區域(例如 支撐區域與晶片區域)。於此些實施例中,隔離結構245 可為定義形成於基板内支撐結構240與晶片230間之隔 離區域(例如為孔隙或空間或空的環狀物)所取代。而於如 第2F圖所示之其他實施例中,則可省略此些隔離區。切 割道區231係環繞支撐結構區240與晶片區230。換句話 說,支撐區240即為佔據介於切割道區231與晶片區230 之區域。於如第2F圖所示,介於晶片區230與切割道區 231間之支撐結構區240具有不少於150微米之一寬 度” w”。 包括此些支撐結構240與晶片區230之基板於經過 電性測試後,接著施行後側研磨程序與晶片分割程序以 得到複數個晶片,此些晶片則分別包括一對應之支撐結 0503-A32632TWF/ShawnChang 13 1328277 構240與晶片230。晶片接著將安裝於晶片220上。 '散熱片250係安裝於晶片230上並藉由黏著層247 而耦接於包含晶片230之一區域,黏著層247例如為一 導熱材料層。散熱片2 5 0則可包括如銘層、銅層、铭銅 層或其他導熱之膜層。於晶片220與230之主動區(未顯 示)處所產生之熱能,例如分別於晶片220與230之表面 221與231處所產生之熱能,則可為導電結構223、225、 235及/或黏著層247傳導至散熱片250處並於該處逸 散。如前所述,由於支撐結構240係設置於晶片220上 且具有大體相同於晶片230高度之一高度。因此晶片230 與支撐結構240形成了用於安裝散熱片250之一大體平 整表面。 於部份實施例中,支撐結構240包括複數個依序安 裝之基板。舉例來說,支撐結構240可包括兩堆疊基板(未 顯示)。堆疊基板之總高度大體相同於晶片230之高度以 使得堆疊基板之頂面大體與晶片230之頂面232共平 面。如果多重支撐結構具有適當之機械支撐、電子傳遞 及/或熱逸散等功效,則可採用如此之多重支撐結構240。 第2B圖則顯示了 一堆疊結構之一剖面示意圖,其内 支撐結構240包括形成並穿透支撐結構240之至少一導 電結構,例如為導電結構260。於第2A圖與第2B圖中, 相同元件採用了相同編號。導電結構2 6 0之則將詳細描 述於第4A-4B圖等圖式及其相關描述中。如第2B圖所 示,於黏著於凸塊結構215之晶片220的表面221處產 0503-A32632TWF/ShawnChang 14 1328277 生之熱能此時不僅藉由導電結構223、225、235以及黏 著層247而逸散至散熱片250處,其亦藉由導電結構 223、225、260與黏著層247而逸散至散熱片250處。此 外,於晶片220與230之表面222與231所產生之熱能 可不僅藉由導電構件235與黏著層247而傳導至散熱片 250處,其亦可藉由導電構件260與黏著層247而傳導至 散熱片250處。因此,設置於散熱片250與晶片220間 之支撐結構240除了於安裝散熱片250時具有適當之機 械支撐效用,其亦於晶片220與散熱片250間形成適當 之散熱通道。 第2C圖顯示了一實施例之剖面示意圖,其中晶片 220(由隔離區245所定義出之區域)小於晶片230。於第 2A圖與第2C圖中,相同之元件採用相同標號。第2C圖 中所不之導電結構223a-c、225a-c以及235a_c相似於如 第2A圖所示所示之導電結構223、225與235。於實施 例中,導電結構係顯示為223a-c、225a-c以及235a-c。 於第2C圖中,支撐結構240係設置於基板210上。支撐 結構240係位於基底210與晶片230之間,以於安裝晶 片230及或散熱片250時提供適當之機械支撐效用。 第2D圖則為另一實施例之剖面示意圖,其中晶片 220係小於晶片230。於第2B、2C與2D圖中,相同元 件採用相同標號。導電結構在此顯不為223lc、225a-d 以及235a-d。於第2D圖中,安裝於基板210與晶片230 間之支撐結構240不僅於安裝晶片230及/或散熱片250 0503-A32632TWF/ShawnChang 15 1328277 時提供期望之機械支撐效用,其亦形成了熱逸散通道, 因此產生黏著於凸塊215之晶片220的表面221處之熱 能可逸散至散熱片250處。 再者,形成穿透支撐結構240之導電結構260亦於 晶片230與基底210間形成了電性傳輸。舉例來說,晶 片230之主動區(未顯示)係形成於晶片230之表面231 上。電子訊號(例如產生於接近導電結構23 5 a處之晶片之 表面231處之電流)可經由形成於主動區内之一金屬圖案 (未顯示)而傳輸至如第2C圖所示之導電結構225a處。上 述電子訊號可接著藉由導電結構225a與223a傳輸至凸 塊結構215與基板210處。如此,由於形成於如第2C圖 所示之晶片230之主動區内之金屬圖案結構極為複雜。 藉由形成如第2D圖所示之支撐結構240,產生於接近於 導電結構235a之晶片230之表面231之訊號可藉由導電 結構225d與260而傳輸至導電凸塊215。因此,可較為 簡化如第2D圖所示之形成於晶片230之主動區之金屬圖 案(未顯示)之繞線情形。因而可有效地降低產生於主動區 内之寄生電容。
如第2E圖所示之其他實施例中,則依序於基板210 上形成兩支撐結構240a與240b,此些支撐結構240a與 240b分別相同於前述之支撐結構240並分別鄰近或僅靠 晶片220與230,以提供適當之機械支撐、熱逸散及/或 電子傳輸功能。由於支撐結構240a與240b係形成於兩 個晶片膜層中,而非僅環繞頂部晶片230 (請參照第2A 0503-A32632TWF/ShawnChang 16 1328277 圖)或僅環繞底部晶片(請參照第2C圖)。在此,導電結構 260a與260b則可相似或相同於導電結構260。隔離層 245a與245b則可相同或相似於隔離層245。如第2E圖 所示,堆疊結構至少於長度上較晶片220與230之一為 大。第2E圖亦顯示了上述晶片之一或全部更擴展朝向至 少堆疊結構之一邊。於本實施例中,位於頂部之晶片230 向堆疊結構之右側擴展,但結束於其隔離結構245b之左 側。雖然堆疊結構包括延伸超過晶片220與230之尺寸, 只要具有適當之機械支撐、熱逸散及/或電子傳輸等功 能,如此之堆疊結構仍為可行的。 第3A-3F圖則為一系列剖面示意圖,顯示了依據其 他實施例之具有三晶片之堆疊結構。於第3A-3F圖中, 相同於第2A圖中元件將採用第2A圖内標號加上100表 示。 如第3A圖所示,晶片370係安裝於位於隔離結構 369間之一晶片330上,於第3A圖中隔離結構369則標 示為斜線圖示。晶片3 7 0可藉由如金屬連結程序、氧化 連結程序或黏著物連結程序而安裝於晶片330上。於部 份實施例中,晶片370係覆晶安裝於晶片330上。於其 他實施例中,晶片370則直接地安裝於晶片330上而未 經過覆晶程序。 於部份實施例中,晶片370之尺寸至少於如第3A圖 所示之水平方向上小於晶片330之尺寸。晶片370可包 括P或N型石夕基底、III-V族化合物基板、如液晶顯示器、 0503-A32632TWF/ShawnChang 17 1328277 電漿顯示器、電激發光螢光顯示器之顯示基板或發光二 極體基板。於部分之實施例中,晶片370可包括穿透其 之至少一導電構件,例如導電構件367。導電構件367形 成了黏著於散熱片350之晶片370的表面372與黏著於 晶片330之晶片370之另一表面371間之電性耦接情形 及/或熱能耦接情形。於部分實施例中,導電結構367相 同或相似於如前所述之導電結構323或335。再者’晶片 370可包括設置有電晶體、裝置及或電路之主動區(未顯 示)。晶片370之主動區可形成於黏著於散熱片350之晶 片370的表面372上或黏著於晶片330之晶片370的表 面371上。再者,晶片370之主動區可藉由如銲墊或凸 塊之至少·導電結構3 6 5而輛接於晶片330之主動區。 晶片370之主動區亦藉由導電結構365、335、325、323 及/或凸塊結構315而耦接於晶片320之主動區與基板 310。導電結構367可包括如銘層、銅層、铭銅層、金層、 錫鉛層或其他導電材料層。於部分實施例中,於晶片330 與370間形成有如環氧樹脂層之隔離層363,藉以隔離晶 片330與370之主動區以及導電結構365。於部分之實施 例中,隔離層363以及369係由相同或不同材料所形成, 且可藉由如分散或塗佈程序之同一程序例所形成。於部 份實施例中,形成晶片370之分割方法相同或相似於相 關於第2A圖之描述中之分割形成晶片220之方法。經過 電性測試後與後側研磨以及晶片切割後,晶片370可安 裝於晶片330上。 0503-A32632TWF/ShawnChang 18 1328277 於晶片330及/或支撐結構340上可形成如支撐結構 380之另一支撐結構。支撐結構380可形成於鄰近晶片 370處,並具有大體相同於晶片370高度之一高度。換句 話說,支撐結構380之頂面大體與晶片370之頂面372 共平面。於部份實施例中,支撐結構380頂面之區域約 佔晶片320、330與370中較大者之一的區域之20%或更 多。舉例來說,如第3A圖所示,晶片320較晶片330與 370為大,而支撐結構380之頂面約佔晶片320區域之 20%或更多。於部份實施例中,支撐結構380可包括矽基 底、III-V族化合物基板、印刷電路板、導電基板、塑膠 基板、或可形成有導電結構於其内之其他基板。於如第 3A圖所示之實施例中,並無導電結構形成通過支撐結構 340與380。於此些實施例中,支撐結構340與380係位 於散熱片350與晶片320之間,以安裝散熱片350於晶 片370上時形成期望之機械支撐。支撐結構380可按照 前述之形成支撐結構240之方式而形成。於部份實施例 中,晶片370與支撐結構380可由按照前述方式而由同 一基板所形成。 第3B圖顯示了三晶片堆疊結構之剖面示意圖,其内 之支撐結構340與380中包括至少一導電結構,例如為 分別形成穿透支撐結構340與380之導電結構360與 390。在此,於第3A與3B圖中相同元件採用相同標號。 如第3B圖所示,黏著於凸塊結構315之晶片320表面 321上產生之熱不僅藉由導電結構323、325、335、365、 0503-A32632TWF/ShawnChang 19 1328277 367以及黏著層347逸散至散熱片350處且經由導電構件 323、325、360、365、390以及黏著層347而逸散至散熱 片350處。再者,產生於晶片320與330之表面322與 331上之熱可不僅透過導電結構335、365、367以及黏著 層347而傳導至散熱片350且亦透過導電結構335、365、 390以及黏著層347而傳導至散熱片350處。如此,形成 於散熱片350與晶片320間之支撐結構340與380不僅 於安裝散熱片時形成了機械上之支撐,且形成了其間之 熱逸散通道。 於部份之實施例中,支撐結構340或380之一中具 有導電結構360或390。舉例來說,支撐結構380包括形 成並穿透的導電結構390,而支撐結構340則不包括形成 並穿透的導電結構360。對於此實施例而言,支撐結構 380作為熱逸散之通道及/或機械支撐。不具有形成並穿 透之導電結構360的支撐結構340則於安裝散熱片350 時作為機械支撐之用。熟悉此技藝者可適度修正支撐結 構340與380,以於安裝散熱片350時得到期望之熱逸散 及機械支撐效用。 於部份實施例中,晶片370之尺寸大體相似於晶片 320之尺寸。於此些實施例中,支撐結構380以及隔離層 369則可省略。再者,除了熱逸散效用之外,參照先前第 2C-2D圖及相關描述,導電結構325、360、365及/或390 亦可作為用於訊號傳遞之用。於其他實施例中,可於基 板310上鄰近於晶片320處更形成具有或不具有導電結 0503-A32632TWF/ShawnChang 20 1328277 構形成穿透之額外支撐結構。於此些實施例中,分別具 有支撐結構380之晶片320、330與370形成並相鄰。相 同第2E圖之堆疊結構200及其相關描述,雖然堆疊結構 300之水平尺寸大於各別晶片320、330及或370之水平 尺寸,其仍可達成期望之機械支撐、熱逸散及/或訊號傳 遞功效。 第3C圖為顯示了 一實施例之一示意剖面圖,其中晶 片330大於晶片320與370。於第3A圖與第3C圖中, 相之元件採用相同標號。如第3C圖所示,支撐結構340 與380可分別形成於基板310與晶片330之間以及於散 熱片350與晶片330之間。支撐結構340係形成於晶片 320上,以於安裝晶片330、370及/或散熱片350時形成 適當之機械支撐作用。支撐結構380則形成於晶片330 上,以於安裝散熱片350時形成期望之機械支撐作用。 第3D圖為另一實施例之剖面示意圖,其中晶片330 係大於晶片320與370,而支撐結構340與380包括分別 形成並穿透之的導電結構360與390。於第3B圖與第3D 圖中,相同元件採用相同標號。於第3D圖中,支撐結構 340與380分別安裝於基板310與330之間以及散熱片 3 50與晶片330之間,其不僅於安裝晶片330、370及/ 或散熱片350形成了期望之機械支撐作用,其亦藉由導 電結構325、335、360、365及或390而提供了散熱用及 /或訊號傳輸用之通道。 第3E圖則顯示了另一實施例之剖面示意圖,其中晶 0503-A32632TWF/ShawnChang 1328277 片370大於晶片320與330,而支撐結構340與380分別 包括形成並之穿透之導電結構360與390。於第3A圖與 第3E圖中,相同元件採用了相同標號。於第3E圖中, 支撐結構340與380分別形成於基板310與晶片330之 間以及於晶片320與370之間。支撐結構340係安裝於 基板310上以於安裝晶片330、370及/或散熱片350時形 成適當之機械支撐作用。支撐結構380係安裝於晶片320 上以於安裝晶片370及/或散熱片350時形成機械支撐作 用。 第3F圖為依據又一實施例之一剖面示意圖,其中晶 片370係大於晶片320與330。於第3A圖與第3F圖中, 相同元件採用了相同標號。於第3F圖中,支撐結構340 與380分別形成於基板310與晶片330之間以及晶片320 與370間之間,此些支撐結構不僅於安裝晶片330、370 及/或散熱片350時形成適當之機械支撐作用,其亦藉由 導電結構325、360、365、367及/或390而形成了熱逸散 及/或訊號傳遞之通道。 第4A圖與第4B圖為導電結構之放大剖面圖,此些 導電結構可用於如第2A-2E圖與第3A-3F圖中所示之導 電結構 223、235、323、325 ° 如第4A圖所示,導電結構423包括介電層457、阻 障層411、413以及形成並穿透晶片420之導電層419。 導電結構423之一端係藉由形成於晶片420之表面421 或422上之一金屬圖案(未顯示)而耦接於一主動區(未顯 0503-A32632TWF/ShawnChang 22 ;=電4結,423可包括如一介層結構、接觸結構、溝 適用於形成穿過一曰片之;^4重_内連結構或 取牙尥日日片之一導電通路的其他έ士構。 或、商Γ層457可為氧化物層、氣化物層^氧化物層 介ΐ膜電層419與晶片420之其他部份的其他 所r志曰。:電層457可藉由如化學氣相沉積法之方法 阻障層411與413可包括如鈦層、氮化鈦層、 或其他適於降低或避免導電層419之離 之環繞區域中之材料層。阻障層 序所形成。7電= = 晶纖其他導電材料層二括電^ 沉積、物理氣相沉積 與二 4由化學亂相 電化子電鍍、热電電鍍之程序或 八他適用於㈣導電層之程序所形成。 意圖第電結構423之另一實施例之剖面示 处構,1勺括a圖所不’導電結構423更包括一多重膜層 、、,σ稱’其包括導雷展 帝居447、心。 455以及阻障層45卜導 ^介電層457、Γ包=障層451係形成於介電層457 射之導電構件之介其他f用於絕緣多重膜層結 包括如㈣、·、=:層:導電膜層447與455可 層術與455可;含金屬之膜層。導電 電化學電鍍、鼓:雷化學氧相沉積、物理氣相沉積、 …电電鍍等程序或類似程序所形成。阻障 0503-A32632TWF/ShawnChang 23 層451可包括如鈦層、氮化欽詹、组層、氮化组層及其 他適用於避免或降低導電層449之金屬離子擴散進入介 電層457之材料層。導電層449可包括紹層、銅層、銘 銅層、多晶石夕層或其他導電材料層。於部份實施例中, ,夕重膜層結構為形成於晶片420之一主動區上之一 邛,且可猎=於晶片42〇形成之主動區之製程所形成。 於部份貫施例中,當第4A圖與第4B圖之導 似應用分別顯示於第2b、2d、2e、3b、3d#3f = 之於導電結構260、360與390時,當導電層419之絕緣 及/或晶片420内之金屬離子情形並不重要時,可省略導 電結構423内之介電層457及/或阻障層413等結構。 ,機械支撐、熱逸散及或⑽傳料仙之支撐結構可 ^包,其内裝置或形成電晶體之—主動區,但此支撑 二:月<〇包括形成於其上且用於訊號傳輸之一金屬圖 Γ祕如此之金屬圖案較形成於主動區内之裝置或電 日日體為不敏感,故導雷社 ^ 不會負面地影響金屬離子擴散情形將 導㈣盖電性特性’進而允許了省略 ' : 中之導電層457與阻障層412之情形。 社構^ ^圖則顯示了形成如第3 F圖所示之堆疊晶片 、'’口構之一貫把例。於第5 A S Γ1 rk , 元件^0 π 中,相同於第3F圖内之 ,才木用第3F圖内之標號並加上200。 如第5A圖戶斤千,aur- ,^ , ’、日日片區570係形成於一基板501 上。基板501可為P或N刑功甘』 ^ 1 如液曰顯-π +次生矽基板'ιιι-ν族化合物基板、 笔浆顯示器、電激發光顯示器之顯示基 0503-A32632TWF/ShawnChang 1328277 板或發光二極體基板。於此些實施例中,主動區係形成 於基板501之表面502上並對應於晶片區570。導電結構 567則形成並穿透晶片區570。 晶片530係安裝於基板501上,其對應於晶片區570 並藉由導電結構565而耦接晶片區510。晶片530可包括 形成並穿透晶片530之導電結構535。晶片530可藉由金 屬連結程序、氧化連結程序或黏著物連結程序等程序而 安裝於晶片區570上。 如第5B圖所示,於基板501上形成有支撐結構580, 支撐結構580包括形成並穿透之導電結構590且支撐結 構580係藉由如金屬連結程序、氧化連結程序或黏著物 連結程序等程序而連結於基板501。於部份實施例中,支 撐結構580藉由如環氧樹脂層之隔離層569與563與晶 片530相隔離。隔離層560亦可形成於晶片530與晶片 區570之間。於部份實施例中,導電結構590係藉由如 為凸塊或銲墊之導電結構565而耦接於導電結構567。 於部份實施例中,晶片530與支撐結構580係形成 於相同之基板内。舉例來說,基板(未顯示)包括相鄰之預 先定義晶片區(用於形成晶片530)與預先定義支撐結構區 (用於形成支撐結構580)。預先定義晶片區與預先定義支 撐結構區為一既定空間所分隔,於此既定空間内不具有 主動區、電晶體、二極體、電路及/或導電結構。主動區 與導電結構5 3 5係形成於預先定義晶片區内’而導電結 構590則形成於預先定義支撐結構區内。於於預先定義 0503-A32632TWF/ShawnChang 25 1328277 晶片區與預先定義支樓結構區分別形成主動區與導電結 構535與590位後,基板則經由電性測試以檢測無效晶 片。於電性測試後,基板經過研磨程序與晶片分割程序 處理後,進而將基板分割成為複數個晶片,每一晶片中 包括一晶片區530以及一支撐結構區580。於部份實施例 中,晶片具有大體相似於晶片區570之一長度與一寬度。 於此些實施例中,隔離層569則忽略並為前述之既定空 間所取代,而隔離層563則設置於晶片530與支撐結構 580之間。 如第5C圖所示,晶片520係分別安裝於各晶片530 上。晶片520可包括導電結構523且可藉由導電結構525 耦接晶片530。晶片530之安裝可藉由前述安裝晶片520 之方法所達成。 如第5D圖所示,支撐結構540係形成於晶片530及 /或支撐結構580上,支撐結構540内包括形成並穿透之 導電結構560,支撐結構540係藉由如金屬連結程序、氧 化連結程序、黏著物連結程序等程序所安裝。於部份實 施例中,支撐結構540與晶片520之間為如環氧樹脂層 之隔離層545與527所分隔。隔離層527亦可設置於晶 片530與520之間作為隔離導電結構525之用。於部份 實施例中,導電結構560係藉由如凸塊或銲墊之導電結 構525而耦接導電結構590。於其他實施例中,晶片520 與支撐結構540可如前述之晶片530與支撐結構580之 相關描述般而形成於同一之基板内。 0503-A32632TWF/ShawnChang 26 1328277 於其他實施例中,於研磨包括前述預先定義晶片區 (用於形成晶片530或520)以及預先定義支撐結構區(用 於形成支撐結構580或540)之基板後,整個經研磨之基 板將依序安裝於基板501上。接著將此安裝基板經過下 文之切割程序處理。 如第5E圖所示,於晶片520與支撐結構540之上藉 由如球栅陣列封裝程序之程序形成複數個凸塊結構 515。此些凸塊結構515係用於電性連結堆疊晶片與如第 5F圖所示之基板510。 於形成凸塊結構515之後,基板501接著經過研磨 程序研磨,而經過研磨之基板接著沿著隔離層527與563 施行施行一晶片切割程序,進而將此經研磨結構分割成 為複數個堆疊晶片結構。接著顛倒放置堆疊晶片結構並 藉由如第5F圖所示之BGA程序將之安裝於包括複數個 凸塊結構505形成於其下之一基板510上。接著於晶片 520與基板510之間填入底膠層517,以電性隔離此些凸 塊結構515並提供機械支撐與避免膜層剝落之情形。 請參照第5G圖,接著於晶片570上安裝一散熱片 550,並於散熱片550與晶片570間設置一黏著層547。 如前所述,安裝於基板510與晶片570間之支撐結構540 與580形成了晶片520、530、570與基板510之間的熱 逸散通道及/或訊號傳遞通道。 第5H-5L圖為一系列剖面示意圖,分別顯示了具有 不同晶片尺寸之堆疊結構。於第5H-5L圖等圖中,與第 0503-A32632TWF/ShawnChang 27 1328277 5E圖中之相同元件係採用相同標號。 如第5H圖所示,晶片520與570具有大體相同之長 度(水平)尺寸,因此支撐結構580僅安裝於鄰近或緊靠晶 片530之處。 如第51圖所示,晶片520具有至少於長度或水平方 向上大於晶片530與570於該方向上尺寸之一尺寸。於 第51圖中,支撐結構區570a係設置於鄰近晶片區570 處。支撐結構區570a與晶片區570之間為一預先定義空 間570b所分隔,其繪示為一斜線標示。支撐結構區570a 係作為相同於前述之支撲結構540與580之功能。於部 份實施例中,支撐結構區570a包括至少一導電結構 567a。再者,導電結構567a可藉由導電結構565a而耦接 穿透晶片530之導電結構535。 第5J圖顯示了一堆疊結構之示意剖面圖,其包括鄰 近於各晶片520、530與570之一支撐結構。此些堆疊晶 片結構具有至少於其剖面情形中大於晶片520、530與570 尺寸之一尺寸。 如第5K圖所示,由於晶片區570至少於水平方向上 之尺寸小於晶片530與540之一的尺寸,故支撐結構570a 僅形成於晶片區570中,以形成前述結構。於第5L圖中, 晶片530則具有大於晶片540與570長度尺寸之一長度 尺寸。藉由此些形成並穿透晶片520、530與570以及支 撐結構540、570a以及580之導電構件的形成,便可達 成期望之機械支撐、熱逸散及/或電性傳輸等功能。 0503-A32632TWF/ShawnChang 28 1328277 雖然本發明已以較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍内,當可作各種之更動與潤飾,因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。
0503-A32632TWF/ShawnChang 29 【圖式簡單說明】 第1圖顯示了 一習知堆疊結構之剖 第2A 2E圖為一系列剖面示意圖, 本發明之多個實施例中之一堆疊結構; 第2F圖為一上視示意圖 區與支撐結構區; 面情形; 分別顯示了依據 顯示了第2A圖内之晶片 第2G圖為一剖面示意圖,顯示 撐結構; 了形成於基板内之支
弟3A-3F圖為 乐夕U剖面示意圖 —-,·ν 小可 1¾ 本發明之多個實施例中之且有 八乃—、 少厍®品傅; 首第4Α圖與第4Β圖為放大剖面示意圖,分別顯 ‘電結構423之一結構; 了 刀π辩貝不j依據 晶片之一堆疊結構; 第5A-5G圖為一系列剖面示意圖,顯示了形成 3F圖所示之堆疊結構之一製程; 弟
第5H-5L圖為一系列剖面示意圖,分別顯示了具 不同晶片尺寸之堆疊晶片結構。 【主要元件符號說明】 習知部份 100〜堆疊結構; 105、115〜凸塊結構; 110〜基板; 120、130、140〜晶片; 121、m、141、122、132、142〜晶片表面; 123、133、143〜導電結構; 125、135〜銲墊; a〜晶片120上之一處; 〇503-A32632TWF/ShawnChang 30 1328277 b〜晶片130上之一處;c〜晶片140上之一處。 發明部份 200〜堆疊結構; 205、215〜凸塊結構; 210〜基板; 217〜底膠層; 220、230〜晶片; 221〜黏著於凸塊結構之晶片220之表面; 222〜黏著於晶片230之晶片220之表面;
223、235〜導電結構; 225、225a、225b、225c 〜導電結構; 227〜隔離層; 231〜黏著於晶片220之晶片230之表面/切割道區; 232〜黏著於散熱片250之晶片230之表面; 235、235a、235b、235c、235d〜導電結構; 240、240a、240b〜支撐結構; 245、245a、245b〜隔離結構;
247〜黏著層; 250〜散熱片; 260、260a、260b〜導電結構; 270〜基板; 300〜堆疊結構; 305、315〜凸塊結構; 310〜基板; 317〜底膠層; 321〜黏著於凸塊結構315之晶片320表面; 323、325〜導電結構; 327〜隔離層; 320、330、370〜晶片; 0503-A32632TWF/ShawnChang 31 1328277 331〜黏著於晶片320之晶片330之表面; 332〜黏著於散熱片350之晶片330之表面; 340、380〜支撐結構; 345〜隔離結構; 347〜黏著層; 350〜散熱片; 363、369〜隔離層; 365〜導電結構; 323、335、367、360、390〜導電構件; 369〜隔離結構;
371〜黏著於晶片330之晶片370之表面; 372〜黏著於散熱片350之晶片370之表面/晶片370 之頂面; 419〜導電層; 411、413〜阻障層; 420〜晶片; 421、422〜晶片420之表面; 447、449、455〜導電層; 457〜介電層;
423〜導電結構; 451〜阻障層; 5 01〜基板; 510〜晶片區/基板; 523、525〜導電結構; 530〜晶片; 540〜隔離結構; 547〜黏著層; 563〜隔離層; 525 、 535 、 560 、 565 505、515〜凸塊結構; 517〜底膠層; 527、563〜隔離層; 5 3 5〜導電結構, 527、545〜隔離層; 550〜散熱片; 565a、567a〜導電結構; 567、590〜導電結構; 0503-A32632TWF/ShawnChang 32

Claims (1)

  1. (X 第96105458襞專利說明書修正頁;.: 修正日期·· 99.3.15 十、申謗專利範®: 1. 一種堆疊結構’包括: 一第一晶片,耦接於—第_ 穿透該第-晶片之一第一導電結構第-晶片包括 第一晶片,安裝於今楚_BU 由該第一導電結構而轉接“:』曰板上,該第二晶片經 至少一第一支撐結構,由形^於哕 第二5板所製成,該第-支撐上; 二晶片其t之一 ’該第一支 二: -的-頂面及-底面共平面;以,、第-曰曰片其中之 一散熱片,安裝於該第二晶片上。 第一2支樓項所述之堆4結構,其中該 電結構,而:支撐結構之至少-第二導 接該散熱片r 構_㈣第二導電結構而輕 一第3一.曰如申請專利範圍第1項所述之堆疊結構,更包括 rii’输於該第二晶片與該散熱片之間。 .μ料㈣躺述之 ,支標結構’設置於該第二晶片舆該散熱鸯片之更二括 第二主=請專利範圍第4項所述之堆疊結構,盆中該 “構包括穿透該第二支撐結構之至少 接該散熱片而該第二支禮結構係藉由該第二導電結㈣ 0503. A32632TWFl/jychen 34 修正曰期:99.3.15 第96105458號專利說明書修正頁 6· 一種堆疊結構,包括: 、:f 一晶片’耦接於一第一基板,該第-晶片包括 牙透該苐—晶片之一第一導電結構; 晶片經 一第二晶片,安裝於該第一晶片上,該第二 曰片 ^該,—導電結構而耦接該苐一基板,其中該第 至,丨、力。曰曰片區之一切割道區以及鄰近該切割道區之 /一支撐結構區’而該支撐結構區係位於該晶片區盘 =切割道區之間,其中該支撑結構區之—底面及一頂面 刀別^該第二晶片之—底面及—頂面大體共平面;以及 一散熱片,安裝於該第二晶片上。 支^士晴專利範圍第6項所述之堆疊結構,其中該 牙、·,。構〇括穿透該支撐結構區之至少一第二導電結 散熱Γ該切結構11域則經由該第二導f結構_接該 8一.曰如申請專利範圍第6項所述之堆疊結構,更包括 弟二曰曰片,減於該第二晶片與該散熱片之間。 .如申凊專利範圍第6項所述 1-支樓結構,位於該第二晶片與該散熱片二^ 产如申請專利範圍第9項所述之 =撐結構包括穿透該第一支撐結構之至少一第3 而該第—支撺結構經由該第二導電結構而減 至少^隔^料利範圍第6項所述之堆疊結構,更包括 離& ’⑽該晶丨區㈣支撐結構區之間。 〇503-A32632TWF]/jychen 35 J厶〇厶11 第9⑽5458細咖齡胃 :99.3,5 12. 如申請專利範圍第6項所述之堆疊結構,其中該 姜結構區具有不少於150微米之一寬度。 於 第一基板上依序安裝一第一晶片與一第二晶 13, 種堆豐結構之製造方法,包括下列步騾: 片 =該第m形成至少—第—支#結構,該第一 一牙、、、。構係鄰近至少該第一晶片與該第二晶片其中之 片與支1結構區之一底面及-頂面分別與該第-晶 面由—晶片其令之一的一底面及-頂面大體共平 面^中該第-支撐結構之頂面具#不少於該第一 一日曰片之較大者内之-晶片區2()%之—區;以及、 於該第二晶片上安裝一散熱片。 方法圍第13項所述之堆疊結構之製造 ,、中該第—支樓結構包括-第二基板。 方二如:請專利範圍第14項所述之堆叠結構之製造 谨少丰更匕括形成穿透該第二基板之至少一第二導雷锋 ^之乂驟’其中該第_基板係 : 接該散熱片。 λ示一等电結構而耦 16 ·如申清專利範圍第 方法,更包括於哕坌a 、义之堆疊結構之製造 片之步驟。、曰曰片與該散熱片間安裝一第三晶 方法Π更16項所述之堆疊結構之製造 撐結構之步驟。 曰曰肖該散熱片間形成-第二支 〇5〇3-A32632TWFl/jychen 36 1328277 '第96105458號專利說明書修正頁 修正日期:99.3.15 18. 如申請專利範圍第17項所述之堆疊結構之製造 方法,其中該第二支撐結構包括一第二基板。 19. 如申請專利範圍第18項所述之堆疊結構之製造 方法,更包括形成穿透該第二基板之至少一第二導電結 構之步驟,其中該第一基板係藉由該第二導電構件而耦 ' 接該散熱片。 • 20.如申請專利範圍第13項所述之堆疊結構之製造 方法,更包括於不同之晶圓上形成該第一晶片與該第二 • 晶片之步驟。
    0503-A32632TWFl/jychen 37
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4237207B2 (ja) * 2006-07-07 2009-03-11 エルピーダメモリ株式会社 半導体装置の製造方法
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US20080277779A1 (en) * 2007-05-07 2008-11-13 Abhishek Gupta Microelectronic package and method of manufacturing same
KR100871382B1 (ko) * 2007-06-26 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 스택 패키지 및 그의 제조 방법
US8299590B2 (en) * 2008-03-05 2012-10-30 Xilinx, Inc. Semiconductor assembly having reduced thermal spreading resistance and methods of making same
US7948072B2 (en) * 2008-07-25 2011-05-24 Industrial Technology Research Institute Wafer-to-wafer stacking
US8106520B2 (en) * 2008-09-11 2012-01-31 Micron Technology, Inc. Signal delivery in stacked device
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8385073B2 (en) * 2009-07-08 2013-02-26 Flextronics Ap, Llc Folded system-in-package with heat spreader
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8822281B2 (en) 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
TWI441305B (zh) 2010-12-21 2014-06-11 Ind Tech Res Inst 半導體裝置
US9252172B2 (en) 2011-05-31 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
EP2555239A3 (en) * 2011-08-04 2013-06-05 Sony Mobile Communications AB Thermal package with heat slug for die stacks
US9564413B2 (en) 2011-09-15 2017-02-07 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus
US9553162B2 (en) 2011-09-15 2017-01-24 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus
US9153520B2 (en) * 2011-11-14 2015-10-06 Micron Technology, Inc. Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US9129929B2 (en) 2012-04-19 2015-09-08 Sony Corporation Thermal package with heat slug for die stacks
JP2014054718A (ja) * 2012-09-14 2014-03-27 Seiko Epson Corp 電子装置
KR20140106038A (ko) * 2013-02-25 2014-09-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
WO2021146860A1 (zh) * 2020-01-20 2021-07-29 深圳市汇顶科技股份有限公司 堆叠式的芯片、制造方法、图像传感器和电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176137A (ja) * 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
US6867501B2 (en) * 2001-11-01 2005-03-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
US7180173B2 (en) * 2003-11-20 2007-02-20 Taiwan Semiconductor Manufacturing Co. Ltd. Heat spreader ball grid array (HSBGA) design for low-k integrated circuits (IC)

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