TWI555160B - 再造晶片的堆疊封裝及其製造方法 - Google Patents

再造晶片的堆疊封裝及其製造方法 Download PDF

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TWI555160B
TWI555160B TW101132865A TW101132865A TWI555160B TW I555160 B TWI555160 B TW I555160B TW 101132865 A TW101132865 A TW 101132865A TW 101132865 A TW101132865 A TW 101132865A TW I555160 B TWI555160 B TW I555160B
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Taiwan
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wafer
reconstituted
molding compound
package
passivation layer
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TW101132865A
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TW201330212A (zh
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胡坤忠
趙子群
雷澤厄 拉曼 卡恩
皮耶特 佛倫肯
山沛 可芙 卡里卡蘭
陳向東
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美國博通公司
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Description

再造晶片的堆疊封裝及其製造方法
本發明涉及使用再造晶片的堆疊封裝。
用於包括例如至少一個積體電路(IC)的晶片的封裝不斷地傾向于減少封裝件的尺寸而增加封裝件的密度。例如，包括這些封裝件的、諸如手機、耳機、便攜式攝像機、照相機和個人電腦的電子裝置不斷地變得更小。同時，這些電子裝置愈加要求更高級的機能。然而，將更高級的機能併入這些電子裝置中傾向于增加封裝件的尺寸並減少封裝件的密度。例如，併入更高級的機能一般要求額外的電路系統和/或晶片。額外的電路系統和/或晶片會令封裝變得複雜。作為一個示例，除了其他考慮，額外的電路系統和/或晶片會要求額外的輸出/輸入(1/O)墊片(pads)的容納空間。
可具體關注在諸如可擕式裝置的電子裝置中的封裝的複雜化，其中對封裝件的元件空間和佈局選擇受到限制。例如，手機可能有形狀因素，該因素將元件空間約束在特定的尺寸中。一種應對有限元件空間和佈局選擇性的方法是堆疊封裝的晶片以減少其接合的覆蓋區(footprint)。例如，封裝好的晶片中的每一個可被安置在各封裝件內。之後，利用封裝級處理，各封裝件可被彼此堆疊並互相連接。
大致如結合圖中的至少一個所述和/或所描述，並如在申請專利範圍中更全面地描述，本發明涉及利用再造晶片 的堆疊封裝。
(1)一種疊層封裝件，包括：來自頂部再造晶片的頂部晶片，所述頂部再造晶片位於來自底部再造晶片的底部晶片之上；所述頂部晶片和所述底部晶片被隔離佈置而彼此隔離；所述頂部晶片和所述底部晶片通過所述隔離佈置而互連。
(2)根據(1)所述的疊層封裝件，其中，所述頂部晶片和所述底部晶片通過導電通孔而互連。
(3)根據(2)所述的疊層封裝件，其中，所述導電通孔在所述隔離佈置中延伸。
(4)根據(1)所述的疊層封裝件，其中，所述頂部晶片具有頂部再分配層，並且所述底部晶片具有連接至所述頂部再分配層的底部再分配層。
(5)根據(1)所述的疊層封裝件，其中，所述隔離佈置包括與所述頂部晶片側接(flank)的頂部模製化合物和與所述底部晶片側接的底部模製化合物。
(6)根據(5)所述的疊層封裝件，其中，所述頂部模製化合物位於所述底部模製化合物之上。
(7)根據(1)所述的疊層封裝件，其中，所述隔離佈置包括與所述頂部晶片側接的頂部模製化合物，所述頂部晶片和所述底部晶片至少通過所述頂部模製化合物而互連。
(8)一種用於製造疊層封裝件的方法，所述方法包括：在具有底部晶片的底部再造晶片之上堆疊具有頂部晶片的頂部再造晶片，以形成再造晶片疊層；通過隔離佈置以互連所述頂部再造晶片的所述頂部晶片和所述底部再 造晶片的所述底部晶片；分割所述再造晶片疊層，以形成所述疊層封裝件。
(9)根據(8)所述的方法，其中，所述互連包括形成穿過所述隔離佈置的導電通孔。
(10)根據(8)所述的方法，其中，所述隔離佈置包括與所述頂部再造晶片的所述頂部晶片側接的頂部模製化合物和與所述底部再造晶片的所述底部晶片側接的底部模製化合物。
(11)根據(10)所述的方法，其中，所述頂部模製化合物位於所述底部模製化合物之上。
(12)根據(8)所述的方法，進一步包括：在所述分割之前形成用於連接至所述頂部再造晶片的所述頂部晶片和所述底部再造晶片的所述底部晶片的封裝件端子。
(13)根據(8)所述的方法，其中，所述堆疊包括利用鈍化層將所述頂部再造晶片附著至所述底部再造晶片。
(14)一種用於製造疊層封裝件的方法，所述方法包括：在具有底部晶片的底部再造晶片之上堆疊具有頂部晶片的頂部再造晶片，以形成再造晶片疊層，所述頂部晶片具有頂部再分配層，所述底部晶片具有底部再分配層；通過連接所述頂部再分配層至所述底部再分配層，互連所述頂部再造晶片的所述頂部晶片和所述底部再造晶片的所述底部晶片；分割所述再造晶片疊層，以形成所述疊層封裝件。
(15)根據(14)所述的方法，其中，所述互連包括形成穿過所述頂部再分配層的導電通孔。
(16)根據(14)所述的方法，其中，所述互連包括形成穿過所述底部再分配層的導電通孔。
(17)根據(14)所述的方法，其中，所述互連穿過隔離佈置。
(18)根據(14)所述的方法，進一步包括：在所述分割之前形成用於連接至所述頂部晶片和所述底部晶片的封裝件端子。
(19)根據(14)所述的方法，其中，所述堆疊包括利用鈍化層將所述頂部再造晶片附著至所述底部再造晶片。
(20)根據(19)所述的方法，其中，所述鈍化層是所述底部再分配層鈍化而成。
下面的說明包括與本發明的實施方式有關的具體的資訊。本領域技術人員應認識到，本發明可以以不同于本文具體討論過的方式被實施。本申請中的圖和其所附詳細說明僅僅被指向實施例的實施方式。除非額外注明，否則圖中同樣或對應的元件可以被同樣或對應的數字表示。另外，本申請中的圖和插圖一般不是按比例尺繪製的，並且不試圖與實際相關的尺寸相對應。
圖1表示製造疊層封裝件的方法的實施例流程圖100。流程圖100所指示的方法和技術足以說明本發明的至少一種實施方式，不過，本發明的其他實施方式可使用不同於這些流程圖100中的所示的方法和技術。進一步地，當關於圖2A、圖2B、圖2C和圖2D來說明流程圖100時，被發明的發明性概念將不被圖2A、圖2B、圖2C和圖2D 中所示的具體的特徵所局限。
現在參照圖1的流程圖100和圖2A和圖2B，流程圖100包括：在具有底部晶片的底部再造晶片之上堆疊具有頂部晶片的頂部再造晶片以形成再造晶片疊層(流程圖100中的動作170)。圖2A和圖2B顯示根據本發明實施方式在動作170之後的再造晶片疊層280的一些部份。
圖2A表示根據本發明實施方式的再造晶片疊層280的實施例透視圖。再造晶片疊層280包括頂部再造晶片202和底部再造晶片204。如圖2A所示，頂部再造晶片202包括疊層封裝件區域218，該區域被指定用於疊層封裝件的形成，如圖2D中的疊層封裝件284。圖2A中，疊層封裝件區域218是矩形的並穿過再造晶片疊層280而完全延伸。圖2B表示沿橫截面220的再造晶片疊層280的一部分的橫截面圖。
如圖2A所示，頂部再造晶片202包括：頂部晶片214，其中的頂部晶片206、208、210和212被獨立標明；以及頂部模製化合物216(或更一般的“頂部鈍化(passivation)216”)。圖2A顯示以網格(grid)狀的圖案佈置的頂部晶片214，其中每一個都被頂部模製化合物216側接。如圖2A所示，頂部模製化合物216在頂部晶片214中的每一個的周圍形成邊界並與其側接。
在一種實施方式中，頂部晶片214分割自同一晶片，諸如矽片。在另一種實施方式中，頂部晶片214中的至少一個分割自與頂部晶片214中的至少另一個不同的晶片。進一步地，頂部晶片214中的一些或者所有均可具有彼此大體相同的尺寸(例如，寬度、長度、厚度)，或任意的 尺寸均可不同。任何的頂部晶片214可包括積體電路(IC)和/或其他電組件，諸如例如無源(passive)元件。在一種實施方式中，頂部晶片214中的每一個包括IC。
頂部再造晶片202可使用多種手段進行製造。在一種實施方式中，頂部再造晶片202使用嵌入式晶片級的技術進行製造。不過在一些實施方式中，則使用其他或另外的技術。在一種特定實施方式中，頂部晶片214以網格狀圖案被放置在附著層(adhesive layer)上。之後頂部晶片214被用頂部模製化合物216覆蓋以便被嵌入頂部模製化合物216之中。隨後，頂部模製化合物216被薄化以形成頂部再造晶片202。在所示的實施方式中，頂部模製化合物216被薄化到到達頂部晶片214。不過，在其他實施方式中，頂部模製化合物216的層可被保持而覆蓋頂部晶片214中的每一個。
底部再造晶片204可通過使用與頂部再造晶片202相同的、相似的或不同的手段進行製造。相似於頂部再造晶片202的頂部晶片214，底部再造晶片204包括多個底部晶片，其中底部晶片224被顯示在圖2B中。進一步地，相似於頂部晶片214，多個底部晶片可被以與頂部晶片214(未顯示)的網格狀圖案不同的網格狀圖案來佈置。而且，相似於頂部晶片214，底部模製化合物226(或更一般地“底部鈍化226”)在多個底部晶片周圍形成邊界並與其側接。
如圖2B所示，在一些實施方式中，頂部再造晶片202具有頂部再分配層(頂部RDL)228a。附加地或替代地，在一些實施方式中，底部再造晶片204具有底部再分配層 (底部RDL)228b。頂部RDL 228a電連接至頂部晶片206而底部RDL 228b電連接至底部晶片224。頂部RDL 228a和底部RDL 228b包括諸如銅之類的導電材料並分別連通至(route)對應的頂部晶片206和底部晶片224的輸入和/或輸出(I/O)墊片230和232。儘管僅顯示頂部RDL 228a、底部RDL 228b與頂部和底部I/O墊片230和232，但頂部再造晶片202和底部再造晶片204均包括圖2A和圖2B中不可見的多個RDL和I/O墊片。進一步地，多個RDL和I/O墊片中的任意一些可以在頂部再造晶片202和底部再造晶片204的任意一側並可以包括一個或多個級別(levels)或層。如一個示例，頂部RDL 228a和頂部I/O墊片230是在頂部側222上，但在一些實施方式中，其可以在底部側240上(或根本不存在)。
如圖2B所示，頂部RDL 228a在頂部晶片鈍化234(也可被稱為“頂部晶片RDL鈍化234”)上而底部RDL 228b在底部晶片鈍化236(也可被稱為“底部晶片RDL鈍化236”)上。而且，底部RDL鈍化238在底部RDL 228b上。頂部晶片鈍化234、底部晶片鈍化236和底部RDL鈍化238每個都包括介電材料。例如，在本實施方式中，頂部晶片鈍化234、底部晶片鈍化236和底部RDL鈍化238是介電聚合物。在各個實施方式中，頂部晶片鈍化234、底部晶片鈍化236和底部RDL鈍化238可以是彼此相同或不同的材料。
如圖2A和圖2B所示，具有頂部晶片206的頂部再造晶片202被堆疊在具有底部晶片224的底部再造晶片204之上以形成再造晶片疊層280。在一種實施方式中，頂部 再造晶片202獨立於底部再造晶片204而進行製造並且頂部再造晶片202隨後再堆疊至底部再造晶片204之上。在另一種實施方式中，頂部再造晶片202被形成於底部再造晶片204之上和/或上方，從而在底部再造晶片204之上堆疊頂部再造晶片202。雖然頂部再造晶片202被堆疊以使底側240面向下方，但在其他實施方式中，底側240可以向上。而且，在一些實施方式中，底部再造晶片204被用作載體晶片。
在各個實施方式中，頂部RDL 228a、底部RDL 228b、頂部I/O墊片230、底部I/O墊片232、頂部晶片鈍化234、底部晶片鈍化236以及底部RDL鈍化238和/或其他特徵中的任何特徵可在底部再造晶片204之上堆疊頂部再造晶片202之前被形成。在一些實施方式中，頂部RDL 228a、頂部1/O墊片230、頂部晶片鈍化234和/或其他特徵中的至少一些可在底部再造晶片204之上堆疊頂部再造晶片202之後被形成。
在各個實施方式中，堆疊包括利用鈍化層將頂部再造晶片附著至底部再造晶片。例如，在本實施方式中，堆疊包括利用底部RDL鈍化238將頂部再造晶片202附著至底部再造晶片204。因此，再造晶片疊層280可以是薄的以提供高的封裝件密度，如本實施方式所示。
現在參照圖1的流程圖100和圖2C，流程圖100包括：通過隔離佈置(絕緣佈置)(流程圖100中的動作172)以相互連接頂部再造晶片的頂部晶片和底部再造晶片的底部晶片。圖2C顯示再造晶片疊層282的一部分，再造晶片疊層282是根據本發明的實施方式，由在再造晶片疊 層280上進行的動作172得來的。在本實施方式中，頂部再造晶片202的頂部晶片206和底部再造晶片204的底部晶片224通過隔離佈置242而互相連接。
在本實施方式中，隔離佈置242包括頂部模製化合物216、底部模製化合物226、頂部晶片鈍化234、底部晶片鈍化236、底部RDL鈍化238和頂部RDL鈍化244。不過，在其他實施方式中，隔離佈置242可具有不同的組成和/或其他組成。
在一些實施方式中，相互連接包括形成穿過該隔離佈置的導電通孔。不過，相互連接可以以多種方式被完成。圖2C顯示穿過該隔離佈置242而形成的導電通孔250。形成穿過該隔離佈置242的導電通孔250可包括鑽一個穿過頂部模製化合物216、底部模製化合物226、頂部晶片鈍化234、底部晶片鈍化236、底部RDL鈍化238和頂部RDL鈍化244中至少一個的孔(儘管在所示實施方式中，並未穿過頂部RDL鈍化244而進行鑽孔)。可例如使用機械鑽孔機、雷射或其他手段進行鑽孔。
在本實施方式中，穿過底部模製化合物226、頂部晶片鈍化234、底部晶片鈍化236和底部RDL鈍化238以及圖2B中再造晶片疊層280的頂部RDL 228a和底部RDL 228b以進行鑽孔。之後，孔中可被填入導電材料以形成導電通孔250，從而使頂部RDL 228a和底部RDL 228b短路。頂部RDL鈍化244可在之後形成在頂部RDL 228a上。頂部RDL鈍化244包括介電材料，諸如作為一個例子的介電聚合物。注意在各個實施方式中，頂部RDL鈍化244和/或其他組成可形成於鑽孔之前，而本發明並不被所示的 具體的實施方式所限制。
因此，如上所述，在本實施方式中，頂部再造晶片202的頂部晶片206和底部再造晶片204的底部晶片224通過連接頂部RDL 228a和底部RDL 228b而相互連接。更具體地，頂部晶片206和底部晶片224通過形成穿過頂部RDL 228a和可選地穿過底部RDL 228b的導電通孔250而相互連接。
現在參照圖1中的流程圖100和圖2C，流程圖100包括：形成用於連接頂部再造晶片的頂部晶片和底部再造晶片的底部晶片的封裝件端子(流程圖100中的動作174)。例如，圖2C顯示再造晶片疊層282，該再造晶片疊層282是根據本發明的實施方式，由在再造晶片疊層280上進行的動作174得來的。在本實施方式中，封裝件端子252被形成以用於連接到頂部再造晶片202的頂部晶片206和底部再造晶片204的底部晶片224的連接。封裝件端子252也被形成以用於連接到頂RDL 228a和底RDL 228b的連接。
在本實施方式中，封裝件端子252被形成在頂部RDL鈍化244中、凸塊下(under bump)金屬結構層(UBM)254和頂部RDL 228a上。注意UBM 254是可選的(optional)。例如在一些實施方式中，封裝件端子252被形成在頂部RDL鈍化224和頂部RDL 228a上。而且，在本實施方式中，封裝件端子252是焊錫球，該焊錫球是球柵陣列(BGA)的一部分。雖然封裝件端子252被顯示為焊錫球，但封裝件端子252是示例性的，並且除焊錫球之外或替代焊錫球，其他類型的封裝件端子也可被採用。在一種實施方式 中，例如，導電墊片被用作封裝件端子。而且雖然只有一個封裝件端子被顯示，但多個封裝件端子可被形成。例如，再造晶片疊層282可包括用於僅連接到頂部晶片206或底部晶片224或其他組成(未顯示)之一的連接的其他封裝件端子。根據多種實施方式，其他的封裝件端子可以與封裝件端子252同時或不同時形成。
注意，雖然流程圖100將動作174顯示在動作172之後，根據多種實施方式，動作174也可以在動作172之前、之中和/或之後發生。
現參照圖1的流程圖100和圖2C和圖2D，流程圖100包括：分割再造晶片疊層以形成單獨的疊層封裝件(流程100中的動作176)。例如，在本實施方式中，圖2C的再造晶片疊層282被分割以形成疊層封裝件284。更具體地，再造晶片疊層282被沿著圖2A所示的疊層封裝件區域218而分割。當分割該再造晶片疊層282時，可形成其他單獨的疊層封裝件，該疊層封裝件大體與疊層封裝件284相似或不同。
雖然疊層封裝件284僅僅包括頂部晶片206和底部晶片224，但在其他實施方式中，疊層封裝件284包括兩個以上的晶片。例如，疊層封裝件區域218可在頂部再造晶片202和/或底部再造晶片204中包括其他的晶片。如一個示例，圖2A中的頂部晶片208可以在疊層封裝件區域218內。進一步地，其他晶片可使用RDL、導電通孔(例如，導電通孔250)和/或其他手段以穿過隔離佈置242而相互連接、及與頂部晶片206和/或底部晶片224相互連接。例如，頂部RDL 228a可與頂部晶片206和頂部晶片208相 互連接。而且，雖然只有頂部再造晶片202和底部再造晶片204被顯示，但疊層封裝件284可包括來自其他再造晶片的晶片。例如，一個或更多的其他再造晶片可在再造晶片疊層280和282中的任意一個中。而且，額外的RDL、鈍化和其他的組成可被包括於一個或更多的其他的再造晶片中。
進一步地，雖然只有導電通孔250被顯示，但一個以上的導電通孔可被用來連接來自不同再造晶片的晶片。在一種實施方式中，導電通孔至少延伸而穿過隔離佈置242的頂部晶片化合物216。進一步地，當疊層封裝件284包括來自其他再造晶片(未顯示)的晶片時，導電通孔(或其他的相互連接)可將晶片與頂部晶片206和底部晶片224中的一個或兩個相互連接。
在本實施方式中，封裝件端子252和/或其他封裝件端子被形成於分割再造晶片疊層282之前以形成疊層封裝件284。不過，在其他實施方式中，封裝件端子252和/或其他封裝件端子可形成於分割再造晶片疊層282之後。進一步地，在一些實施方式中，頂部晶片206和底部晶片224和/或其他晶片可在分割該再造晶片疊層282之後被相互連接。
然而，通過在分割該再造晶片疊層282之前形成封裝件端子252和/或其他封裝件端子並將頂部晶片206和底部晶片224和/或其他晶片相互連接，可使用晶片級(level)和/或面板(例如基板)級的過程簡單地並高效地形成疊層封裝件284。例如，根據一些實施方式，在頂部再造晶片202和底部再造晶片204上僅使用晶片級和/或面板級的過程 來進行流程圖100所示的方法。因此，除了其他優點，疊層封裝件284可以比使用封裝級處理形成的封裝件更薄。
如圖2D所示，疊層封裝件284包括位於來自底部再造晶片204的底部晶片224之上的來自頂部再造晶片202的頂部晶片206。頂部晶片206和底部晶片224被隔離佈置242而彼此隔離。隔離佈置242包括與頂部晶片206側接的頂部模製化合物216和與底部晶片224側接的底部模製化合物226，其中頂部模製化合物216位於底部模製化合物226之上。
頂部晶片206和底部晶片224通過隔離佈置242而相互連接。更具體地，頂部晶片206和底部晶片224通過頂部模製化合物216而相互連接。在本實施方式中，頂部晶片206和底部晶片224通過導電通孔250而相互連接，該導電通孔在隔離佈置242中延伸。頂部晶片206具有頂部RDL 228a，底部晶片224具有通過導電通孔250而連接至頂部RDL 228a的底部RDL 228b。
因此，如上所述，頂部晶片206和底部晶片224可以通過隔離佈置242而有效地並高效地相互連接。例如，絕緣佈置242可有利於頂部晶片206和底部晶片224之間的相互連接，同時提供對疊層封裝件284足夠的機械支持。進一步地，頂部RDL 228a和底部RDL 228b可容易地通過利用例如穿過隔離佈置242形成的導電通孔250而連接該頂部RDL 228a至底部RDL 228b來相互連接。
通過使用諸如頂部RDL 228a和底部RDL 228b的RDL和晶片和/或面板級的過程，疊層封裝件284可有利地支持更高級的機能，同時容納額外的電路系統和/或晶片而不複 雜化封裝和降低封裝密度。例如，額外的RDL、I/O墊片和/或晶片可容易地如期望地被併入疊層封裝件284而大體不複雜化封裝，並增加了封裝件密度。
而且，在各個實施方式中，載體晶片被用於製造底部再造晶片204並被用作疊層封裝件284的一部分。例如，載體晶片可以是被積體入疊層封裝件284的矽晶片或基板。例如，載體晶片可作為散熱器而被積體入疊層封裝件284。在一種實施方式中，載體晶片是銅引線框架板。
現在參照圖3，圖3表示根據本發明的實施方式的疊層封裝件300的橫截面視圖。疊層封裝件300可使用流程圖100所示的用於製造疊層封裝件的方法進行製造。疊層封裝件300包括頂部晶片306、頂部模製化合物316、底部晶片324、底部模製化合物326、頂部RDL 328a、底部RDL 328b、頂部I/O墊片330、底部I/O墊片332、頂部晶片鈍化334、底部晶片鈍化336、底部RDL鈍化338、頂部RDL鈍化344、隔離佈置342和導電通孔350，分別對應於圖2D的疊層封裝件284中的頂部晶片206、頂部模製化合物216、底部晶片224、底部模製化合物226、頂部RDL 228a、底部RDL 228b、頂部I/O墊片230、底部I/O墊片232、頂部晶片鈍化234、底部晶片鈍化236、底部RDL鈍化238、頂部RDL鈍化244、隔離佈置242和導電通孔250。
儘管疊層封裝件284具有在頂部再造晶片202的頂側222上的封裝件端子252，但除了在頂側222上或替代在頂側222上，至少一個封裝件端子也可被形成在頂部再造晶片204的底側256上。例如，疊層封裝件300包括在底 部晶片324和底側356上的封裝件端子352a、352b、352c、352d、352e、352f和352g。封裝件端子352a、352b、352c、352d、352e、352f和352g可僅用於到底部晶片324的連接或還可用於或轉而用於到頂部晶片306和/或其他晶片的連接。疊層封裝件300還可包括在導電介面358和底側356上的封裝件端子352h和352i。與圖2C中的封裝件端子252類似，封裝件端子352a、352b、352c、352d、352e、352f和352g、352h和352i可以是作為BGA的一部分的焊錫球或可以是其他類型的封裝件端子。儘管未顯示，但在一些實施方式中，疊層封裝件300具有在模製化合物326上的額外的焊錫球以保持機械穩定性。
疊層封裝件300還可具有通過頂部RDL 328a而連接至頂部晶片306的電元件360。在本實施方式中，電元件360是一個獨立的晶片，在頂部RDL鈍化344上，並被互連362a和362b以穿過頂部RDL鈍化344而連接至頂部晶片306。電元件360還可以通過圖3中未顯示的其他RDL和/或其他互連而連接至頂部晶片306。進一步地，至少一個其他的單獨晶片可被以與單獨的晶片306相同或不同的方式而連接至頂部晶片306。在一種實施方式中，在分割一再造晶片疊層之前，電元件360被連接至頂部晶片306以形成疊層封裝件300。在另一種實施方式中，在分割一再造晶片疊層之後，電元件360被連接至頂部晶片306以形成疊層封裝件300(例如在動作176之後)。進一步地，在一些實施方式中，電元件360在封裝件300的底側356上。
因此，如上所述，本發明的實施方式的結果是具有來 自頂部再造晶片的頂部晶片和來自底部再造晶片的底部晶片的疊層封裝件。在各個實施方式中，在仍提供具有高級機能的疊層封裝件的同時，封裝的複雜化和減少的封裝件密度可有利地被避免或最小化。進一步地，應理解，本發明的實施方式提供很大的靈活性(flexibility)以應對有限的元件空間和佈局選擇性。
從上面的說明顯然的是，在不脫離本申請所說明的概念的範圍的前提下，多種技術可被使用以實施這些概念。此外，雖然所述概念已具體參照某些實施方式被說明，本領域技術人員將認識到在不脫離這些概念的精神和範圍的前提下，可以進行形式和細節上的改變。這樣，所說明的實施方式將被全部作為例證性的並無局限的加以考慮。還應理解，本申請並不局限于本文說明的具體的實施方式，在不脫離本發明的範圍的前提下，許多調整、修改和替換是可行的。
100‧‧‧製造疊層封裝件的方法的實施例流程圖
170‧‧‧在具有底部晶片的底部再造晶片之上堆疊具有頂部晶片的頂部再造晶片以形成再造晶片疊層
172‧‧‧通過隔離佈置以相互連接頂部再造晶片的頂部晶片和底部再造晶片的底部晶片
174‧‧‧形成用於連接頂部再造晶片的頂部晶片和底部再造晶片的底部晶片的封裝件端子
176‧‧‧分割再造晶片疊層以形成單獨的疊層封裝件
202‧‧‧頂部再造晶片
204‧‧‧底部再造晶片
206‧‧‧頂部晶片
208‧‧‧頂部晶片
210‧‧‧頂部晶片
212‧‧‧頂部晶片
214‧‧‧頂部晶片
216‧‧‧頂部模製化合物
218‧‧‧疊層封裝件區域
220‧‧‧橫截面
222‧‧‧頂部側
224‧‧‧底部晶片
226‧‧‧底部模製化合物
228a‧‧‧頂部再分配層
228b‧‧‧底部再分配層
230‧‧‧頂部I/O墊片
232‧‧‧底部I/O墊片
234‧‧‧頂部晶片鈍化
236‧‧‧底部晶片鈍化
238‧‧‧底部RDL鈍化
240‧‧‧底部側
242‧‧‧隔離佈置
244‧‧‧頂部RDL鈍化
250‧‧‧導電通孔
252‧‧‧封裝件端子
254‧‧‧凸塊下金屬結構層
280‧‧‧再造晶片疊層
284‧‧‧疊層封裝件
306‧‧‧頂部晶片
316‧‧‧頂部模製化合物
324‧‧‧底部晶片
326‧‧‧底部模製化合物
328a‧‧‧頂部RDL
328b‧‧‧底部RDL
330‧‧‧頂部I/O墊片
332‧‧‧底部I/O墊片
334‧‧‧頂部晶片鈍化
336‧‧‧底部晶片鈍化
338‧‧‧底部RDL鈍化
342‧‧‧隔離佈置
344‧‧‧頂部RDL鈍化
350‧‧‧導電通孔
352a‧‧‧封裝件端子
352b‧‧‧封裝件端子
352c‧‧‧封裝件端子
352d‧‧‧封裝件端子
352e‧‧‧封裝件端子
352f‧‧‧封裝件端子
352g‧‧‧封裝件端子
352h‧‧‧封裝件端子
352i‧‧‧封裝件端子
356‧‧‧底側
358‧‧‧導電介面
360‧‧‧電元件
圖1表示本發明實施方式的用於製造疊層封裝件(stacked package)的方法的實施例流程圖。
圖2A表示本發明的實施方式的再造晶片疊層(reconstituted wafer stack)的實施例透視圖。
圖2B表示本發明的實施方式的再造晶片疊層的一部分的實施例之橫截面圖。
圖2C表示本發明的實施方式的再造晶片疊層的一部分的實施例之橫截面圖。
圖2D表示本發明的實施方式的疊層封裝件的實施例之橫截面圖。
圖3表示本發明的實施方式的疊層封裝件的實施例之橫截面圖。
170‧‧‧在具有底部晶片的底部再造晶片之上堆疊具有頂部晶片的頂部再造晶片以形成再造晶片疊層
172‧‧‧通過隔離佈置以相互連接頂部再造晶片的頂部晶片和底部再造晶片的底部晶片
174‧‧‧形成用於連接頂部再造晶片的頂部晶片和底部再造晶片的底部晶片的封裝件端子
176‧‧‧分割再造晶片疊層以形成單獨的疊層封裝件

Claims (8)

  1. 一種疊層封裝件，包括：底部再造晶片，包括底部晶片以及側面環繞所述底部晶片的底部模製化合物；頂部再造晶片，包括頂部晶片以及側面環繞所述頂部晶片的頂部模製化合物；鈍化層，包夾於所述底部再造晶片與所述頂部再造晶片之間，使得所述鈍化層直接接觸所述底部晶片、所述底部模製化合物、所述頂部晶片以及所述頂部模製化合物；導電通孔，貫穿所述底部模製化合物、所述鈍化層以及所述頂部模製化合物以電性連接所述頂部晶片與所述底部晶片；導電介面，設置於所述底部晶片之底部表面，以電性連接到所述導電通孔；多個底部封裝件端子，所述多個底部封裝件端子的部分位於所述底部晶片相對於所述鈍化層的一面，所述多個底部封裝件端子的另一部分位於所述導電介面之下；以及多個互連；至少一電元件，位於所述頂部晶片之上，透過所述多個互連電性連接所述頂部晶片，其中，所述頂部晶片與所述底部晶片可同時分割自所述底部再造晶片與所述頂部再造晶片所構成的再造晶片疊層。
  2. 如申請專利範圍第1項所述的疊層封裝件，其中，所述頂部晶片具有頂部再分配層，並且所述底部晶片具有連接至所述頂部再分配層的底部再分配層。
  3. 如申請專利範圍第1項所述的疊層封裝件，其中，所述鈍化 層包括與所述底部晶片以及所述底部模製化合物接觸之底部鈍化層以及與所述頂部晶片以及所述頂部模製化合物接觸之頂部鈍化層。
  4. 一種用於製造疊層封裝件的方法，所述方法包括：提供底部再造晶片，包括底部晶片以及側面環繞所述底部晶片的底部模製化合物；提供頂部再造晶片，包括頂部晶片以及側面環繞所述頂部晶片的頂部模製化合物；形成鈍化層，包夾於所述底部再造晶片與所述頂部再造晶片之間，使得所述鈍化層直接接觸所述底部晶片、所述底部模製化合物、所述頂部晶片以及所述頂部模製化合物，以形成再造晶片疊層；形成導電通孔，貫穿所述底部模製化合物、所述鈍化層以及所述頂部模製化合物以電性連接所述頂部晶片與所述底部晶片；分割所述再造晶片疊層，以形成所述疊層封裝件；在所述分割之前，形成設置於所述底部晶片之底部表面以電性連接到所述導電通孔的導電界面；在所述分割之前，形成用於連接至所述頂部再造晶片的所述頂部晶片和所述底部再造晶片的所述底部晶片的多個底部封裝件端子，其中所述多個底部封裝件端子的部分位於所述底部晶片相對於所述鈍化層的一面，所述多個底部封裝件端子的另一部分位於所述導電介面之下；在所述分割之前，形成多個互連；以及在所述分割之前，形成位於所述頂部晶片之上並透過所述多個互連電性連接所述頂部晶片的至少一電元件。
  5. 如申請專利範圍第4項所述的用於製造疊層封裝件的方法，其中，所述頂部晶片具有頂部再分配層，並且所述底部晶片具有連接至所述頂部再分配層的底部再分配層。
  6. 如申請專利範圍第4項所述的用於製造疊層封裝件的方法，其中，所述鈍化層包括與所述底部晶片以及所述底部模製化合物接觸之底部鈍化層以及與所述頂部晶片以及所述頂部模製化合物接觸之頂部鈍化層。
  7. 如申請專利範圍第4項所述的用於製造疊層封裝件的方法，其中，所述頂部晶片具有頂部再分配層，並且所述底部晶片具有連接至所述頂部再分配層的底部再分配層。
  8. 如申請專利範圍第4項所述的用於製造疊層封裝件的方法，其中，所述鈍化層包括與所述底部晶片以及所述底部模製化合物接觸之底部鈍化層以及與所述頂部晶片以及所述頂部模製化合物接觸之頂部鈍化層。
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US9293393B2 (en) 2016-03-22
CN103165585A (zh) 2013-06-19
EP2605279A1 (en) 2013-06-19
TW201330212A (zh) 2013-07-16
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US20130154106A1 (en) 2013-06-20
US20140151900A1 (en) 2014-06-05

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