TWI471987B - 半導體封裝半成品及半導體封裝製程 - Google Patents

半導體封裝半成品及半導體封裝製程 Download PDF

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TWI471987B
TWI471987B TW97116682A TW97116682A TWI471987B TW I471987 B TWI471987 B TW I471987B TW 97116682 A TW97116682 A TW 97116682A TW 97116682 A TW97116682 A TW 97116682A TW I471987 B TWI471987 B TW I471987B
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outer flanges
semiconductor package
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semi
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TW97116682A
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TW200947639A (en
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Ren Yi Cheng
Kuang Hsiung Chen
Chun Hung Hsu
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Advanced Semiconductor Eng
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Priority to TW97116682A priority Critical patent/TWI471987B/zh
Priority to US12/387,266 priority patent/US7927924B2/en
Publication of TW200947639A publication Critical patent/TW200947639A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
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    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/0025—Preventing defects on the moulded article, e.g. weld lines, shrinkage marks
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
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    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
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    • B29C45/14836—Preventing damage of inserts during injection, e.g. collapse of hollow inserts, breakage
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Description

半導體封裝半成品及半導體封裝製程
本發明係關於一種半導體封裝半成品及半導體封裝製程，詳言之，係關於一種具有複數個外凸緣之封膠體之半導體封裝半成品及切割該半成品之半導體封裝製程。
參考圖1，顯示第一種習知半導體封裝半成品之剖面示意圖。該第一種習知半導體封裝半成品1包括一承載板11、複數個晶片12及一封膠體13。該封膠體13係位於該承載板11之一表面上，以包覆該等晶片12。
該第一種習知半導體封裝半成品1之缺點如下。當該第一種習知半導體封裝半成品1在進行灌膠(molding)步驟時，該封膠體13係受高溫加熱形成融熔狀態，以便包覆該等晶片12，而該承載板11及該等晶片12也連帶受高溫影響因而膨脹，使得該承載板11、該封膠體13及該等晶片12在高溫狀態下結合。然上述元件之熱膨脹係數不同，在完成該灌膠步驟而逐漸降溫後，該承載板11、該封膠體13及該等晶片12之收縮程度不同，而導致該第一種習知半導體封裝半成品1產生翹曲(wrapage)現象，如圖2所示。此外，在半導體封裝結構追求輕薄短小的今日，該承載板11及該封膠體13之厚度愈來愈薄，使得翹曲現象更加嚴重。而過度翹曲之半導體封裝半成品1將會造成後續封裝製程之困難與封裝缺失，例如：機台卡料、夾持困難、雷射打印缺失、上球困難與缺球、封裝單體翹曲過大及無法符合共面 性要求等等。
參考圖3，顯示美國專利第US 2004/0029318號所揭示之第二種習知半導體封裝半成品之剖面示意圖。該第二種習知半導體封裝半成品2包括一承載板21、複數個晶片22、一封膠體23及複數個切割線24。該封膠體23係位於該承載板21之一表面上，以包覆該等晶片22。該封膠體23具有複數個凹槽231，該等凹槽231係位於該等晶片22之上方。
該第二種習知半導體封裝半成品2之缺點如下。該第二種習知半導體封裝半成品2在沿該等切割線24切割後，形成複數個封裝單體25。然每一封裝單體25之該封膠體23仍具有一凹槽231，而影響產品外觀。
因此，有必要提供一種創新且具進步性的半導體封裝半成品，以解決上述問題。
本發明提供一種半導體封裝半成品，其包括一承載板及至少一封膠體。該封膠體位於該承載板之一表面上，且具有一本體及複數個外凸緣。該等外凸緣係位於該本體之外圍，且該等外凸緣之高度係大於該本體之高度。
本發明另提供一種半導體封裝製程，其包括以下步驟：(a)提供一承載板，該承載板具有複數個晶片，且該等晶片係電性連接至該承載板；(b)形成至少一封膠體於該承載板上，以包覆該等晶片，該封膠體具有一本體及複數個外凸緣，該等外凸緣之高度係大於該本體之高度；及(c)進行切割步驟，以去除該等外凸緣。
利用該等外凸緣可提升該半導體封裝半成品之剛性，以克服因封膠體及承載板之熱膨脹係數不同，而導致該半導體封裝半成品翹曲之情況。因此，可提升切割後之封裝單體之良率。
參考圖4至圖7，顯示本發明半導體封裝製程之第一實施例之示意圖。首先，參考圖4，提供一承載板31。該承載板31具有複數個晶片32，且該等晶片32係電性連接至該承載板31。在本實施例中，該承載板31係為一基板，而在其他應用中，該承載板31亦可為一導線架。
接著，參考圖5及圖6，形成至少一封膠體33於該承載板31上，以完全包覆該等晶片32，亦即，該等晶片32並未顯露於該封膠體33之外。該封膠體33具有一本體331及複數個外凸緣332，該等外凸緣332係位於該本體331之外圍，且該等外凸緣332之高度係大於該本體331之高度。每一該等外凸緣332之一最高點與該本體331間具有一轉折。
在本實施例中，該封膠體33具有四個外凸緣332，分別位於該本體331之四側，該等外凸緣332係定義出一空間34，且至少一晶片32位於該空間34內。在本實施例中，所有該等晶片32係位於該空間34內，亦即，該等外凸緣332並不位於該等晶片32之正上方。藉由此步驟可得到一第一實施例之半導體封裝半成品3。較佳地，該半導體封裝半成品3更包括複數條切割線35。
最後，進行切割步驟，以去除該等外凸緣332。在本實 施例中，係沿著該等切割線35進行切割，以去除該等外凸緣332，並切割該本體331以形成複數個封裝單體36，每一封裝單體36包括一晶片32，如圖7所示。
請再參考圖5及圖6，該第一實施例之半導體封裝半成品3包括一承載板31及至少一封膠體33。在本實施例中，該半導體封裝半成品3更包括至少一晶片32。
在本實施例中，該承載板31係為一基板，而在其他應用中，該承載板31亦可為一導線架。該等晶片32係附著且電性連接至該承載板31。該封膠體33位於該承載板31之一表面上，係用以完全包覆該等晶片32，亦即，該等晶片32並未顯露於該封膠體33之外。該封膠體33具有一本體331及複數個外凸緣332，在本實施例中，該封膠體33具有四個外凸緣332，分別位於該本體331之四側。該等外凸緣332係位於該本體331之外圍，且該等外凸緣332之高度係大於該本體331之高度，在本實施例中，該等外凸緣332係定義出一空間34，且所有該等晶片32係位於該空間34內，亦即，該等外凸緣332並不位於該等晶片32之正上方。
此外，該等外凸緣332之頂部之剖面係為梯形。在其他應用中，該等外凸緣332之頂部之剖面亦可為其他形狀，例如圖8之外凸緣332A之頂部之剖面係為矩形，圖9之外凸緣332B之頂部之剖面係為另一種梯形。或者，圖10之外凸緣332C之上表面更包括一凹槽3321。在本發明中，由於該等外凸緣332之高度係大於該本體331之高度，所以可提升該半導體封裝半成品3之剛性，以克服因該封膠體33及該 承載板31之熱膨脹係數不同，而導致該半導體封裝半成品3翹曲之情況。因此，可提升該封裝單體36之良率。
參考圖11及圖12，顯示本發明半導體封裝製程之第二實施例之示意圖，本實施例與第一實施例之不同處在於形成至少一封膠體33於該承載板31之步驟。在本實施例中，該封膠體33具有二個外凸緣332，分別位於該本體331之相對之二側，該二外凸緣332係定義出一空間34，且所有該等晶片32係位於該空間34內。藉由此步驟可得到一第二實施例之半導體封裝半成品4。
請再參考圖11及圖12，分別顯示本發明半導體封裝半成品之第二實施例之剖面及俯視示意圖。本實施例之半導體封裝半成品4與第一實施例之半導體封裝半成品3(圖5及圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該半導體封裝半成品4之封膠體33之結構不同。在本實施例中，該封膠體33具有二個外凸緣332，分別位於該本體331之相對之二側，該二外凸緣332係定義出一空間34，且所有該等晶片32係位於該空間34內。
參考圖13及圖14，顯示本發明半導體封裝製程之第三實施例之示意圖，本實施例與第一實施例之不同處在於形成至少一封膠體33於該承載板31之步驟。在本實施例中，該封膠體33具有四個外凸緣332，且更具有複數個內凸緣333，該等外凸緣332係分別位於該本體331之四側，該等內凸緣333之高度係大於該本體331之高度且連接該等外凸 緣332。該等外凸緣332係定義出一空間34，且該等外凸緣332及該等內凸緣333定義出複數個次要空間34A，其中該等次要空間34A係包含於該空間34之內，至少一晶片32位於每一次要空間34A內。藉由此步驟可得到一第三實施例之半導體封裝半成品5。
請再參考圖13及圖14，分別顯示本發明半導體封裝半成品之第三實施例之剖面及俯視示意圖。本實施例之半導體封裝半成品5與第一實施例之半導體封裝半成品3(圖5及圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該半導體封裝半成品5之封膠體33更包括複數個內凸緣333。在本實施例中，該封膠體33具有四個外凸緣332，且更具有複數個內凸緣333，該等外凸緣332係分別位於該本體331之四側，該等內凸緣333之高度係大於該本體331之高度且連接該等外凸緣332，該等外凸緣332及該等內凸緣333定義出複數個次要空間34A，至少一晶片32位於每一次要空間34A內。
參考圖15及圖16，顯示本發明半導體封裝製程之第四實施例之示意圖，本實施例與第一實施例之不同處在於形成複數個封膠體33於該承載板31上，每一封膠體33具有四個外凸緣332，該四個外凸緣332係分別位於每一封膠體33之本體331之四側，該四個外凸緣332定義出一空間34，至少一晶片32位於每一空間34內。藉由此步驟可得到一第四實施例之半導體封裝半成品6。在該第四實施例中之半導體封裝半成品6具有二個封膠體33。
請再參考圖15及圖16，分別顯示本發明半導體封裝半成品之第四實施例之剖面及俯視示意圖。本實施例之半導體封裝半成品6與第一實施例之半導體封裝半成品3(圖5及圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該半導體封裝半成品6係包括複數個晶片32及複數個封膠體33。在本實施例中，每一該封膠體33具有四個外凸緣332，該四個外凸緣332係分別位於每一該封膠體33之本體331之四側，該四個外凸緣332定義出一空間34，至少一晶片32位於每一空間34內。
參考圖17，顯示本發明半導體封裝製程之第五實施例之示意圖，本實施例與第一實施例之不同處在於形成至少一封膠體33於該承載板31之上表面311之後，更包括一形成複數個銲球37於該承載板31之下表面312之步驟。
本發明另外關於一種用於半導體封裝之上模具。參考圖18，顯示本發明用於半導體封裝之上模具之第一實施例之剖面示意圖。該用於半導體封裝之上模具7係用以製成該第一實施例之半導體封裝半成品3(配合參考圖5及圖6)，且包括一第一模穴71及複數個第二模穴72。該第一模穴71係用以製成該半導體封裝半成品3之封膠體33之本體331。該等第二模穴72係用以製成該半導體封裝半成品3之封膠體33之外凸緣332。每一該等第二模穴72與該第一模穴71間具有一轉折。此外，該等第二模穴72係位於該第一模穴71之四側，且該等第二模穴72之深度大於該第一模穴71之深度。
該等第二模穴72之頂部之剖面係為梯形。在其他應用中，該等第二模穴72之頂部之剖面亦可為其他形狀，例如圖19之第二模穴72A之頂部之剖面係為矩形，圖20之第二模穴72B之頂部之剖面係為另一種梯形。或者，圖21之第二模穴72C之頂部更包括一凸槽722。
參考圖22，顯示本發明用於半導體封裝之上模具之第二實施例之剖面示意圖。該用於半導體封裝之上模具8係用以製成該第二實施例之半導體封裝半成品4(配合參考圖11及圖12)，且包括一第一模穴71及複數個第二模穴72。該第一模穴71係用以製成該半導體封裝半成品4之封膠體33之本體331。該等第二模穴72係用以製成該半導體封裝半成品4之封膠體33之外凸緣332。此外，該等第二模穴72係位於該第一模穴71之相對之二側，且該等第二模穴72之深度大於該第一模穴71之深度。
參考圖23，顯示本發明用於半導體封裝之上模具之第三實施例之剖面示意圖。該用於半導體封裝之上模具9係用以製成該第三實施例之半導體封裝半成品5(配合參考圖13及圖14)，且包括一第一模穴71、複數個第二模穴72及複數個第三模穴73。該第一模穴71係用以製成該半導體封裝半成品5之封膠體33之本體331。該等第二模穴72係用以製成該半導體封裝半成品5之封膠體33之外凸緣332。該等第三模穴73係用以製成該半導體封裝半成品5之封膠體33之內凸緣333。此外，該等第二模穴72係位於該第一模穴71之四側，該等第三模穴73係連接該等第二模穴72，且該等 第二模穴72及該等第三模穴73之深度皆大於該第一模穴71之深度。
參考圖24，顯示本發明用於半導體封裝之上模具之第四實施例之剖面示意圖。該用於半導體封裝之上模具10係用以製成該該第四實施例之半導體封裝半成品6(配合參考圖15及圖16)，且包括複數個第一模穴71及複數個第二模穴72。該等第一模穴71係用以製成該半導體封裝半成品6之封膠體33之本體331。該等第二模穴72係用以製成該半導體封裝半成品6之封膠體33之外凸緣332。此外，該等第二模穴72係位於該等第一模穴71之四側，且該等第二模穴72之深度大於該等第一模穴71之深度。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1‧‧‧第一種習知半導體封裝半成品
2‧‧‧第二種習知半導體封裝半成品
3‧‧‧本發明半導體封裝半成品之第一實施例
4‧‧‧本發明半導體封裝半成品之第二實施例
5‧‧‧本發明半導體封裝半成品之第三實施例
6‧‧‧本發明半導體封裝半成品之第四實施例
7‧‧‧本發明用於半導體封裝之上模具之第一實施例
8‧‧‧本發明用於半導體封裝之上模具之第二實施例
9‧‧‧本發明用於半導體封裝之上模具之第三實施例
10‧‧‧本發明用於半導體封裝之上模具之第四實施例
11‧‧‧承載板
12‧‧‧晶片
13‧‧‧封膠體
21‧‧‧承載板
22‧‧‧晶片
23‧‧‧封膠體
24‧‧‧切割線
25‧‧‧封裝單體
31‧‧‧承載板
32‧‧‧晶片
33‧‧‧封膠體
34‧‧‧空間
34A‧‧‧次要空間
35‧‧‧切割線
36‧‧‧封裝單體
37‧‧‧銲球
71‧‧‧第一模穴
72‧‧‧第二模穴
72A‧‧‧第二模穴
72B‧‧‧第二模穴
72C‧‧‧第二模穴
73‧‧‧第三模穴
231‧‧‧凹槽
311‧‧‧上表面
312‧‧‧下表面
331‧‧‧本體
332‧‧‧外凸緣
332A‧‧‧外凸緣
332B‧‧‧外凸緣
332C‧‧‧外凸緣
333‧‧‧內凸緣
721‧‧‧頂部
722‧‧‧凸緣
3321‧‧‧凹槽
圖1顯示第一種習知半導體封裝半成品之剖面示意圖；圖2顯示第一種習知半導體封裝半成品產生翹曲現象之剖面示意圖；圖3顯示美國專利第US 2004/0029318號所揭示之第二種習知半導體封裝半成品之剖面示意圖；圖4至圖7顯示本發明半導體封裝製程之第一實施例之示意圖；圖8至圖10顯示本發明半導體封裝半成品之外凸緣之頂 部之剖面示意圖；圖11顯示本發明半導體封裝半成品之第二實施例之剖面示意圖；圖12顯示本發明半導體封裝半成品之第二實施例之俯視示意圖；圖13顯示本發明半導體封裝半成品之第三實施例之剖面示意圖；圖14顯示本發明半導體封裝半成品之第三實施例之俯視示意圖；圖15顯示本發明半導體封裝半成品之第四實施例之剖面示意圖；圖16顯示本發明半導體封裝半成品之第四實施例之俯視示意圖；圖17顯示本發明半導體封裝半成品之第五實施例之剖面示意圖；圖18顯示本發明用於半導體封裝之上模具之第一實施例之剖面示意圖；圖19至圖21顯示本發明用於半導體封裝之上模具之該等第二模穴之不同態樣示意圖；圖22顯示本發明用於半導體封裝之上模具之第二實施例之剖面示意圖；圖23顯示本發明用於半導體封裝之上模具之第三實施例之剖面示意圖；及圖24顯示本發明用於半導體封裝之上模具之第四實施例 之剖面示意圖。
3‧‧‧本發明半導體封裝半成品之第一實施例
31‧‧‧承載板
32‧‧‧晶片
33‧‧‧封膠體
34‧‧‧空間
35‧‧‧切割線
331‧‧‧本體
332‧‧‧外凸緣

Claims (20)

  1. 一種半導體封裝半成品，包括：一承載板；至少一封膠體，位於該承載板之一表面上，該封膠體具有一本體及複數個外凸緣，該等外凸緣係位於該本體之外圍，該等外凸緣之高度係大於該本體之高度，且每一該等外凸緣之一最高點與該本體間具有一轉折；及至少一晶片，電性連接至該承載板，且該至少一封膠體係完全包覆該至少一晶片，其中該等外凸緣定義出一空間，且該至少一晶片位於該空間內。
  2. 如請求項1之半導體封裝半成品，其中該承載板係為一基板。
  3. 如請求項1之半導體封裝半成品，其中該承載板係為一導線架。
  4. 如請求項1之半導體封裝半成品，其包括一封膠體及複數個晶片，其中該封膠體具有四個外凸緣，分別位於該本體之四側，該等外凸緣係定義出該空間，且所有該等晶片係位於該空間內。
  5. 如請求項1之半導體封裝半成品，其包括一封膠體及複數個晶片，其中該封膠體具有二個外凸緣，分別位於該本體之相對之二側，該二外凸緣係定義出該空間，且所有該等晶片係位於該空間內。
  6. 如請求項1之半導體封裝半成品，其包括一封膠體及複數個晶片，其中該封膠體具有四個外凸緣且更具有複數 個內凸緣，該等外凸緣係分別位於該本體之四側，該等內凸緣之高度係大於該本體之高度且連接該等外凸緣，該等外凸緣及該等內凸緣定義出複數個次要空間，其中該等次要空間係包含於該空間內，至少一晶片位於每一次要空間內。
  7. 如請求項1之半導體封裝半成品，其包括複數個封膠體及複數個晶片，其中每一該封膠體具有四個外凸緣，該等外凸緣係分別位於每一該封膠體之本體之四側，該等外凸緣定義出複數個空間，至少一晶片位於每一空間內。
  8. 如請求項1之半導體封裝半成品，其中該等外凸緣之剖面係為矩形或梯形。
  9. 如請求項1之半導體封裝半成品，其中每一外凸緣之上表面更包括一凹槽。
  10. 一種半導體封裝製程，包括：(a)提供一承載板，該承載板具有複數個晶片，且該等晶片係電性連接至該承載板；(b)形成至少一封膠體於該承載板上，以完全包覆該等晶片，該封膠體具有一本體及複數個外凸緣，該等外凸緣係位於該本體之外圍，該等外凸緣之高度係大於該本體之高度，且每一該等外凸緣之一最高點與該本體間具有一轉折，其中該等外凸緣定義出一空間，且該等晶片位於該空間內；及(c)進行切割步驟，以去除該等外凸緣。
  11. 如請求項10之半導體封裝製程，其中該步驟(a)中，該承載板係為一基板。
  12. 如請求項10之半導體封裝製程，其中該步驟(a)中，該承載板係為一導線架。
  13. 如請求項10之半導體封裝製程，其中步驟(b)係形成一封膠體於該承載板上，該封膠體具有四個外凸緣，分別位於該本體之四側，該等外凸緣係定義出該空間，且所有該等晶片係位於該空間內。
  14. 如請求項10之半導體封裝製程，其中步驟(b)係形成一封膠體於該承載板上，該封膠體具有二個外凸緣，分別位於該本體之相對之二側，該二外凸緣係定義出該空間，且所有該等晶片係位於該空間內。
  15. 如請求項10之半導體封裝製程，其中步驟(b)係形成一封膠體於該承載板上，該封膠體具有四個外凸緣且更具有複數個內凸緣，該等外凸緣係分別位於該本體之四側，該等內凸緣之高度係大於該本體之高度且連接該等外凸緣，該等外凸緣及該等內凸緣定義出複數個次要空間，其中該等次要空間係包含於該空間內，至少一晶片位於每一次要空間內。
  16. 如請求項10之半導體封裝製程，其中步驟(b)係形成複數個封膠體於該承載板上，每一封膠體具有四個外凸緣，該等外凸緣係分別位於每一封膠體之本體之四側，該等外凸緣定義出複數個空間，至少一晶片位於每一空間內。
  17. 如請求項10之半導體封裝製程，其中步驟(b)中該等外凸緣之剖面係為矩形或梯形。
  18. 如請求項10之半導體封裝製程，其中步驟(b)中每一外凸緣之上表面更包括一凹槽。
  19. 如請求項10之半導體封裝製程，其中步驟(c)係進行切割步驟，以去除該等外凸緣，且切割該本體以形成複數個封裝單體，每一封裝單體包括一晶片。
  20. 如請求項10之半導體封裝製程，其中步驟(b)中該至少一封膠體係形成於該承載板之上表面，步驟(b)之後更包括一形成複數個銲球於該承載板之下表面之步驟，步驟(c)係進行切割步驟，以去除該等外凸緣，且切割該本體以形成複數個封裝單體，每一封裝單體包括一晶片。
TW97116682A 2008-05-06 2008-05-06 半導體封裝半成品及半導體封裝製程 TWI471987B (zh)

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JP2004047693A (ja) * 2002-07-11 2004-02-12 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置の製造方法
TW200818349A (en) * 2006-10-14 2008-04-16 Powertech Technology Inc Mold array process for semiconductor packages

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JP2000022044A (ja) * 1998-07-02 2000-01-21 Mitsubishi Electric Corp 半導体装置とその製造方法
JP2002009097A (ja) * 2000-06-22 2002-01-11 Oki Electric Ind Co Ltd 半導体装置とその製造方法
US6469932B2 (en) * 2001-03-12 2002-10-22 Micron Technology, Inc. Memory with row redundancy

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JP2004047693A (ja) * 2002-07-11 2004-02-12 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置の製造方法
TW200818349A (en) * 2006-10-14 2008-04-16 Powertech Technology Inc Mold array process for semiconductor packages

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