200818349 九、發明說明： 【發明所屬之技術領域】 種半導體封裝技術，特別係有關 本發明係有關於一200818349 IX. Description of the invention: [Technical field to which the invention pertains] A semiconductor packaging technology, particularly related to the present invention
Array 於一種半導體封裝之模封陣列處理過程（M〇id Process，MAP)。 【先前技術】Array is a M id process (MAP) for a semiconductor package. [Prior Art]
在半導體封裝領域中，使用模封陣列處理(M〇id Array Process，MAP)可以大幅降低封膠體之製造成本並提昇 封裝效率。如帛i及2圖所示，複數個基板單元ιη 係一體包含在一基板條110内，在黏貼半導體晶片i2〇 於該基板條U0之後，使用模封技術由適當之注洗口 11 3提供一封膠體1 3 〇，其係連續地覆蓋該基板條】1 〇 之該些基板單元Ui之上表面。之後，在接合複數個 外接知子1 5 0於該些基板單元i丨丨之下表面之後沿 著該些基板單元1 1 1之間之切割道n 2切割該封膠體 130與該基板條110’可以得到複數個方塊形的map 半導體封裝構造（如第3圖所示）。 再如第1及2圖所示，在習知模封陣列處理（MAp) 製私中’該封膠體1 3 0在熟化前之前驅材料依模流方 向132以模封方式大面積覆蓋該些基板單元丨丨1，由於 該些晶片1 20會阻擋前驅材料之模流速度，導致該封 膠體130之晶片上模流速度133會小於該封膠體130 之切割道上模流速度1 3 4。導致模封在越後段排列之 晶片1 2 0，該晶片上模流速度1 3 3與該切割道上模流 5In the field of semiconductor packaging, the use of M id Array Process (MAP) can greatly reduce the manufacturing cost of the encapsulant and improve the packaging efficiency. As shown in FIGS. ii and 2, a plurality of substrate units iι are integrally contained in a substrate strip 110, and after the semiconductor wafer i2 is pasted on the substrate strip U0, it is provided by a suitable rinsing port 113 using a molding technique. A colloid 1 3 〇 continuously covers the upper surface of the substrate unit Ui of the substrate strip. Thereafter, the encapsulant 130 and the substrate strip 110' are cut along the scribe line n 2 between the substrate units 1 1 1 after bonding a plurality of external ferrules 150 to the lower surface of the substrate unit i 丨丨A plurality of square-shaped map semiconductor package structures can be obtained (as shown in FIG. 3). As shown in FIGS. 1 and 2, in the conventional mold-molding array processing (MAp) process, the encapsulant 130 is covered in a large area by a mold-sealing direction before the curing.丨丨1, because the wafers 120 will block the mold flow rate of the precursor material, the die flow velocity 133 of the sealant 130 will be less than the die flow velocity of the sealant 130 by 134. Resulting in the die-cutting of the wafer 1 2 0 arranged in the rear stage, the die flow speed of the wafer is 133 and the die flow on the scribe line 5
Ο 200818349 速度134之速度差135會越來越大，在後排晶片 之後侧邊的空氣將會來不及排出，會有MAP封裝 1 3 1的問題（如第3圖所示）。 我國專利證書號數第1240395「陣列型態基板 膠方法」提出一種解決MAP封裝氣泡之半導體 技術。在MAP製程中，在每一基板之上表面兩 有障礙物（obstruction)，以減緩兩側模流速度， 基板之上表面具有晶片部分之模流速度相當，以 MAP封裝氣泡的問題。然而該些障礙物係為額外附 基板上，會增加製程步驟與封裝成本。當採用厚 罩層’則其厚度不足，減緩模流速度的效果有限 由於變更了半導體封裝產品之内含元件組成，需 作產品認證。 【發明内容】 為了解決上述之問題，本發明之主要目的係— 供一種半導體封裝之模封陣列處理過程，能刪 技術中的障礙物並仍具備解決封膠體模流速方 致的問題，達到晶片上模流速度與縱向切割道二 速度兩者匹配一致，不會在晶片旁邊產生封裝 故達到習知障礙物技術特徵嗜略且模流平衡的 本發明的目的及解決其技術問題是採用以_ 方案來實現的。依據本發明，一種半導體封裝： 陣列處理過程。首先’提供—基板條，包含有; 基板單元並定義有複數個在該些基板單元之間丨 12〇 氣泡 上封 封裝 側設 而與 解決 加在 膜銲 ，且 要重 於提 先前 不一 模流 泡， 效。 技術 模封 數個 切割 6 200818349 道’其中該些切割道係由複數個橫向切割道與複數個 縱向切割道所構成。複數個晶片係設置於該基板條之 上表面並位於對應之該些基板單元内。在模封前，一 上模具係設置於該基板條之上表面，該上模具係具有 複數個緩流槽道，其係對應於該些晶片之間之橫向切 割道之上。最後，一封膠體形成於該基板條之上表面， 其係連續地覆蓋該些基板單元，以密封該些晶片，該 封膠體在注膠時係通過該些緩流槽道，以減緩該封膠 D 體在縱向切割道之模流速度。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在前述的模封陣列處理過程中，該些緩流槽道係與形 成該封膠體之模流方向為垂直。 在則述的杈封陣列處理過程中，該些縱向切割道係與 形成5亥封膠體之模流方向為同向。 0 在前述的模封陣列處理過程中，另包含有：形成複數 個銲線，其係電性連接該些晶片至該基板條。 在前述的模封陣列處理過程中，另包含有：設置複數 個外接端子，其係接合在該基板條之下表面。 在前述的半導體封裝之模封陣列處理過程中，該些 外接端子係包含銲球。 在前述的模封陣列處理過程中，該基板條之上表面係 設有複數個注淹口，其係輿最鄰近的橫向切割道為同向排 列。 7 200818349 該些緩流槽道之槽壁 在前述的模封陣列處理過程 中，該些緩Ο 200818349 The speed difference 135 of speed 134 will be larger and larger. After the rear row of wafers, the air on the side will not be able to be discharged, and there will be problems with MAP package 1 3 1 (as shown in Figure 3). China Patent Certificate No. 1240395 "Array Type Substrate Adhesive Method" proposes a semiconductor technology for solving MAP package bubbles. In the MAP process, there are two obstructions on the surface of each substrate to slow the flow velocity of the two sides. The upper surface of the substrate has a mold flow velocity equivalent to that of the wafer portion, and the problem of encapsulating the bubbles with MAP. However, these obstacles are attached to the substrate, which increases the process steps and packaging costs. When a thick cover layer is used, the thickness is insufficient, and the effect of slowing down the mold flow speed is limited. Since the component composition of the semiconductor package product is changed, product certification is required. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a method for processing a packaged array of a semiconductor package, which can remove obstacles in the technology and still have the problem of solving the flow rate of the sealing body mold to reach the wafer. The upper mold flow velocity and the longitudinal scribeway two speeds are matched in the same manner, and the package is not produced next to the wafer, so that the object of the conventional obstacle technical feature is appreciable and the mold flow balance is achieved, and the technical problem is solved by using _ The program to achieve. In accordance with the present invention, a semiconductor package: an array process. Firstly, the 'providing-substrate strip includes: the substrate unit and defines a plurality of 在12〇 bubble encapsulation side between the substrate units, and the solution is added to the film, and is more important than the previous one. Bubble, effect. Technical Molding Several Cuts 6 200818349 The roads consist of a plurality of transverse cuts and a plurality of longitudinal cuts. A plurality of wafers are disposed on the upper surface of the substrate strip and are located in the corresponding substrate units. Prior to molding, an upper mold is disposed on the upper surface of the substrate strip, the upper mold having a plurality of slow flow channels corresponding to the transverse cuts between the wafers. Finally, a gel is formed on the upper surface of the substrate strip, and the substrate unit is continuously covered to seal the wafers. The sealant passes through the slow flow channels during the injection to slow down the seal. The mold flow velocity of the plastic D body in the longitudinal direction. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. During the aforementioned process of patterning the array, the slow flow channels are perpendicular to the direction of the mold flow forming the sealant. In the process of the tantalum-encapsulated array described above, the longitudinal scribe lines are in the same direction as the direction of the mold flow forming the lacquer seal. In the foregoing process of the package array, the method further includes: forming a plurality of bonding wires electrically connecting the wafers to the substrate strip. In the foregoing process of the package array, the method further includes: providing a plurality of external terminals that are bonded to the lower surface of the substrate strip. The external terminals comprise solder balls during the aforementioned packaged array processing of the semiconductor package. In the foregoing process of the mold array, the upper surface of the substrate strip is provided with a plurality of flooding openings, and the most adjacent transverse cutting lanes of the system are arranged in the same direction. 7 200818349 The walls of the slow-flow channels are in the process of the aforementioned sealed array process.
【實施方式】 些注澆口之高度。[Embodiment] The height of some gates.
其係包含有複數個基板單元The system includes a plurality of substrate units
，第4圖係為繪示半導 i*膠體在一基板條上流 配合參閱第5A至5E 示，提供一基板條2 1 0， 211並定義有複數個在該 些基板單元2 1 1之間的切割道2丨2與2丨3。其中，該 些基板單το 2 1 1係為一體連接，該些切割道係由複數 個杈向切割道2 1 2與複數個縱向切割道2丨3所構成。 此外，該基板條210係具有一上表面214與一下表 面215，該上表面214係可供一封膠體24〇之形成（如 第5D圖所示），該下表面2丨5係可供接合複數個外接 端子260，以供對外表面接合（如第5E圖所示）。 如第5 B所示，設置複數個晶片2 2 0於該基板條2 1 〇 之上表面214並位於對應之該些基板單元211内，再 利用打線技術形成複數個銲線2 5 0，該些銲線2 5 0係 電性連接該些晶片220至該基板條210。 之後，如第5C圖所示，設置一上模具230於該基 板條210之上表面214。配合參閱第4圖，該上模具 23 0係具有複數個缓流槽道23 1，其係對應於該些晶片 2 2 0之間之橫向切割道2 1 2之上。在本實施例中，該 8 200818349 基板條2 1 0之上表面2 i 4 #來士 + 係形成有複數個注洗口 216, 其係與最鄰近的彳頁向切到遠· 9 1 °』這212為同向排列（如第4圖 所示）。較佳地，該歧綉#播$ —後μ槽道231之槽壁至該基板條21〇 之下降高度係概約等同該 流槽道2 3 1之形成可如 達到模流緩流之功效。 些注洗口 2 1 6之高度，以使該些緩 同注堯口 2 1 6之緊縮收斂方式 如第5D圖所示，形成一封赚 ^ 封膠體240於該基板條210Figure 4 is a flow diagram showing the semi-conductive i* colloid on a substrate strip. Referring to Figures 5A to 5E, a substrate strip 2 1 0, 211 is provided and a plurality of substrates are defined between the substrate units 2 1 1 . The cutting path is 2丨2 and 2丨3. The plurality of substrate το 2 1 1 are integrally connected, and the scribe lines are composed of a plurality of tangential scribe lines 2 1 2 and a plurality of longitudinal dicing streets 2 丨 3 . In addition, the substrate strip 210 has an upper surface 214 and a lower surface 215. The upper surface 214 is formed by a colloid 24 (as shown in FIG. 5D), and the lower surface 2丨5 is available for bonding. A plurality of external terminals 260 are provided for external surface bonding (as shown in FIG. 5E). As shown in FIG. 5B, a plurality of wafers 220 are disposed on the upper surface 214 of the substrate strip 2 1 并 and located in the corresponding substrate units 211, and a plurality of bonding wires 250 are formed by a wire bonding technique. The bonding wires 250 are electrically connected to the wafers 220 to the substrate strip 210. Thereafter, as shown in Fig. 5C, an upper mold 230 is disposed on the upper surface 214 of the substrate strip 210. Referring to Fig. 4, the upper mold 230 has a plurality of slow flow channels 23 1 corresponding to the transverse cuts 2 1 2 between the wafers 2 2 0 . In this embodiment, the surface of the 8 200818349 substrate strip 2 1 0 2 i 4 # 士士+ is formed with a plurality of rinsing ports 216 which are cut away from the nearest 彳 page and are 9 1 ° 』This 212 is aligned in the same direction (as shown in Figure 4). Preferably, the descending height of the groove wall of the rear dummy channel 231 to the substrate strip 21 is approximately equal to the formation of the flow channel 2 31 to achieve the effect of the mold flow slowing down. . The height of the nozzles 2 1 6 is such that the convergence of the buffers 2 1 6 is convergent. As shown in FIG. 5D, a sealant 240 is formed on the substrate strip 210.
Ο 之上表面2 1 4 ’其係連锖从薄望 思、，地覆盍该些基板單元2丨丨，以 密封該些晶片220，該封膦舻^ 乂对膠體240在注膠時係通過該 些緩流槽道231，以減緩該封膠體24〇在縱向切割道 之模流速度243。再如第4圖所示，所謂「縱向」係指該 些縱向切割道2 1 3係與形成該封膠體24〇之模流方向 24i為同一平行向；所謂「縱向」係指該些橫向切割道 212係與形成該封膠體240之模流方向241為垂直向。 在本實施例中’該些緩流槽道23 i係與形成該封膠體 240之模流方向241為垂直。 再如第4及5D圖所示，由於該封膠體24〇在縱向 切割道上模流速度2 4 3係被該些緩流槽道2 3 1阻擋而 減緩，使得該縱向切割道上模流速度2 4 3接近於一晶 片上模流速度242，即縱向切割道上模流速度243與 晶片上模流速度242兩者速度差比習知速度差更加縮 小，以達模流平衡。故能防止在較後段晶片220之側面產 生MAP封裝氣泡（如第6圖所示）。 最後，如第5 E圖所示，在脫模之後，能在不需附加 ▼200818349 習知内置於封膠體之障礙物的情況下能解決習知MAP封裝 氣/包之問通。如第6圖所示，可以錄切（sawing)方式切判 該封膠體240與該基板條210，得到複數個半導體封裝構 造。 此外，再如第5 E圖所示，上述半導體封裝之模封 陣列處理過程中可另包含一步驟，設置複數個外接端 子2 6 0 ’其係接合在該基板條之下表面。該些外接端 子260係可包含銲球（solder ball)，以製成球格陣列 〇 (BGA)之MAP半導體封裝構造。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟来 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 〇. 第1圖：繪示一種習知半導體封裝之模錡陣列處理過 程中一封膠體在一基板條上產生模流速度差 異之示意圖。 第2圖：繪示習知模封陣列處理過程中封膠體在基板 條上流動速度差異之縱向截面示意圖。 第3圖：習知MAP半導體封裝構造之戴面示意圖。 第4圖··依據本發明之一具體實施例，繪示一種半導 體封裝之模封陣列處理過程中一封膠體在陣 10 .200818349 列型態基板上流動速度一致化之示意圖。 第5Α至5Ε圖：依據本發明之一具體實施例，在該 導體封裝之模封陣列處理過程中其基板條 縱向截面示意圖。 第6圖：依據本發明之一具體實施例，該模封陣列 理過程製成MAP半導體封裝構造之載面示 圖0之上 the upper surface 2 1 4 'the lining of the substrate unit 2 锖 from the thin layer, to seal the wafers 220, the sealing 舻 舻 乂 胶 胶 胶 胶The slow flow channels 231 are used to slow the mold flow rate 243 of the sealant 24 in the longitudinal cut. Further, as shown in Fig. 4, the term "longitudinal" means that the longitudinal scribe lines 2 1 3 are in the same parallel direction as the mold flow direction 24i forming the sealant 24 ;; the so-called "longitudinal" means the transverse cuts. The track 212 is perpendicular to the mold flow direction 241 forming the sealant 240. In the present embodiment, the slow flow channels 23 i are perpendicular to the mold flow direction 241 in which the sealant 240 is formed. Further, as shown in FIGS. 4 and 5D, since the molding flow rate of the sealant 24 〇 on the longitudinal scribe line is retarded by the slow flow channels 213, the dies flow velocity on the longitudinal scribe line is 2 4 3 is close to a die flow velocity 242 on the wafer, i.e., the velocity difference between the die flow velocity 243 on the longitudinal scribe line and the die flow velocity 242 on the wafer is further reduced than the conventional velocity difference to achieve mold flow balance. Therefore, it is possible to prevent MAP encapsulation bubbles from being generated on the side of the rear stage wafer 220 (as shown in Fig. 6). Finally, as shown in Fig. 5E, after the demolding, the conventional MAP package gas/package can be solved without the need to attach the obstacles embedded in the sealant. As shown in Fig. 6, the encapsulant 240 and the substrate strip 210 can be cut in a sawing manner to obtain a plurality of semiconductor package structures. In addition, as shown in FIG. 5E, the semiconductor package packaged array process may further include a step of arranging a plurality of external terminals 2 60 ' to be bonded to the lower surface of the substrate strip. The external terminals 260 can include solder balls to form a MAP semiconductor package construction of a ball grid array (BGA). The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. It is still within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications made by the skilled artisan without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a difference in mold flow velocity of a colloid on a substrate strip during processing of a conventional semiconductor package. Fig. 2 is a longitudinal cross-sectional view showing the difference in flow velocity of the sealant on the substrate strip during the processing of the conventional mold-sealed array. Figure 3: Schematic diagram of the wearing surface of the conventional MAP semiconductor package structure. Fig. 4 is a schematic view showing the flow velocity uniformity of a colloid on a matrix of a matrix of a semiconductor package during processing of a package array of a semiconductor package according to an embodiment of the present invention. Figures 5 to 5 are schematic views of longitudinal sections of a substrate strip during processing of the packaged array of the conductor package in accordance with an embodiment of the present invention. Figure 6 is a diagram showing the surface of the MAP semiconductor package structure in accordance with an embodiment of the present invention.
半 之 處 意 【主要元件符號說明】 110 基板條 111基板單元 112 切割道 113 注澆口 120 晶片 130 封膠體 1 3 1氣泡 132 模流方向 133 晶片上模流速度 134 切割道上模流速度 135 速度差 140 銲線 1 5 0外接端子 210 基板條 211基板單元 212 橫向切割i 213 縱向切割道 2 1 4上表面 215 下表面 216 注澆口 220 晶片 230 上模具 2 3 1緩流槽道 240 封膠體 241模流方向 242 晶片上模流速度 243 縱向切割道上模流速度 244 速度差 250 銲線 260外接端子 11Half point meaning [main component symbol description] 110 substrate strip 111 substrate unit 112 cutting channel 113 gate 120 wafer 130 sealant 1 3 1 bubble 132 mold flow direction 133 die flow speed 134 die flow speed 135 speed Difference 140 Bonding wire 150 External terminal 210 Substrate strip 211 Substrate unit 212 Transverse cutting i 213 Longitudinal cutting lane 2 1 4 Upper surface 215 Lower surface 216 Injection gate 220 Wafer 230 Upper mold 2 3 1 Slow flow channel 240 Sealant 241 Mold flow direction 242 Wafer flow speed 243 Longitudinal cutting path Mold flow speed 244 Speed difference 250 Welding wire 260 External terminal 11