•1307951 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種晶片封裝技術，特別係有關於 一種封裝晶片之模封陣列處理過程（Mold Array Process，MAP)。 【先前技術】 在半導體封裝領域中，對於晶片之保護可利用模製形成 之封膠體逹成，在一具有複數個基板單元之基板條上，複數 • 個封膠體可預先對應於基板單元之尺寸與數量而能單顆獨 立成形。另一模製方法為先以一封膠體全面且連續地形成在 一基板條上’沿著該些基板條之切割道切割該封膠體與 忒基板條，可以得到方塊形的模封陣列處理Array • Process, MAP)型態之半導體封裝構造。因此，模封陣 • 列處理（M〇ld Array Process，MAP)技術相較於早期傳統 的單顆模封方式可以增加模具的通用性、大幅降低封 馨 膠體之製造成本並提昇封裝效率。 如第1圖所示，一種習知MAP型態半導體封裝構造 100主要包含一基板單元110、一晶片12〇與一封膠體。 其與傳統單顆模封之半導體封裝構造最大差異在於，該封膠 體130係具有四周切割面，其係與該基板單元11〇之切割邊 緣為縱向對齊。該晶片120係設置於該基板單元ιι〇上。打 線形成之複數個銲線140電性連接該晶片12〇之銲墊ΐ2ι至 ，基板單元H0’該封勝體13G係以模封方式形成於該基板 早凡U0上，而該基板單元11〇之下方可以設有複數個例如 5 * 1307951 辉球之外接端子150。該封膠體130係具有與該基板單元n〇 對齊之切割面。然而模封陣列處理（MAp)製程容易在晶片 120之一側邊形成一封裝氣泡131。如第2圖所示，這是由 於在模封陣列處理（MAP)製程中，複數個基板單元ιι〇係二 維陣列（two-dimensional arrays)方式配置並一體連接於一基 板條，一封膠體130在熟化前之前驅材料依模封方向132以 模封方式大面積覆蓋該些基板單元11〇，由於該些晶片 會阻擋前驅材料之模流速度，故該封膠體丨3 〇之前驅材料在 該些晶片120的模流速度會小於在該些基板單元ιι〇兩側之 模流速度，且在越後段排列之晶片12〇部分，在該些基板單 π 110中央（具有晶片12〇之部位）的模流覆蓋面積與在該些 基板單元110兩側之模流覆蓋面積差異會越來越大，導致後 排晶片之後側邊的空氣來不及排出，會有MAp封裝氣泡131 的問題。 我國專利證書號數第124〇395「陣列型態基板上封 膠方法」提出一種解決MAP封裝氣泡之半導體封裝 技術。如第3圖所示，另一種習知半導體封裝構造 2〇〇主要包含一基板單元21〇、複數個障礙物22〇、 —晶片230、一封膠體24〇。該些障礙物22〇係設置 在該基板單元2 1 0之上。該晶片230係設置於該基板單 兀* 2 10上。打線形成之複數個銲線25〇電性連接該晶片23〇 之銲墊231至该基板單元21〇，該封膠體24〇係以模封方式 形成於該基板單元21〇上，而該基板單元21〇之下方可以設 有複數個例如銲球之外接端子260。其中，該障礙物220係 6 1307951 可減緩晶片兩側之模流速度，而與該些基 上表面中央且具有晶片2 3 0部分之模流速 解决MAP封裝氣泡的'問題。然而該些障礙物 外附加在基板單元210上，會增加製程步 本。因此’由於增加了半導體封裝構造之 原設計組成，需要重新驗證其產品特性。 【發明内容】 為了解決上述之問題，本發明之主要目 _ 供一種封裝晶片之模封陣列處理過程以/ 條，利用基板條内基板單元的排列變化， 模流速度不一致的問題，達到晶片之中央 流平衡，不會在晶片旁邊產生map封裝 * 能省略先前技術中的封膠内置障礙物 inside encapsulant)，故能以不改變原有半 造的元件與組成仍具備消除MAP封裝氣: 本發明的目的及解決其技術問題是採 方案來實現的。依據本發明，一種封裝晶 列處理過程主要包含以下步驟：提供一基 有複數個呈一維陣列之第一排基板單元與 維陣列之第二排基板單元，在該些第一排 間的切割道係不對準於在該些第二排基板 切割道，以使該些第一排基板單元與該些 單元為非二維陣列。設置複數個晶片於該 表面並位於對應之該些第一排基板單元與 板單元2 1 0 度相當，以 22〇係為額 驟與封裝成 元件，變更 的係在於提 L使用之基板 解決封膠體 與側邊的模 氣泡，並且 (obstruction 導體封裝構 包的功效。 用以下技術 片之模封陣 板條係包含 複數個呈一 基板單元之 單元之間的 第二排基板 基板條之上 該些第二排 7 1307951 基板單兀内。以轉移模製方式形成一封膠體於該基板 :之上表® ’其係連續且實質地覆蓋該些第一排基板 單兀與δ亥些第二排基板單元，以密封該些晶片。另揭 示一種在該模封陣列處理過程所使用之基板條。 本發月的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在岫述。的封裝晶片之模封陣列處理過程中，該些第 排基板單疋之間之切割道係對準於相鄰該些第二排 基板單元之中心線。 在岫述的封裝晶片之模封陣列處理過程中，該封移 體在排基板單元之間之切割道之模流速度係 被該些第二排某；1¾置+ t α 板早疋上的晶片阻擋而減緩，以達模 流平衡。 在前述的封裝晶i 片之Μ封陣列處理過程中，該些第 一排基板單元與該此筮_ —第一排基板|元係為等尺寸之矩BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a chip packaging technique, and more particularly to a mold array processing (MAP) for a packaged wafer. [Prior Art] In the field of semiconductor packaging, the protection of the wafer can be formed by molding the formed encapsulant. On a substrate strip having a plurality of substrate units, the plurality of encapsulants can correspond to the size of the substrate unit in advance. It can be formed separately from the quantity. Another molding method is that a gel is integrally and continuously formed on a substrate strip. The encapsulant and the ruthenium substrate strip are cut along the dicing streets of the substrate strips, and a square-shaped mold array processing Array can be obtained. • Process, MAP) type semiconductor package construction. Therefore, the M〇ld Array Process (MAP) technology can increase the versatility of the mold, greatly reduce the manufacturing cost of the sealant, and improve the packaging efficiency compared to the conventional single-molding method. As shown in FIG. 1, a conventional MAP type semiconductor package structure 100 mainly includes a substrate unit 110, a wafer 12 and a gel. The biggest difference from the conventional single-molded semiconductor package construction is that the encapsulant 130 has a peripheral cut surface that is longitudinally aligned with the cutting edge of the substrate unit 11〇. The wafer 120 is disposed on the substrate unit ιι. The plurality of bonding wires 140 formed by the wire bonding are electrically connected to the bonding pads ι2ι of the wafer 12, and the substrate unit H0' is formed in a die-sealing manner on the substrate U0, and the substrate unit 11〇 A plurality of, for example, 5*1307951 glow ball external terminals 150 may be provided below. The encapsulant 130 has a cut surface aligned with the substrate unit n〇. However, the Molded Array Process (MAp) process tends to form a package of bubbles 131 on one side of the wafer 120. As shown in Fig. 2, this is because in the mold array processing (MAP) process, a plurality of substrate units are arranged in a two-dimensional arrays and integrally connected to a substrate strip, a colloid Before the aging, the precursor material covers the substrate unit 11 大 in a mold-sealing manner in a mold-sealing direction 132. Since the wafers block the mold flow speed of the precursor material, the sealant 丨3 〇 precursor material is The mold flow speed of the wafers 120 may be smaller than the mold flow speeds on both sides of the substrate units, and the wafers 12 排列 arranged in the rear stage are in the center of the substrate π 110 (the portion having the wafer 12 〇) The difference between the mold flow coverage area and the mold flow coverage area on both sides of the substrate unit 110 is larger, resulting in less air being discharged from the side of the rear wafer, and there is a problem that the MAp encapsulates the air bubbles 131. China Patent Certificate No. 124〇395 “Attaching Method on Array Type Substrate” proposes a semiconductor packaging technology for solving MAP package bubbles. As shown in Fig. 3, another conventional semiconductor package structure 2b mainly includes a substrate unit 21, a plurality of obstacles 22, a wafer 230, and a gel 24 〇. The obstacles 22 are disposed above the substrate unit 210. The wafer 230 is disposed on the substrate unit 兀* 2 10 . a plurality of bonding wires 25 formed by wire bonding are electrically connected to the pad 231 of the wafer 23 to the substrate unit 21, and the sealing body 24 is formed on the substrate unit 21 by molding, and the substrate unit A plurality of solder ball external terminals 260 may be provided under the 21 〇. Wherein, the obstacle 220 series 6 1307951 can slow down the mold flow velocity on both sides of the wafer, and solve the problem of the MAP package bubble with the center of the upper surface of the substrate and having the mold flow velocity of the wafer 230 portion. However, the addition of these obstacles to the substrate unit 210 increases the process steps. Therefore, due to the increase in the original design composition of the semiconductor package structure, it is necessary to re-verify the product characteristics. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a method for processing a packaged array of packaged wafers, using the arrangement of substrate units in the substrate strip, and the problem of inconsistent mold flow speed to reach the wafer. The central flow balance does not produce a map package next to the wafer. * It can omit the inside encapsulant of the prior art, so it can still have the MAP encapsulation gas without changing the original semi-constructed components and components: The purpose and solution to its technical problems are achieved through the adoption of the program. According to the present invention, a package crystallographic process mainly comprises the steps of: providing a second row of substrate units having a plurality of first-row substrate units and a dimensional array in a one-dimensional array, and cutting between the first rows The trajectory is not aligned with the second row of substrate dicing streets such that the first row of substrate units and the cells are non-two-dimensional arrays. A plurality of wafers are disposed on the surface and corresponding to the first row of substrate units and the board unit 2 is 10 degrees, and the components are packaged into components by 22 〇, and the modification is based on the substrate used for lifting the package. The colloid and the side of the die bubble, and (obstruction of the conductor package structure. The use of the following technology sheet of the die plate strip system comprising a plurality of substrates in a substrate unit between the second row of substrate substrate strips The second row of 7 1307951 substrate is in a single crucible. A colloid is formed on the substrate by transfer molding: the top sheet® 'the system continuously and substantially covers the first row of substrates and the second and the second The substrate unit is arranged to seal the wafers. Another substrate strip used in the processing of the mold array is disclosed. The purpose of the present invention and solving the technical problems thereof can be further realized by the following technical measures. During the processing of the packaged array of packaged wafers, the dicing lines between the rows of the first row of substrate are aligned with the center lines of the adjacent second row of substrate units. During the processing of the array array, the mold flow velocity of the dicing channel between the substrate units of the sealing body is slowed down by the wafers on the second row of the first row; Flow balance. During the processing of the encapsulated array of the packaged crystal i-chip, the first row of substrate units and the first row of substrates are elementally sized
形、六角形或八角形。 在前述的封裝晶片 有：形成複數個銲線 板條。 之模封陣列處理過程中，另包含 I係電性連接該些晶片至該基 在前述的封裝晶片 有：設置複數個外接 表面。 之模封陣列處理過程中，另包含 ^子’其係接合在該基板條之下 在前述的封裝晶片 接端子係包含銲球。 之模封陣列處理過程中 該些外 8 1307951 在前述的封裝晶片之模封陣列處理過程中，該基板 條之上表面係設有至少一注洗口 ，其係與最鄰近的該 些第一排基板單元為同側排列。 在前述的封裝晶片之模封陣列處理過程中，由該注 澆口提供之模流方向係與該些第一排基板單元之排列 方向概呈垂直。 【實施方式】Shape, hexagon or octagon. In the aforementioned package wafer, a plurality of wire bond slats are formed. In the process of the package array, the I system electrically connects the wafers to the substrate. The package wafer has a plurality of external surfaces. During the process of the package array, a further sub-mount is bonded under the substrate strip. The package wafer terminal comprises a solder ball. The outer surface of the packaged array is processed during the processing of the packaged array of the packaged wafer. The upper surface of the substrate strip is provided with at least one filling port, which is adjacent to the first one. The row of substrate units are arranged on the same side. During the processing of the package array of the packaged wafer, the direction of the mold flow provided by the gate is substantially perpendicular to the arrangement direction of the first row of substrate units. [Embodiment]
在本發明之第一具體實施例中，配合參閱第4A至 4 F圖’揭示一種封裝晶片之模封陣列處理過程。 首先，如第4A圖所示，提供一基板條310，其係 包含有複數個呈一維陣列之第一排基板單元3 1 1與複 數個呈一維陣列之第二排基板單元3 12，其中第一排 基板單元311與第二排基板單元312係為排與排之鄰 接間隔。所謂「一維陣列」（one_dimensi〇nai aj_rayS) 係指複數個元件為線性等距排列。此外，如第4E圖所 示，該基板條310係具有一上表面313與一下表面 3 1 4，該上表面3 1 3係可供一封膠體3 3 〇之形成，該下 表面 3 14係可供接合複數個外接端子34〇，以供對外 表面接合。在本實施例中，該基板條31()係可為一印刷 電路板，其内部設有兩面導通之線路結構。此外，該此第 一排基板單元311與該些第二排基柄罝-"一 丞板早兀3 1 2係可為 等尺寸之矩形、六角形或八角形。右 任本實施例中，第 -排基板單元3"肖第二排基板單& 312係具有概呈 矩形之上表面。 9 1307951 請再參閱第4A圖’在該些第一排基板單元311之 間的切割道3 11 A係不對準於在該些第二排基板單元 3 1 2之間的切割道3 1 2A’以使該些第一排基板單元3丄i 與該些第二排基板單元3 1 2為非二維陣列。所謂「非 二維陣列」（Non two-dimensional arrays)係指複數個元 件的縱向與橫向排列並不是如同象棋棋盤般對齊的矩 陣排列。 在本實施例中’在該些第一排基板單元3 1 1之間之 籲 切割道3 1 1 A係對準於相鄰該些第二排基板單元3 i 2 之中心線。該基板條3 1 0之上表面3 1 3係設有至少一 注澆口 315’其係與最鄰近的該些第一排基板單元311 為同側排列，該注澆口 3 1 5係鄰近如第4a圖所示之其 • 中一較近第一排基板單元3 1 1之側向切割道3丨丨b。 如第4B圖所示，設置複數個晶片320於該基板條 310之上表面313並位於對應之該些第一排基板單元 鲁 311與該些第二排基板單元312内。之後，如第4C圖 所示’利用打線技術形成複數個銲線3 2 2。配合參閱 第4 E圖’該些锌線3 2 2係電性連接該些晶片3 2 0之複 數個銲墊321至該基板條310。 如第4D與4E圖所示’以轉移模製（transfei· molding) 方式形成一封膠體330於該基板條310之上表面313, 其係連續且實質地覆蓋該些第一排基板單元311與該 些第二排基板單元3 1 2，以密封該些晶片3 2 0。如第 4 D圖所示，在本實施例中，由該注澆口 3丨5提供之模 10 1307951 流方向33 1係與該些第一排基板單元3 11之排列方向 概呈垂直。由於該封膠體330在該些第一排基板單元 3 1 1之間之切割道3 11 A之模流速度係被該些第二排基 板单元312上的晶片320阻擋而減緩，以達模流平衡。 故能防止在較後段晶片320之侧面產生]ViAP封裝氣泡。如 第4E圖所示’在脫模之後’能在不需附加習知内置於封 膠體之障礙物的情況下能解決習知MAP封裝氣泡之問題。 最後’如第4F圖所示’可以鋸切（sawing)方式切割該 封膠體330與該基板條310’得到複數個半導體封裝構造。 此外’再如第4E圖所示’上述封裝晶片之模封陣 列處理過程中可另包含一步驟：設置複數個外接端子 3 40 ’其係接合在該基板條310之下表面314。該些外 接端子340係可包含銲球（s〇iderball)，以製成球格陣 列（BGA)之半導體封裝構造。 因此’在上述之半導體封裝構造中，能在模封陣列處 理（MAP)過程中達到該基板條31〇在每—封裝單元3ΐι 與3 1 2之晶片3 2 0中央與側邊模流之平衡，不會在曰曰 片320後側旁邊產生MAP封裝氣泡。僅以原有元件 的基板單元之排列變化便可達到解決MAP封裝氣泡 問題之功效，不需要在封膠體内額外附加障礙物。 請參閱第5A至5C圖’在本發明之第二具體實施 例中，揭示另一種封裝晶片之模封陣列處理過程。如 5A圖所示，首先提供一基板條41〇，其係包含有複數 個呈一維陣列之第一排基板單元4丨丨與複數個呈—维 1307951 陣列之第二排基板單元412。並且，在該些第一排& 板單元4 1 1之間的切割道4 1 1 A係不對準於在該些第_ 排基板單元4 1 2之間的切割道4 1 2 A，以使該些第__ ?非 基板單元411與該些第二排基板單元412為「非二 陣列」。該基板條 4 1 0之上表面係設有至少一注> 口 4 1 3，其係與最鄰近的該些第一排基板單元4丨丨為同側 排列。在本實施例中，該些第一排基板單元4 1 1虛^ 與5亥In a first embodiment of the invention, reference is made to Figures 4A through 4F to disclose a process for patterning arrays of packaged wafers. First, as shown in FIG. 4A, a substrate strip 310 is provided, which comprises a plurality of first row of substrate units 31 in a one-dimensional array and a plurality of second row of substrate units 3 12 in a one-dimensional array. The first row of substrate units 311 and the second row of substrate units 312 are adjacent to each other in rows and rows. The so-called "one-dimensional array" (one_dimensi〇nai aj_rayS) means that a plurality of elements are arranged linearly equidistantly. In addition, as shown in FIG. 4E, the substrate strip 310 has an upper surface 313 and a lower surface 3 1 4, and the upper surface 3 1 3 is formed by a colloid 3 3 ,, and the lower surface 3 14 is formed. A plurality of external terminals 34A can be joined for bonding to the outer surface. In this embodiment, the substrate strip 31() may be a printed circuit board having a line structure in which both sides are conductive. In addition, the first row of substrate units 311 and the second rows of base handles -' a rafter 3 1 2 series may be of equal size rectangular, hexagonal or octagonal. In the present embodiment, the first row of substrate units 3 " the second row of substrate sheets & 312 has a substantially rectangular upper surface. 9 1307951 Please refer to FIG. 4A again. 'The scribe line 3 11 A between the first row of substrate units 311 is not aligned with the scribe line 3 1 2A' between the second row of substrate units 3 1 2 The first row of substrate units 3 丄 i and the second row of substrate units 3 1 2 are non-two-dimensional arrays. By "Non two-dimensional arrays" is meant that the longitudinal and lateral alignment of a plurality of elements is not a matrix arrangement aligned as a chess board. In the present embodiment, the scribe line 3 1 1 A between the first row of substrate units 3 1 1 is aligned with the center line of the adjacent second row of substrate units 3 i 2 . The upper surface of the substrate strip 310 is provided with at least one gate 315' which is arranged on the same side as the first row of the first row of substrate units 311, and the gate 3 3 is adjacent to each other. The first one of the first row of substrate units 3 1 1 is closer to the side cutting lane 3丨丨b as shown in Fig. 4a. As shown in FIG. 4B, a plurality of wafers 320 are disposed on the upper surface 313 of the substrate strip 310 and located in the corresponding first row of substrate units 311 and the second row of substrate units 312. Thereafter, as shown in Fig. 4C, a plurality of bonding wires 3 2 2 are formed by a wire bonding technique. Referring to FIG. 4E, the zinc wires 3 2 2 are electrically connected to the plurality of pads 321 of the wafers 300 to the substrate strips 310. As shown in FIGS. 4D and 4E, a gel 330 is formed on the upper surface 313 of the substrate strip 310 by a transfer molding method, which continuously and substantially covers the first row of substrate units 311 and The second row of substrate units 3 1 2 to seal the wafers 300 . As shown in Fig. 4D, in the present embodiment, the flow direction 33 1 of the mold 10 130795 provided by the gate 3 丨 5 is substantially perpendicular to the arrangement direction of the first row of substrate units 3 11 . Since the mold flow speed of the dicing block 3 11 A between the first row of substrate units 31 is blocked by the wafer 320 on the second row of substrate units 312, the mold flow is slowed down. balance. Therefore, it is possible to prevent the generation of [ViAP package air bubbles" on the side of the rear stage wafer 320. As shown in Fig. 4E, 'after demolding', the problem of the conventional MAP encapsulating bubble can be solved without the need to additionally attach an obstacle built in the encapsulant. Finally, as shown in Fig. 4F, the encapsulant 330 and the substrate strip 310' can be sawed in a sawing manner to obtain a plurality of semiconductor package structures. Further, in the process of molding the array of the packaged wafers as shown in Fig. 4E, a further step may be included in which a plurality of external terminals 3 40 ' are attached to the lower surface 314 of the substrate strip 310. The external terminals 340 can include solder balls to form a semiconductor package structure of a ball grid array (BGA). Therefore, in the above-described semiconductor package structure, the balance between the center and the side mold flow of the substrate strip 31 in the package array processing (MAP) can be achieved in the wafer 3 2 0 of each of the package units 3 ΐ and 3 1 2 MAP encapsulation bubbles are not generated next to the back side of the cymbal 320. The effect of solving the MAP package bubble problem can be achieved only by the arrangement of the substrate units of the original components, and no additional obstacles are required in the sealant body. Referring to Figures 5A through 5C, in a second embodiment of the present invention, another packaged array process for packaging wafers is disclosed. As shown in FIG. 5A, a substrate strip 41 is first provided, which comprises a plurality of first row of substrate units 4' in a one-dimensional array and a plurality of second row of substrate units 412 in an array of dimensions - 1307951. Moreover, the scribe line 4 1 1 A between the first row & plate unit 4 1 1 is not aligned with the scribe line 4 1 2 A between the first row of substrate units 4 1 2 The __ _ non-substrate unit 411 and the second row of substrate units 412 are "non-two arrays". The upper surface of the substrate strip 410 is provided with at least one of the nozzles 4 1 3 , which are arranged on the same side as the first rows of the first row of substrate units 4 . In this embodiment, the first row of substrate units 4 1 1 virtual ^ and 5 Hai
些第二排基板單元412係為等尺寸之矩形、六角 八角形。之後，如第5B圖所示，設置複數個晶片々Μ 於該基板條4 1 0之上表面並位於對應之該些第— 一 徘基 板單元411與該些第二排基板單元412内。最後，士 第5C圖所示，形成複數個銲線421，其係電性連接1 些晶片4 2 0至該基板條4 1 0。再以轉移模製方式妒成 一封膠體（圖未繪出）於該基板條410之上表面，其係連 續且實質地覆蓋該些第一排基板單元411與該此 —弟. 排基板單元4 12，以密封該些晶片42〇。其中，由該、主 澆口 414提供封膠體之模流方向431係與該些第二— 基板早元4 1 1之排列方向概呈垂直。在本實施例中， 該封膠體在該些第一排基板單元4丨丨之間之切割首 411A之模流速度係被該些第二排基板單元412上^ = 片420阻擋而減緩，以遠 ’日日 、 運^流平衡。因此，能不需要链 外增加緩流障礙物元件的/欠Λ 早籾兀仟的條件下便可達到在晶片420之中止 與側邊模流平衡，在晶片42 、 、 42〇旁邊不會有MAP封襞氣泡。 、上所述4堇疋本發明的較佳實施例而已 12 1307951 本發明作任何形式上的限制，雖然本發明已以較值實 施例揭露如上，然而並非用以限定本發明，任何熟悉 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 第1圖：一種習知半導體封裳構造之截面示意圖。The second row of substrate units 412 are rectangular in shape and hexagonal octagon. Then, as shown in FIG. 5B, a plurality of wafers are disposed on the upper surface of the substrate strip 410 and located in the corresponding first substrate unit 411 and the second row substrate unit 412. Finally, as shown in Fig. 5C, a plurality of bonding wires 421 are formed which electrically connect the plurality of wafers 420 to the substrate strips 410. Then, a colloid (not shown) is formed on the upper surface of the substrate strip 410 by a transfer molding method, which continuously and substantially covers the first row of substrate units 411 and the tray substrate unit 4 12 to seal the wafers 42. Wherein, the mold flow direction 431 of the sealant provided by the main gate 414 is perpendicular to the arrangement direction of the second substrate early 4 1 1 . In this embodiment, the mold flow speed of the cutting head 411A between the first row of substrate units 4丨丨 is blocked by the second row of substrate units 412 and blocked by the sheet 420. 'Day and day, the flow balance. Therefore, it is possible to achieve the balance between the die and the side mold flow in the wafer 420 without the need to increase the retardation of the underflow barrier element/under the chain, and there is no next to the wafers 42 and 42 MAP seals the bubbles. The above description of the preferred embodiment of the present invention has been made to 12 1307951. The present invention is not limited to the above, but is not intended to limit the present invention. It is still within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications made by the skilled artisan without departing from the technical scope of the present invention. [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view of a conventional semiconductor sealing structure.
第2圖：繪示在習知模封陣列處理過程中一封膠艏在 陣列型態基板上流動迷度差異之示意圖。 第3圖：另—種習知半導體封裝構造之截面示意圖。 第4A至4F圖：依據本發明 ^ /£丨，在該 乃 < 第一具體實施例，私 半導體封裝構造之模封陣列處理過程中其基 板條載面示意圖。 第二具體實施例’另 列處理過程之截面示 意 第5A至5C圖·依據本發明之 種封裝晶片之模封陣 圖。 【主要元件符號說明】 100半導體封裝構造 11 〇基板單元 13 0封膠體 120 13 1 140銲終 150 晶片氣泡 外接端子 1 2 1 銲墊 1 3 2模流方向 200半導體封裝構造 220障礙物 23 1銲墊 210基板單元 230晶片 13 1307951 240 封膠體 250 銲線 310 基板條 311 第一排基板單元 3 11B切割道 3 12 第二排基板單元 313 上表面 314 下.表面 320 晶片 321 銲墊 330 封膠體 331 模流方向 410 基板條 411 第一排基板單元 412 第一排基板單元 413 注澆口 420 晶片 421 銲線 2 6 0外接端子 3 11Α切割道 3 12A切割道 3 15注澆口 322焊線 340外接端子 411A切割道 412A切割道 4 3 1模流方向Fig. 2 is a schematic view showing the difference in flow of a capsule on an array type substrate during the processing of a conventional mold-sealed array. Figure 3: A cross-sectional view of another conventional semiconductor package structure. 4A to 4F are schematic views of the substrate strips in the process of the package array process of the private semiconductor package structure in accordance with the present invention. Second Embodiment FIG. 5A to 5C is a cross-sectional view of a packaged wafer according to the present invention. [Main component symbol description] 100 semiconductor package structure 11 〇 substrate unit 13 0 sealant 120 13 1 140 solder terminal 150 wafer bubble external terminal 1 2 1 pad 1 3 2 mold flow direction 200 semiconductor package structure 220 obstacle 23 1 welding Pad 210 substrate unit 230 wafer 13 1307951 240 encapsulant 250 bonding wire 310 substrate strip 311 first row substrate unit 3 11B cutting lane 3 12 second row substrate unit 313 upper surface 314 lower surface 320 wafer 321 solder pad 330 sealing body 331 Mold flow direction 410 substrate strip 411 first row substrate unit 412 first row substrate unit 413 gate 420 wafer 421 bonding wire 2 60 external terminal 3 11 Α cutting lane 3 12A cutting lane 3 15 pouring gate 322 bonding wire 340 external connection Terminal 411A cutting path 412A cutting path 4 3 1 mold flow direction
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