TWI240395B - Encapsulating method on an array substrate by molding - Google Patents

Encapsulating method on an array substrate by molding Download PDF

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Publication number
TWI240395B
TWI240395B TW093137656A TW93137656A TWI240395B TW I240395 B TWI240395 B TW I240395B TW 093137656 A TW093137656 A TW 093137656A TW 93137656 A TW93137656 A TW 93137656A TW I240395 B TWI240395 B TW I240395B
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scope
obstacles
array
patent application
type substrate
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TW093137656A
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TW200620592A (en
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Chin-Hsien Lin
Mariano L Ching Jr
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An encapsulating method on an array substrate by molding is provided. Firstly, a chip carrier having multiple carrier units is provided. Next, a plurality of obstructions and a plurality of chips are formed on the upper surface of the chip carrier. The obstructions can be adjacent or disposed on the cutting streets of the chip carrier. When a molding compound is formed on the chip carrier to seal the chips, the obstructions can delay the flowing speed of the molding compound in filling state at specific location. Thus, the mold flow is balanced to avoid void inside the molding compound.

Description

12403951240395

_I240395 五、發明說明（2) ———-—一-—〜〜一 ，模封膠時，該晶片載體1Q係被固定於—模具内（圖未絡 以充填一封膠體40，請參閱第1圖，該封膠體40係〇由 2具之至少-注膠口 15導入並流動在該晶片載體1〇:; 表面11，以覆蓋該些載體單元13及密封該些晶片2〇。= ί4=ϊ曰體10上形成該封膠體40時，由夠 ，4〇之杈流被该些晶片2〇阻檔，導致該封膠體“在平行於 二k動方向之切割道14上之流動速率較快’當該些晶片2〇 或是為堆疊晶片型態時，該封膠體4〇在該晶片載體】〇 上表面Η流動速率的差異更為明顯，尤其是該封膠 4〇極容易在該些晶片20遠離該注膠口15之一遠離側邊23妒 成空隙41 (void)(請參閱第2圖），其係因該封膠體4〇之局ν 部流動速率過慢，導致該封膠體4〇包覆氣體所 影響封裝品質。 室 【發明内容】 本發明之主要目的係在提供一種陣列型態基板上封膠 方法及其構造，用以平衡一封膠體之模流流動速率，以解 決封膠空隙（m〇id v〇id)之問題，首先，提供一具有複數 ，載，單元之晶片載體，接著，在該晶片載體之一上表面 α又置複數個晶片及複數個障礙物（〇匕s f r u c f丨〇 n )，之後， 於Λ =片載體之違上表面上形成一封膠體，以密封該些晶 當該封膠體在充填狀態時，該些障礙物係能延緩該封 膠體之局部流動速率，以避免該封膠體包覆 膠空隙。 ^ ^_I240395 V. Description of the invention (2) ———-— One-— ~~ 1, the wafer carrier 1Q is fixed in the mold when molding the glue (the picture is not shown to fill a colloid 40, please refer to the section 1 figure, the sealant 40 is introduced from at least two glue injection ports 15 and flows on the wafer carrier 10: surface 11 to cover the carrier units 13 and seal the wafers 20. = ί4 = When the sealant 40 is formed on the body 10, it is enough that the flow of 40 is blocked by the wafers 20, resulting in the "flow rate of the sealant on the cutting path 14 parallel to the direction of two k motions" Faster. When the wafers 20 are in the form of stacked wafers, the difference in flow rate between the sealant 40 and the upper surface of the wafer carrier is more obvious, especially the sealant 40 is extremely easy to The wafers 20 are far away from one of the glue injection ports 15 and away from the side edges 23 (see FIG. 2). This is because the flow rate of the local ν part of the sealant 40 is too slow, which causes the Sealing gel 40. The quality of the package is affected by the encapsulation gas. [Summary of the Invention] The main purpose of the present invention is to provide an array-type substrate. The sealing method and its structure are used to balance the mold flow rate of a colloid to solve the problem of sealing gap (moid v〇id). First, a wafer carrier having a plurality of cells, cells and cells is provided. Next, a plurality of wafers and a plurality of obstacles (〇 匕 frucf 丨 〇n) are placed on the upper surface α of one of the wafer carriers, and then a colloid is formed on the upper surface of the wafer carrier to seal the When the sealant is in the filling state, the obstacles can delay the local flow rate of the sealant to prevent the sealant from covering the voids. ^ ^

第7頁 1240395 ----- 五、發明說明（3) 号务日月 方法，^ 人—目的在於提供一種陣列型態基板上封膠 障礙物係^ 1晶片載體係為鋸切型態封裝基板，複數個 片之間^ :有於—晶片載體之適當位置而與相鄰之該些晶 流動方向同向間隙，該些障礙物係可鄰近於與該封膠體 緩該封膠f右V之/軸切割道或是設置於Y軸切割道上，以延 全面性地臂案沐切割道上之流動速率，使得該封膠體能 壓模封膠1 有載體單兀，以達到無封膠空隙之大面積 方法，力二f 目的在於提供一種陣列型態基板上封膠 曰日片载體之該些障礙物係具有一障礙高产，j： 係介於該些晶片夕 < 要古危七、 I羊礙问度，具 —載體軍:η ，，6又问度 /刀之一到一倍之間，在每 最，由1此pi 5玄些晶片可為單一晶片黏設或多晶片堆 ς g由以二陣礙物以有效延緩該封膠體之局部流動速 率，以避免該封膠體包覆氣體而產生封膠空隙。 依本發明之陣列型態基板上封膠方法，首先， 曰曰片载體，該晶片載體係具有一上表面以及一 並 含有複數個載體單元，每一載體單元係定義有一晶接= 區。接著，設置複數個晶片於該些晶片 日日 ° ζ F# 41 ^(obstruction) ^ .. a , ^ 3 =置。^壓模方法•一封膠體形成於該晶片載體之 μ上表面，以岔封该些晶片，當該封膠體在充填狀觫 (f 1 u ing State)時，該些障礙物传能 、〜 部流動速率。 “b延緩該封膠體之局 1240395 五、铎明說明（4、 請參閱所附圖式，本發明將列舉以下之實施例說明： ^ v在本發明之第_一具體實施例中，如第3Α至3 D圖與第4 W Hr π，其係揭不--種陣列型態基板X封膠方法。讀參閱 第3Α與4圖’首先，提供載體u〇，該晶片載體ιι〇 ‘ 係具有一上表面1 η以及一下表面丨丨2，並且該晶片載體 110係包含有複數個載體單元113，用以製Page 7 1240395 ----- V. Description of the invention (3) Sun and Moon method, ^ person-the purpose is to provide an array type substrate sealing glue system ^ 1 chip carrier system is sawing type package Between the substrate and the plurality of pieces ^: there is a proper position of the wafer carrier with a gap in the same direction as the flow direction of the adjacent crystals, and the obstacles can be adjacent to the sealant to slow the sealant f right V The / axis cutting path is set on the Y-axis cutting path to extend the flow rate on the cutting path comprehensively, so that the sealing compound can be molded with a sealing unit 1 to achieve a sealless gap The large-area method, force two f aims to provide an array-type substrate that seals the Japanese wafer carrier. The obstacles have a high yield, and j: is between the wafers. I sheep interfering degree, with-carrier army: η ,, and 6 times the interrogation / knife between one and double, in each case, the chip can be a single chip or a multi-chip stack. ς g uses two obstacles to effectively delay the local flow rate of the sealing colloid to avoid the sealing colloid coating Generating voids encapsulant body. According to the sealing method for an array-type substrate according to the present invention, first, a wafer carrier, the wafer carrier has an upper surface and contains a plurality of carrier units, and each carrier unit defines a crystal junction area. Next, a plurality of wafers are set on these wafers. ° ζ F # 41 ^ (obstruction) ^ .. a, ^ 3 = set. ^ Compression molding method • A colloid is formed on the μ upper surface of the wafer carrier to seal the wafers. When the sealing colloid is in a filling state (f 1 u ing State), the obstacles transfer energy, ~部 流速。 Department of flow rate. "B Delay the situation of the sealing colloid 1240395 V. Duo Ming's description (4. Please refer to the attached drawings. The present invention will enumerate the following embodiments: ^ v In the first embodiment of the present invention, as in 3A to 3D pictures and the 4th W Hr π, which cannot be exposed-an array type substrate X sealing method. Please refer to Figs. 3A and 4 'First, a carrier u0 is provided, and the wafer carrier ιι〇' The wafer carrier 110 has an upper surface 1 η and a lower surface 丨 2, and the wafer carrier 110 includes a plurality of carrier units 113 for manufacturing.

封裝:該些載體單元1]3係為矩陣排列，每：：載體單元]13 係支義有-晶片接合區]14。該晶片載miQ在該也載體單 兀1 1 3之間係定義有相互垂直之複數個γ軸切割道丨丨5與複 數個X軸切剔迢1 1 6。在本實施例中，該、晶片載體〇係為 鋸切型態封裝之電路基板，該晶片載體丨u)内設有雙面電 性導通之鍍通孔與線路（圖未繪出）^Package: The carrier units 1] 3 are arranged in a matrix, each :: carrier unit] 13 are supported by-wafer bonding area] 14. The wafer-carried miQ defines a plurality of γ-axis cutting lines 5 and a plurality of X-axis cutting lines 1 1 6 that are perpendicular to each other between the carrier units 1 1 3. In this embodiment, the wafer carrier 0 is a circuit substrate in a saw-cut type package, and the wafer carrier is provided with plated through holes and wirings (not shown in the figure) that are electrically conductive on both sides.

請參閱第3B與4圖，將複數個障礙物U8 (〇bstructlon)設置於該晶片載體11〇之該上表面m，該 些障礙物118係不覆蓋至該些晶片接合區114。在本實施例 中，該些障礙物118係包含有銲罩材料（s〇lder masli material)，其形成方式係可先將一厚膜銲罩層（圖未繪 出），成於該晶片載體1丨〇之該上表面丨丨i，再圖案化該厚 膜銲罩層，以形成該些障礙物丨丨8。或者，該些障礙物1工8 係可為膠帶、虛晶片或樹脂。該些障礙物丨的形狀與設 置位置係可依封膠體之流動性及晶片之設置狀態作適當變 化’在本實施例中’該些障礙物丨丨8係為條狀且鄰近該些γ 轴切割道115 ’如第3B圖所示，該些障礙物118係設置於該 些Y軸切割道115之對應兩側邊。Referring to FIGS. 3B and 4, a plurality of obstacles U8 (Obstructlon) are disposed on the upper surface m of the wafer carrier 11. The obstacles 118 do not cover the wafer bonding areas 114. In this embodiment, the obstacles 118 include a solder masli material, and the formation method can be formed by first forming a thick film solder mask layer (not shown) on the wafer carrier. 1 丨 the upper surface 丨 丨 i, and then pattern the thick film solder mask layer to form the obstacles 丨 8. Alternatively, the obstacles may be tapes, virtual wafers, or resins. The shape and setting position of the obstacles can be appropriately changed according to the fluidity of the sealing colloid and the setting state of the wafer. In this embodiment, the obstacles are in a strip shape and are adjacent to the γ axis. Cutting lines 115 ′ As shown in FIG. 3B, the obstacles 118 are disposed on the two sides of the Y-axis cutting lines 115.

第9頁 1240395 五、發明說明（5) 之後，請參閱第3C與4圖，將複數個晶片丨2 〇設置於該 些aa 接合區1 1 4。母一晶片1 2 0係具有一主動面】2 1以及 一背面122，並包含形成於該主動面12】之複數個銲墊 1 2 3。複數個銲線1 3 0或其它電性導接元件，係連接該曰片 載體110與該些晶片120之該些銲墊丨21。在本實施例Λ中aa， 該些障礙物1 1 8係位於該些晶片1 20之間且與相鄰之該些晶 片1 2 0之間係留有一間隙為較佳。 、μ二BaPage 9 1240395 V. Description of the invention (5), please refer to Figures 3C and 4 and set a plurality of wafers 丨 2 0 in these aa junctions 1 1 4. The mother-wafer 1 2 0 has an active surface 2 1 and a back surface 122, and includes a plurality of pads 1 2 3 formed on the active surface 12 2. The plurality of bonding wires 130 or other electrical conductive elements are connected to the pad carrier 110 and the pads 21 of the wafers 120. In this embodiment Λ, it is preferable that the obstacles 1 18 are located between the wafers 120 and a gap is left between the wafers 120 and the adjacent wafers 120. ΜμBa

如第4圖所示，該些障礙物Π8係應不高於該些晶片 120之最上層主動面22，較佳地，該些障礙物118係具有一 障礙高度（a)，其係介於該些晶片12〇之設置高度（b)之四 分之一到一倍之間，以達到有效之膠體流動障礙效果。As shown in FIG. 4, the obstacles Π8 are not higher than the uppermost active surface 22 of the wafers 120. Preferably, the obstacles 118 have an obstacle height (a), which is between The setting height (b) of the wafers 120 is between one quarter and one time, so as to achieve an effective colloidal flow barrier effect.

w參閱第3 D與4圖，以壓模技術形成一封膠體1 & 〇於該 晶片載體110之該上表面111，該封膠體14〇係由該晶片載 體11 0之至少一注膠口 11 7導入，在本實施例中，該封膠體 14 0係覆蓋該些晶片1 2 〇與該些障礙物丨丨8。由於該封膠體 140在該Μ片載體11〇之該上表面hi之流動方向係與該些γ 軸切割道115為同向。當該封膠體14〇在充填狀態（fiUing state)時，該些鄰近於該些γ軸切割道115之該些障礙物 118係能延緩該封膠體丨4〇在該些γ軸切割道丨丨5上之流動速 率，使得該封膠體140之整體流動速率更加一致化，以解 決習知一次多載體單元封膠會發生空隙（v〇id)之問題。 在固化該封膠體1 4 0之後，係執行一鑛切步驟，其係 1著該些Y轴切割道11 5與該些X軸切割道1丨6切割斷穿該封 膠體1 4 0與該晶片載體11 〇，以形成複數個，以供積體電路w Referring to FIGS. 3D and 4, a colloid 1 is formed by a compression molding technique. The upper surface 111 of the wafer carrier 110 is formed by the at least one glue injection port of the wafer carrier 110. 11 7 is introduced. In this embodiment, the sealing compound 14 0 covers the wafers 120 and the obstacles 8. Because the flow direction of the sealant 140 on the upper surface hi of the M-chip carrier 11 is in the same direction as the γ-axis cutting tracks 115. When the sealant 14 is in a fiUing state, the obstacles 118 adjacent to the γ-axis cutting paths 115 can delay the sealant 丨 4 on the γ-axis cutting paths 丨 丨The flow rate above 5 makes the overall flow rate of the sealant 140 more uniform, so as to solve the problem that the conventional multi-carrier unit sealant will generate a void. After curing the sealing gel 1 4 0, a mining step is performed, which cuts through the sealing gel 1 4 0 and the 1 along the Y-axis cutting paths 115 and the X-axis cutting paths 1 丨 6. Wafer carrier 11 〇 to form a plurality of chips for integrated circuit

第10頁 1240395 五、發明說明（6) ^ 一— 之封裝產業上廣泛利用。 依據本發明之第二具體實施例， 複數個障礙物之晶片載體之上# 。又1為 士右一私视麟 月载骷之上表面不意圖，第δ圖係為形 成有一封膠脰之該晶片載體之截 片載體21〇係可選自於由一鋸二= 岣牟盥一北目上μ 鑛切型恶封裝之無外接腳式導 、在木”月貼片（back tape)構成之組合件、一 ;中：^是，…無外接腳式導線架或-金屬載板夕 ::::一 J本實施例中’該晶片載體210為由一鋸切型 =封衣=热外接腳式導線架211與一背貼片212構成之組合 —如弟5圖所不，該晶片載體2 i 〇係包含有複數個載體單 元2 1 3以及在。亥些載體單元2 1 3之間的γ軸切割道2丨5盥X軸 切割道216，每一載體單元213係定義有一晶片接合區 214，以供複數個晶片220之設置。在本實施例中該些晶 片2 20係以堆疊型態設置於每一晶片接合區214，最底層之 該晶片220係可黏設於該背貼片212或是一導線架之晶^承 座（die pad)(圖未繪出），並以複數個銲線23〇電性連接該 些晶片2 2 0與該晶片載體2 1 0之該導線架2 11。此外，複數 個障礙物218係設置於該晶片載體21〇，其係具有一適當之 障礙高度，用以延緩一封膠體240在充填狀態時，於該\曰曰 片載體210之特定部位之流動速率。該些障礙物218係可利 用印刷或點塗樹脂形成。在本實施例中，該些障礙物2 1 8 係設置於該些Y軸切割道215上，以延緩該封膠體24〇在充 填狀態時，於該晶片載體2 1 0之該些γ軸切割道2丨5上流動 速率。該封膠體2 4 0係以壓模形成在該晶片載體2 1 〇，以密Page 10 1240395 V. Description of the invention (6) ^ a — widely used in the packaging industry. According to a second embodiment of the present invention, a plurality of obstacles are on the wafer carrier #. Another 1 is that the right surface of Lin Yuezai's skull is not intended by Shi Youyi. The δ diagram is a slice carrier 21 of the wafer carrier formed with a seal. The system can be selected from one saw two = 岣 牟A combination of a non-external leg type guide and a wood-on-a-moon back tape on the μ-cut-type package on the North Project, one; middle: ^ Yes, ... no external leg type lead frame or -metal Carrier board :::: J In this embodiment, 'the wafer carrier 210 is a combination of a saw-cut type = coating = hot external leg type lead frame 211 and a back patch 212—as shown in FIG. 5 No, the wafer carrier 2 i 〇 includes a plurality of carrier units 2 1 3 and a γ-axis cutting path 2 丨 5 X-axis cutting path 216 between the carrier units 2 1 3, each carrier unit 213 A wafer bonding area 214 is defined for the arrangement of a plurality of wafers 220. In this embodiment, the wafers 20 and 20 are arranged in a stacked manner on each wafer bonding area 214, and the wafer 220 at the bottom layer can be adhered. A die pad (not shown) provided on the back patch 212 or a lead frame, and the plurality of bonding wires 230 are electrically connected to the die pads. 2 2 0 and the lead frame 2 11 of the wafer carrier 2 1 0. In addition, a plurality of obstacles 218 are disposed on the wafer carrier 21, which have an appropriate obstacle height for delaying a colloid 240 In the filling state, the flow rate at a specific part of the carrier 210. The obstacles 218 can be formed by printing or dot coating resin. In this embodiment, the obstacles 2 1 8 are disposed on the The Y-axis cutting lanes 215 are used to delay the flow rate of the sealing gels 24 on the γ-axis cutting lanes 2 and 5 of the wafer carrier 2 10 in the filling state. The sealing gels 2 4 0 are based on A stamper is formed on the wafer carrier 2 1 〇 to densely

第】1頁 1240395 五、發明說明（γ) ~—— 封該些晶片2 2 0。該封膠體2 4 〇係 一 入，並且該封膠體240在該晶片㈣210上流動方該 些Υ軸切割迢21 5壬同一方向。藉由該些障礙物2丨8設置於 0些Υ軸切刎道2 1 5上，以使得在該些¥軸切割道2丨5上之該 封膠體240不會有過快之封膠體流動速率，以避免產生封 膠空隙（mo 1 d vo i d )之問題。Page] 1 1240395 V. Description of the invention (γ) ~ —— Seal these wafers 2 2 0. The sealing compound 24 is integrated, and the sealing compound 240 flows on the wafer ㈣210 to cut the Υ21 壬 in the same direction. The obstacles 2 and 8 are arranged on the zero-axis cutting channels 2 1 5 so that the sealing gel 240 on the ¥ -axis cutting channels 2 and 5 will not have excessively fast sealing gel flow. Rate to avoid the problem of sealing gap (mo 1 d vo id).

本發明係不局限在晶片載體上障礙物之形狀，如第7 圖所示，其係為本發明之第三具體實施例，一晶片載體 310係包含有複數個載體單元311、在該些載體單元3ΐι之 間的複數個Y轴切割道31 3與複數個X轴切割道31 4，該些γ ，切割道313係與一封膠體之流動方向為同向。每一載一體 單元311係定義有一晶片接合區3 12，以供設置晶片。複數 個障礙物315係設置於該晶片載體31〇，其係可為塊狀，用 以延緩一壓模形成之封膠體在特定部位之流動速率。在本 實施例中，該些障礙物315係可為半圓形或具有一收斂之 尾知，以平衡封膠體之流動速率，避免產生封膜空隙。 …本發明之陣列型態基板上封膠方法可以適用在各式的 半導體封裝產品，例如球格陣列封裝構造（BGA package)、平面陣列封裝構造（LGA叩以叫6)、四方扁平 無外接腳封裝構造（Quad nat N〇n—leaded package，QFN package)、小尺寸外觀無外接腳封裝構造（SmaU 〇utiine Non-leaded package，S0N package)、凸塊晶片載體封裝 構造（Bump Chip Carrier package，Bcc package)或其它 無外接腳封裝構造（leadless package)，在本發明之第四The present invention is not limited to the shape of obstacles on the wafer carrier. As shown in FIG. 7, it is a third specific embodiment of the present invention. A wafer carrier 310 includes a plurality of carrier units 311. The plurality of Y-axis cutting lines 31 3 and the plurality of X-axis cutting lines 31 4 between the units 3ΐι are γ, and the cutting lines 313 are in the same direction as the flow direction of a colloid. Each integrated loading unit 311 defines a wafer bonding area 3 12 for mounting a wafer. A plurality of obstacles 315 are disposed on the wafer carrier 31, and they can be block-shaped to delay the flow rate of the sealing colloid formed by a stamper at a specific location. In this embodiment, the obstacles 315 may be semi-circular or have a convergent tail to balance the flow rate of the sealing colloid and avoid the formation of sealing voids. … The sealing method on the array type substrate of the present invention can be applied to various types of semiconductor packaging products, such as a ball grid array package structure (BGA package), a flat array package structure (referred to as LGA 6), a square flat without external pins Package structure (Quad nat Non-leaded package (QFN package)), small size appearance without external pin package structure (SmaU 〇utiine Non-leaded package (S0N package)), bump chip carrier package structure (Bump Chip Carrier package, Bcc package) or other leadless package structure, in the fourth aspect of the present invention

第12頁 1240395 五、發明說明（8) 方法運用 具體實施例中例舉本發明之陣列型態基板上封膠 在製造凸塊晶片載體封裝構造之過程。 / 首先，請參閱第8A圖，提供一晶片載體41〇，該晶尸 載體41 0係為可被蝕除金屬載板，例如銅或銅合Λ =Page 12 1240395 V. Description of the invention (8) Method application In the specific embodiment, the process of encapsulating the array type substrate of the present invention in the manufacture of a bump wafer carrier package structure is exemplified. / First, please refer to FIG. 8A, a wafer carrier 41o is provided, and the corpse carrier 410 is an etchable metal carrier board, such as copper or copper alloy Λ =

片載體410係具有一上表面411並包含有複數個载體單"元 413，，該些載體單元413之間係定義有複數個切割道 4 1 3，每一載體單元4 1 3係可以半蝕刻方法形成有一凹陷於 該上表面41 1之晶片接合區4Η以及複數個接點凹陷〇/，、 在該些晶片接合區4 1 4與該些接點凹陷4 1 5内部係形成有至 少一電鍍層416，例如鎳-鈀—金等與該晶片载體41〇材質= 同之金屬。 、The chip carrier 410 has an upper surface 411 and includes a plurality of carrier elements 413. A plurality of cutting lines 4 1 3 are defined between the carrier units 413. Each carrier unit 4 1 3 can A half-etching method is formed with a wafer bonding region 4Η recessed on the upper surface 41 1 and a plurality of contact recesses. At least, the wafer bonding regions 4 1 4 and the contact recesses 4 1 5 are internally formed with at least A plating layer 416, such as nickel-palladium-gold, is the same material as the wafer carrier 410. ,

之後’進行黏晶步驟及障礙物之設置步驟，在本實施 例中’係先進行黏晶步驟再設置障礙物。請參閱第8 Β圖， 將複數個晶片420之背面422設置於該些晶片接合區414， 而該些晶片4 2 0之主動面4 2 1係朝向上方，再利用打線技術 形成複數個銲線430，以連接該些晶片42〇與在該些接點凹 陷415内之電鍍層4 16。此外，該些晶片420除了可以打線 電性連接，亦可以是覆晶接合或其它電連接方式設置於該 晶片載體4 1 0上（圖未繪出）。接著，請參閱第§ c圖，可利 用膠體點塗或膠體印刷方式將複數個障礙物440 (obstruct ion)設置於該晶片載體41 〇之該上表面41 1，該 些障礙物440係可位在該些切割道4 1 3上或是鄰近該些切割 道41 3之側邊，而可不接觸至該些晶片4 2 0，該些障礙物 4 4 0應以不高於相鄰該些晶片4 2 0之主動面4 2 1為較佳。之After that, the step of sticking crystals and the step of setting obstacles are performed. In this embodiment, the step of sticking crystals is performed before the obstacles are set. Referring to FIG. 8B, the back surfaces 422 of the plurality of wafers 420 are disposed on the wafer bonding areas 414, and the active surfaces 4 2 1 of the wafers 4 2 0 are directed upward, and then a plurality of bonding wires are formed by using a wire bonding technology. 430 to connect the wafers 42 to the plating layers 4 16 in the contact recesses 415. In addition, the chips 420 can be wired and electrically connected, and can also be provided on the chip carrier 4 10 by flip-chip bonding or other electrical connection methods (not shown). Next, referring to Figure § c, a plurality of obstacles 440 (obstruct ion) can be set on the upper surface 41 1 of the wafer carrier 41 by colloidal spot coating or colloidal printing. The obstacles 440 are positionable. On the cutting lines 4 1 3 or adjacent to the sides of the cutting lines 41 3 without touching the wafers 4 2 0, the obstacles 4 4 0 should not be higher than the adjacent wafers An active surface of 4 2 0 4 2 1 is preferred. Of

1240395 五、發明說明（9) ” -- $ ’凊參閱第8D圖，以壓模形成一封膠體4 5 〇於該晶片載 體4ίο之該上表面4n，該封膠體45〇係覆蓋至該些載體單 兀4 12與該些切割道413，當該封膠體450在充填狀態時， 該些障礙物440係能延緩該封膠體45()在特定切叫道^13夕 動速率，使得模流速度趨向一致化，防止‘該些' 片420側面產生空隙（v〇id)。 410移之：，請/閱細圖，可利用蝕刻方法將該晶片載體 =〇移除，以顯露出該些電鑛層416。接著，請參閱第8ρ 势’在该封膠體45 0上黏設一切割膠帶46〇。之 第8G圖，執行一鋸切步驟，以沿 >閱 載體封裝構造。 …工隙之凸塊日日片 本發明之保護範圍當視後附由& * 為準，任何熟知此項技藝者 圍内所作之任何變化與修改，均屬 毛明之精神和範 3屬於本發明之保護範圍。1240395 V. Description of the invention (9) ''-$ '凊 Refer to FIG. 8D, a piece of colloid 4 5 is formed on the top surface 4n of the wafer carrier 4 by compression molding, and the sealing colloid 45 is covered to these The carrier unit 4 12 and the cutting paths 413. When the sealing gel 450 is in the filling state, the obstacles 440 can delay the moving speed of the sealing gel 45 () at a specific cutting path ^ 13, so that the mold flow The speed tends to be uniform to prevent voids (v〇id) from forming on the sides of the 420 wafers. 410 Move it :, please / read the detailed picture, the wafer carrier can be removed by etching method to reveal these wafers The electric ore layer 416. Next, please refer to the "8ρ potential" on which a sealing tape 46o is stuck on the sealing gel 45 0. Figure 8G, a sawing step is performed to read the carrier packaging structure along the>. The scope of the invention of the gap of the bulge is protected by the & * attached. Any changes and modifications made by those skilled in the art are within the spirit of Mao Ming and the scope of the invention belongs to the protection of the present invention. range.

第14頁 1240395 圖式簡單說明 【圖式簡單說明】第 1 j 圖··在習知陣列蜇態基板上封膠過程中，一用以 =不封膠體充填狀態之晶片載體之上表面示意圖； 2圖：在習知陣列蜇態基板上封膠過程中，該晶片 A -隹形成有封膠體之截面不意圖； 第3 A至3D圖：依據本發明之第一具體實施例 在陣列型態基板上封膠過輕之上表面示意圖 第 4 圖：依據本發明之第一具體實施例 在形成有封膠體時之截面示意圖； 第 5 圖：依據本發明之第二具體實施例 礙物之晶片載體之上表面示意圖； 第6 圖··依據本發明之第二具體實施例 在形成有封膠體時之截面示意圖； 第 7 圖··依據本發明之第三具體實施例 礙物之晶片載體之上表面示意圖；及 第8A至8G圖：依據本發明之第四具體實施例 在陣列型態基板上封膠過程之截面示意圖。 晶片載體 該晶片載體 设置有障 該晶片載體 設置有障 一 日 晶片載體 元件符號簡單說明： 1〇 晶片載體 12 下表面 13 載體單元 2〇 晶片 2 3 遠離側邊 11 上表面 12a連接墊 14 切割道 21 銲墊 11 a導接指 15 注膠口 22 主動面1240395 on page 14 Brief description of the drawings [Simplified description of the drawings] Figure 1 j · A schematic diagram of the upper surface of a wafer carrier in the state of sealing in the conventional array substrate during the sealing process; Figure 2: In the process of sealing on a conventional array substrate, the wafer A- 隹 is not intended to have a cross-section of the sealing compound; Figures 3A to 3D: According to a first embodiment of the present invention in an array type Schematic diagram of the upper surface of the substrate on which the sealant is too light. Figure 4: A cross-sectional view of the first embodiment of the present invention when a sealant is formed. Figure 5: A wafer according to the second embodiment of the present invention Schematic diagram of the upper surface of the carrier; Fig. 6 ························································································································ Top surface schematic diagrams; and FIGS. 8A to 8G: cross-sectional schematic diagrams of a sealing process on an array type substrate according to a fourth embodiment of the present invention. Wafer carrier The wafer carrier is provided with a barrier. The wafer carrier is provided with a barrier. The wafer carrier element symbol is simply explained: 10 wafer carrier 12 lower surface 13 carrier unit 20 wafer 2 3 away from the side 11 upper surface 12a connecting pad 14 cutting path 21 Welding pad 11 a Guide finger 15 Glue injection port 22 Active surface

第15頁 1240395 圖式簡事說明 30 銲線 I 1 0 晶片載體 II 3 載體單元 1 1 5 Y軸切割道 1 1 7 注膠口 1 2 0 晶片1 2 3 銲墊 2 1 0晶片載體 213載體單元21 5 Y軸切割道 2 1 7 注膠口 220晶片3 1 0 晶片載體 3 1 2 晶片接合區 3 1 3 Y軸切割道 41 0晶片載體4 1 3 切割道 416 電鍍層 422 背面 4 4 0 障礙物 a 障礙高度 40 封膠體 111 上表面 114 晶片接合區 116 X轴切割道 118 障礙物 121 主動面 130 銲線 211 導線架 214 晶片接合區 216 X軸切割道 218 障礙物 230 銲線 311 載體單元 314 X軸切割道 411 上表面 414 晶片接合區 41 空隙 1 1 2 下表面 1 2 2 背面 1 4 0 封膠體 2 1 2 背貼片 240 封膠體 3 1 5 障礙物 412載體單元 4 1 5 接點凹陷 421 主動面 4 2 0 晶片 430 銲線 4 5 0 封膠體 4 6 0 切割膠帶 b 晶片設置高度1240395 on page 15 Brief description of drawings 30 Welding wire I 1 0 Wafer carrier II 3 Carrier unit 1 1 5 Y-axis cutting line 1 1 7 Filling port 1 2 0 Wafer 1 2 3 Pad 2 1 0 Wafer carrier 213 Carrier Unit 21 5 Y-axis cutting line 2 1 7 Filling port 220 wafer 3 1 0 Wafer carrier 3 1 2 Wafer bonding area 3 1 3 Y-axis cutting line 41 0 Wafer carrier 4 1 3 Cutting line 416 Plating layer 422 Back side 4 4 0 Obstacle a Obstacle height 40 Sealant 111 Upper surface 114 Wafer bonding area 116 X-axis cutting path 118 Obstacle 121 Active surface 130 Bonding wire 211 Lead frame 214 Wafer bonding area 216 X-axis cutting path 218 Obstacle 230 Welding line 311 Carrier unit 314 X-axis cutting path 411 Upper surface 414 Wafer bonding area 41 Gap 1 1 2 Lower surface 1 2 2 Back surface 1 4 0 Sealant 2 1 2 Back patch 240 Sealant 3 1 5 Obstacle 412 Carrier unit 4 1 5 Contact Depression 421 Active surface 4 2 0 Wafer 430 Welding wire 4 5 0 Sealant 4 6 0 Cutting tape b Wafer setting height

第16頁Page 16

Claims (1)

1240395 六、申請專利範圍 一一一……一―丨 【申請專利範圍】 1、一種陣列型態基板上封膠方法，包含： 提供一晶片載體，該晶片載體係具有一上表面以及一 下表面並包含有複數個載體單元，每一載體單元係养 一晶片接合區； - 尜置複數個障礙物（〇bs true t i on )於該晶片載體之該 上表面； &置複數個晶片於該些晶片接合區；及 ^ 壓模形成一封膠體於該晶片載體之該上表面，當該封 .體在充填狀態時，該些障礙物係能延緩該封膠體之 流動速率。 、2、如申請專利範圍第丨項所述之陣列型態基板上封膠方 法，其中該晶片載體係為鋸切型態（sawing type)封裝之 電路基板，其係具有複數個在該些封裝單元之間的切割 ^ ° ° 3、 如申請專利範圍第2項所述之陣列型態基板上封膠方 法，其中該些障礙物係包含有銲罩材料（solder mask material)。 4、 如申請專利範圍第丨項所述之陣列型態基板上封膠方 法，其中該些障礙物係設置於該些晶片之間且與相鄰之該斯 些晶片之間係留有一間隙。 5如申叫專利範圍第1項所述之陣列型態基板上封膠方 法其中在6亥複數個障礙物之設置步驟中係包含： 形成一厚膜銲罩層於該晶片載體之上表面；及1240395 VI. Scope of applying for patents one by one ...... 丨 【Scope of applying for patents】 1. A sealing method for an array type substrate includes: providing a wafer carrier having an upper surface and a lower surface and Contains a plurality of carrier units, each of which supports a wafer bonding area;-placing a plurality of obstacles (0bs true ti on) on the upper surface of the wafer carrier; & placing a plurality of wafers on the wafer carriers Wafer bonding area; and ^ forming a colloid on the upper surface of the wafer carrier by compression molding, when the seal body is in the filling state, the obstacles can delay the flow rate of the seal colloid. 2. The sealing method for an array type substrate as described in item 丨 of the patent application scope, wherein the wafer carrier is a circuit substrate of a sawing type package, which has a plurality of packages in the packages. Cutting between units ^ ° ° 3. The sealing method for an array type substrate as described in item 2 of the patent application scope, wherein the obstacles include a solder mask material. 4. The sealing method for an array type substrate as described in item 丨 of the patent application scope, wherein the obstacles are arranged between the wafers and a gap is left between the wafers and the adjacent wafers. 5. The method for sealing an array substrate according to item 1 of the claimed patent scope, wherein the step of setting a plurality of obstacles comprises: forming a thick film solder mask layer on the upper surface of the wafer carrier; and 形成該些障礙物。 述之陣列型態基板上封膠方 該些晶片之最上層主動面。 述之陣列型態基板上封膠方 障礙高度，其係介於該些晶 倍之間。 述之陣列型態基板上封膠方 晶片與該些障礙物。 述之陣列型態基板上封膠方 係定義有複數個Υ軸切割道 割道係垂直於該些X軸切割 係為同向。 述之陣列型態基板上封膠方 些Υ軸切割道。 述之陣列型態基板上封膠方 該些Υ軸切割道上。 述之陣列型態基板上封膠方 或塊狀。 述之陣列型態基板上封膠方 由一導線架與一背貼片構成 陶瓷電路板、一導線架、一 述之陣列型態基板上封膠方 疊設有複數個晶片。 法 法 1240395 、申請專利範圍 0案化该厚膜鲜罩層，以 6、如申印專利範圍第1 項所 其中該些障礙物係不高於 如申請專利範圍第1項所 其中該些障礙物係具有一 片之設置高度之四分之一到一 8、 如申請專利範圍第1項所 法’其中該封膠體係覆蓋該些 9、 如申請專利範圍第1項所 法，其中在該些載體單元之間 與X軸切割道，其中該些γ軸切 道並且與該封膠體之流動方向 10、 如申請專利範圍第8項所 法，其中該些障礙物係鄰 11、 如申請專利範圍第8 Ϊ所 法’其中該些障礙物係設置於 12、 如申請專利範圍第1項所 法，其中該些障礙物係為條狀 13如申凊專利範圍第1項所 法，其中該晶片載體係選自於 之組合件、一印刷電路板、一 金屬載板之其中之一。 14、如申請專利範圍第1項所 法，其中每一晶片接合區上係 第18頁 1240395 … a 1 — II . "u嗔·Ι"_·· ..................................... 叫^ _·|··|· 六、申請專刊範圍 2 1、如申請專利範圍第2 0項所述之陣列型態基板上封膊 構造，其中該些障礙物係包含有銲罩材料（s〇丨der mask in a i e r i a 1 ) 〇 22、 如申請專利範圍第]9項所述之陣列型態基板上封勝 構造，其中該些障礙物係設置於該些晶片之間且與相鄰之 該些晶片係留有一間隙。 23、 如申請專利範圍第丨9項所述之陣列型態基板上封膠 構造，其中該些障礙物係不高於該些晶片之最上層主動 面0These obstacles are formed. The array-type substrate described above is sealed with the top active surface of the wafers. The height of the sealing barrier on the array substrate described above is between the multiples. The array-type substrate is encapsulated with a square chip and the obstacles. The sealing pattern on the array-type substrate described above defines a plurality of Z-axis cutting lines. The cutting lines are perpendicular to the X-axis cutting systems in the same direction. The array type substrate described above is sealed with some Z-axis cutting tracks. The sealant on the array-type substrate is described on the sacral scribe lines. The array type substrate is encapsulated in a square or block shape. The above-mentioned sealing substrate on the array type substrate is composed of a lead frame and a back patch. The ceramic circuit board, a lead frame, and the above-mentioned sealing substrate on the array type substrate are stacked with a plurality of wafers. Law 1240395, the scope of patent application 0 case of this thick film fresh cover, according to 6, as in the application of the scope of patent application, these obstacles are not higher than those in the scope of patent application, the first obstacle The material has a quarter of the height of one to eight, as in the method of the first scope of the patent application, where the sealant system covers the nine, as in the method of the first scope of the patent application, in which The cutting path between the carrier unit and the X-axis, where the γ-axis cuts and the flow direction of the sealing colloid 10, as described in item 8 of the patent application range, wherein the obstacles are adjacent 11, as in the patent application range The 8th law of the law 'where these obstacles are set at 12, such as the law of the scope of patent application No. 1 law, where these obstacles are stripe 13 as the law of the scope of the patent application No. 1 law, where the chip The carrier is one selected from the group consisting of a printed circuit board and a metal carrier board. 14. As described in item 1 of the scope of patent application, where each wafer bonding area is on page 18 1240395… a 1 — II. &Quot; u 嗔 · Ι " _ ·· ............... ................. Called ^ _ · | ·· || 6. Scope of application for special publications 2 1. Scope of application for patents 2 The sealing structure on the array substrate described in item 0, wherein the obstacles include a solder mask material (soeder mask in aieria 1). 22. The array as described in item 9 of the patent application scope. The sealed structure on the type substrate, wherein the obstacles are arranged between the wafers and a gap is left between the adjacent wafers. 23. The sealant structure on the array type substrate as described in item 9 of the patent application scope, wherein the obstacles are not higher than the topmost active surface of the wafers. 24、如申請專利範圍第丨9項所述之陣列型態基板上封膠 f造’其中該些障礙物係具有一障礙高度，其係介於該些 日日片之δ又置南度之四分之一到一倍之間。 25、如 構造， 2 6、如 構造， 切割道 與該封 27〜如 構造， 2 8、如 構造， 2 9、如 構造， 甲請專 其中該 申請專 其中在 ，其中 膠體之 申請專 其中該 申請專 其中該 申請專 其中該 利範圍第1 9項所述之陣列型態基板上封膠 封膠體係覆蓋該些晶片與該些障礙物。 利範圍第1 9項所述之陣列型態基板上封膠 a玄些載體單元之間係定義有複數個γ軸與X -该些Υ軸切割道係垂直於該些X軸切割道並」 流動方向係為同向。24. The sealant f on the array type substrate described in item 9 of the scope of the patent application, wherein the obstacles have an obstacle height, which is between δ and south of the daily films. Between a quarter and a double. 25. Such as structure, 2 6. Such as structure, cutting path and the seal 27 ~ such as structure, 2 8. such as structure, 2 9. such as structure, A please apply for the application, and apply for the colloid. The encapsulation system for the array substrate described in item 19 of the application scope covers the wafers and the obstacles. A plurality of gamma axes and X are defined between the sealant a and the carrier units on the array type substrate described in Item 19 of the scope of interest. The y-axis cutting lines are perpendicular to the X-axis cutting lines and are combined. " The direction of flow is the same. 利Iil圍第2 6項所述之陣列型態基板上封膠 些卩早礙物係鄰近該些Y軸切割道。 利圍第2 6項所述之陣列型態基板上封膠 些障礙物係設置於該些γ軸切割道上。 利圍第1 9項所述之陣列型態基板上封膠 些障礙物係為條狀或塊狀。Seal the glue on the array-type substrate described in item 26 of Iil Wai. Some premature obstructions are adjacent to the Y-axis cutting lanes. The barriers are sealed on the array-type substrate described in item 26 of Liwei. Some obstacles are set on the γ-axis cutting lanes. The barriers on the array-type substrate described in item 19 of Liwei are strips or blocks. 1240395 -------η»™....................—-------—----------------------«—»‘一 +—表 六、申請專利範圍 | λ 3 0、如申請專利範圍第1 9項所述之陣列型態基板上封膠構 | I 造，其中該晶片載體係選自於由一導線架與一背貼片構成 之組合件、一印刷電路板、一陶瓷電路板、一導線架、一 金屬載板之其中之一。 3 1、如申請專利範圍第1 9項所述之陣列型態基板上封膠構. 造，其中每一晶片接合區上係疊設有複數個晶片。 3 2、如申請專利範圍第1 9項所述之陣列型態基板上封膠構 造，另包含有複數個導線，以電性連接該些晶片至該晶片 載體。1240395 ------- η »™ ..............--------------------- ------------ «—» '一 + —Table VI. Patent application scope | λ 30, as described in item 19 of the patent application scope, encapsulation on the substrate of the array type | The wafer carrier is selected from the group consisting of a lead frame and a back patch, a printed circuit board, a ceramic circuit board, a lead frame, and a metal carrier board. 3 1. The array-type substrate is sealed with an adhesive structure as described in item 19 of the scope of patent application, wherein each wafer bonding area is provided with a plurality of wafers stacked thereon. 3 2. The encapsulation structure on the array type substrate as described in item 19 of the scope of patent application, further comprising a plurality of wires for electrically connecting the chips to the chip carrier. 第21頁Page 21
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US7691676B1 (en) 2008-11-14 2010-04-06 Powertech Technology Inc. Mold array process for semiconductor packages

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KR20150101040A (en) * 2014-02-25 2015-09-03 에스케이하이닉스 주식회사 Package substrate, and package and method of fabricating the package using the package substrate
US10068822B2 (en) 2016-09-30 2018-09-04 Nanya Technology Corporation Semiconductor package and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7691676B1 (en) 2008-11-14 2010-04-06 Powertech Technology Inc. Mold array process for semiconductor packages

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