JP2008053612A - Semiconductor package - Google Patents

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JP2008053612A
JP2008053612A JP2006230533A JP2006230533A JP2008053612A JP 2008053612 A JP2008053612 A JP 2008053612A JP 2006230533 A JP2006230533 A JP 2006230533A JP 2006230533 A JP2006230533 A JP 2006230533A JP 2008053612 A JP2008053612 A JP 2008053612A
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chip
chip carrier
semiconductor package
map
mold flow
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Wen-Jeng Fan
文正 范
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Powertech Technology Inc
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MAP semiconductor package in which MAP packaging air bubbles are not generated. <P>SOLUTION: The semiconductor package comprises a chip carrier 210, at least one chip 220, and a seal 230. The chip carrier 210 has an upper surface 211, a lower surface 212, and a plurality of partitioning edges 213 between the upper surface 211 and the lower surface 212. The chip 220 is arranged on the chip carrier 210 and connected electrically therewith. The seal 230 seals the chip 220 hermetically while covering the upper surface 211 of the chip carrier 210, and mold fluidity limiting portions 231 are formed on the opposite sides of the seal 230. The mold fluidity limiting portions 231 are lower than the central top surface 233 of the seal 230 and aligned with the partitioning edges 213 of the corresponding chip carrier 210. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体パッケージに関し、特にＭＡＰ型半導体パッケージおよびそれの製造方法に関する。   The present invention relates to a semiconductor package, and more particularly to a MAP type semiconductor package and a manufacturing method thereof.

半導体実装の分野において、ＭＡＰ（Mold Array Process）技術を利用して封止体の製造コストを大幅に低減すること及び実装効率を向上させることができる。基板内には一体化された複数個のチップキャリアを有し、半導体チップをチップキャリア上に貼着した後、モルド技術を用いて封止体で基板の大部分表面を覆い、また、チップキャリアの縁部に沿って封止体と基板とを分割すれば立方体形のＭＡＰ半導体パッケージを得ることができる。   In the field of semiconductor mounting, the manufacturing cost of the sealing body can be greatly reduced and the mounting efficiency can be improved by using MAP (Mold Array Process) technology. The substrate has a plurality of integrated chip carriers, and after the semiconductor chip is adhered onto the chip carrier, the majority of the surface of the substrate is covered with a sealing body using a mold technique. A MAP semiconductor package having a cubic shape can be obtained by dividing the sealing body and the substrate along the edge.

図１に示すように、周知のＭＡＰ型半導体パッケージ構造１００は、チップキャリア１１０、チップ１２０、及び封止体１３０を有し、伝統的な単一個モルド（Single-Mold）で出来る半導体パッケージ構造との最大差別は、封止体１３０が周囲に分割面を有したり、チップキャリア１１０の分割縁部と縦方向に一致したりすることである。チップキャリア１１０上にチップ１２０が設置され、ワイヤボンディング方式で形成される複数個のボンディングワイヤ１４０で電気的にチップ１２０のボンディングパッド１２１とチップキャリア１１０とを接続する。モルド方式でチップキャリア１１０上に封止体１３０が形成され、チップキャリア１１０の下方に複数個の外接端子１５０（例えば半田ボールを使う）を設置することができる。封止体１３０はチップキャリア１１０と縦方向に一致する分割面を有する。しかしながら、ＭＡＰの製造過程には、チップ１２０の側辺に実装気泡１３１を形成し易くなる。図２に示すように、ＭＡＰの製造過程において、複数個のチップキャリア１１０はアレイに配置され且つ一体化されて連結されて基板になり、また、加熱硬化される前の封止体１３０を使ってモルド方式でモルド方向１３２に従ってそれらのチップキャリア１１０の大部分面積を覆う。それらのチップは加熱硬化前封止体のモルドフロウ（mold flow）を塞ぐため、加熱硬化前封止体においてチップキャリア中央（チップを持つ所）のモルドフロウ速度はそれらのチップキャリア両側のモルドフロウ速度より遅くなり、しかも、チップは後ろに並べば並ぶほど、それらのチップキャリア中央のモルドフロウ速度とそれらのチップキャリア両側のモルドフロウ速度との差は大きくなる。ゆえに、チップ両側の空気は排出し難くＭＡＰ実装気泡の現象が起きて１つの問題となる。   As shown in FIG. 1, a well-known MAP type semiconductor package structure 100 includes a chip carrier 110, a chip 120, and a sealing body 130, and a semiconductor package structure made of a traditional single-mold. The maximum discrimination is that the sealing body 130 has a dividing surface around it or coincides with the dividing edge of the chip carrier 110 in the vertical direction. The chip 120 is installed on the chip carrier 110, and the bonding pads 121 of the chip 120 and the chip carrier 110 are electrically connected by a plurality of bonding wires 140 formed by a wire bonding method. A sealing body 130 is formed on the chip carrier 110 by a mold method, and a plurality of external terminals 150 (for example, using solder balls) can be installed below the chip carrier 110. The sealing body 130 has a split surface that coincides with the chip carrier 110 in the vertical direction. However, in the manufacturing process of the MAP, the mounting bubbles 131 are easily formed on the side of the chip 120. As shown in FIG. 2, in the manufacturing process of MAP, a plurality of chip carriers 110 are arranged in an array and connected together to form a substrate, and a sealing body 130 before being heated and cured is used. Then, most of the chip carriers 110 are covered according to the mold direction 132 in the mold method. Since these chips block the mold flow of the sealing body before heat curing, the mold flow speed at the center of the chip carrier (where the chip is located) in the sealing body before heat curing is slower than the mold flow speed on both sides of the chip carrier. In addition, the difference between the mold flow speed at the center of the chip carrier and the mold flow speed on both sides of the chip carrier increases as the chips are arranged rearward. Therefore, the air on both sides of the chip is difficult to be discharged, and the MAP mounting bubble phenomenon occurs, which becomes one problem.

特許文献１の「アレイ型基板上の封止方法」にＭＡＰ実装気泡を解決する半導体実装技術が提出されている。ＭＡＰの製造過程中において、各チップキャリアの上表面の中央と両側のモルドフロウ速度を対等にするように両側のモルドフロウ速度を低下させるため、両側に障碍物が設置されてＭＡＰ実装気泡という問題を解決する。しかし、問題の解決と伴に障碍物の使用は製造過程ステップが増加し、製造コストも上がることになる。他に厚膜の半田マスク層（Solder Mask Layer）をも１つの解決方法として採用され、厚さはあまり足りなくてモルドフロウ速度を低くさせる効果が著しくならない。   A semiconductor mounting technique that solves MAP mounting bubbles is submitted to “Sealing Method on Array Type Substrate” in Patent Document 1. During the MAP manufacturing process, the mold flow speeds on both sides are lowered so that the mold flow speeds on both sides of the chip carrier are equal to each other, so obstacles are installed on both sides to solve the problem of MAP mounting bubbles. To do. However, as the problem is solved, the use of obstacles increases manufacturing process steps and increases manufacturing costs. In addition, a thick solder mask layer is also adopted as one solution, and the thickness is not sufficient so that the effect of reducing the mold flow rate is not significant.

中華民国特許第Ｉ２４０，３９５号Chinese Patent No. I240,395

前記の問題を解決するため、本発明の主な目的はＭＡＰ型半導体パッケージ構造およびそれの製造方法を提供する。前記障碍物を使用しなくても加熱硬化前封止体はチップキャリア両側に流れる速度を遅らせてチップキャリアの中央と両側のモルドフロウ速度のバランスを取ることができ、チップキャリア両側にＭＡＰ実装気泡が発生しなくなる。このように封止体形状を変化させるだけで従来の障碍物使用技術による効果を実現することができる。   In order to solve the above problems, a main object of the present invention is to provide a MAP type semiconductor package structure and a method of manufacturing the same. Even if the obstacle is not used, the encapsulated body before heat curing can balance the mold flow speed of the center and both sides of the chip carrier by delaying the flow speed on both sides of the chip carrier, and MAP mounting bubbles are formed on both sides of the chip carrier. No longer occurs. Thus, the effect by the conventional obstacle use technique is realizable only by changing a sealing body shape.

先ず、本発明によるＭＡＰ型半導体パッケージ構造は、チップキャリア、少なくとも一つのチップ、及び封止体を備える。チップキャリアは上表面、下表面、及び上表面と下表面との間にある複数個の分割縁部を有する。チップはチップキャリア上に設置され且つ電気的にチップキャリアと接続される。封止体は実質的にチップキャリアの上表面を覆いながらチップを密封し、封止体両側にそれぞれモルド流動限定部が形成され、このモルド流動限定部は封止体の中央頂面より低くなって対応のチップキャリアの分割縁部と一列に並んでいる。   First, a MAP type semiconductor package structure according to the present invention includes a chip carrier, at least one chip, and a sealing body. The chip carrier has an upper surface, a lower surface, and a plurality of split edges between the upper and lower surfaces. The chip is placed on the chip carrier and electrically connected to the chip carrier. The sealing body seals the chip while substantially covering the upper surface of the chip carrier, and a mold flow limiting portion is formed on each side of the sealing body, and this mold flow limiting portion is lower than the central top surface of the sealing body. Are aligned with the split edge of the corresponding chip carrier.

本発明の目的と問題解決において、もっと実現できる技術をこれから説明する。
前記のＭＡＰ型半導体パッケージ構造には、各モルド流動限定部は側頂面を有し、各側頂面からチップキャリアの上表面までの高さを第一高度と呼び、封止体の中央頂面からチップの能動面までの高さを第二高度と呼び、第一高度が第二高度に接近するように第一高度を低くする。 A technique that can be more realized in the object and problem solving of the present invention will now be described.
In the MAP type semiconductor package structure, each mold flow restricting portion has a side top surface, and the height from each side top surface to the top surface of the chip carrier is called a first height, The height from the surface to the active surface of the chip is called the second height, and the first height is lowered so that the first height approaches the second height.

前記のＭＡＰ型半導体パッケージ構造では、パッケージ構造は長方体の形であり、両モルド流動限定部は帯状となり、封止体の他の両側はモルド流動限定部を形成しない。
前記のＭＡＰ型半導体パッケージ構造では、各モルド流動限定部の広さはチップの側面を越えず且つ各モルド流動限定部とチップの側面との隙間は前記の第一高度と大体一致或いはより短い。 In the MAP type semiconductor package structure described above, the package structure is in the shape of a rectangular parallelepiped, both mold flow limiting portions are band-shaped, and the other sides of the sealing body do not form mold flow limiting portions.
In the MAP type semiconductor package structure, the width of each mold flow limiting portion does not exceed the side surface of the chip, and the gap between each mold flow limiting portion and the side surface of the chip is approximately the same as or shorter than the first height.

前記のＭＡＰ型半導体パッケージ構造は、他に複数個のボンディングワイヤを備え、電気的にチップとチップキャリアとの接続用として使われる。
前記のＭＡＰ型半導体パッケージ構造では、チップキャリアの上表面にチップの能動面が貼着され、チップの複数個のボンディングパッドはチップキャリアの孔に位置合わせされてそれらのボンディングワイヤで孔を貫通して電気的にそれらのボンディングパッドとチップキャリアとを接続する。 The MAP type semiconductor package structure includes a plurality of other bonding wires, and is used for electrically connecting a chip and a chip carrier.
In the MAP type semiconductor package structure, the active surface of the chip is adhered to the upper surface of the chip carrier, and a plurality of bonding pads of the chip are aligned with the holes of the chip carrier and penetrate the holes with their bonding wires. Then, the bonding pads and the chip carrier are electrically connected.

前記のＭＡＰ型半導体パッケージ構造では、チップの能動面はチップキャリアの上表面から離れ、そして、ボンディングワイヤを用いてチップ能動面上にあるボンディングパッドとチップキャリアとを電気的に接続する。
前記のＭＡＰ型半導体パッケージ構造には、他にチップキャリアの下表面に接合される複数個の外接端子を有する。
前記のＭＡＰ型半導体パッケージ構造では、それらの外接端子は半田ボールを有する。 In the MAP type semiconductor package structure, the active surface of the chip is separated from the upper surface of the chip carrier, and the bonding pads on the chip active surface and the chip carrier are electrically connected using bonding wires.
The MAP semiconductor package structure has a plurality of external terminals that are bonded to the lower surface of the chip carrier.
In the MAP type semiconductor package structure, the external terminals have solder balls.

本発明の第一実施例において、ＭＡＰ型半導体パッケージ構造２００は主にチップキャリア２１０、少なくとも一つのチップ２２０、及び封止体２３０を有する。この半導体パッケージ構造２００はモルドアレイプロセス（Mold Array Process）で封止体２３０を形成するので、封止体２３０はチップキャリア２１０の大部分面積を覆い、且つ封止体２３０の周囲縁部はチップキャリア２１０の四辺分割縁部２１３と一列に並んでいる。
チップキャリア２１０は上表面２１１、下表面２１２、及び上表面２１１と下表面２１２との間にある複数個の分割縁部２１３を有する。本実施例には、チップキャリア２１０の材料は内部に線路を持つ印刷回路基板、セラミク回路基板、リードフレーム、或いは金属キャリアボードを使うことができる。 In the first embodiment of the present invention, the MAP type semiconductor package structure 200 mainly includes a chip carrier 210, at least one chip 220, and a sealing body 230. Since the semiconductor package structure 200 forms the encapsulant 230 by a mold array process, the encapsulant 230 covers a large area of the chip carrier 210 and the peripheral edge of the encapsulant 230 is a chip. The carrier 210 is aligned with the four-side split edge 213 of the carrier 210.
The chip carrier 210 has an upper surface 211, a lower surface 212, and a plurality of divided edges 213 between the upper surface 211 and the lower surface 212. In this embodiment, the material of the chip carrier 210 may be a printed circuit board having a line inside, a ceramic circuit board, a lead frame, or a metal carrier board.

チップ２２０はチップキャリア２１０の上表面２１１に設置され、電気的にチップキャリア２１０と接続される。具体に言えば、チップ２２０は能動面２２１と能動面２２１の反対側の背面２２２を有し、複数個のボンディングパッド２２３は能動面２２１上に形成され、且つ周知のワイヤボンディング或いはフリップチップ接合方式を用いてチップキャリア２１０と電気的に接続される。本実施例では、チップ２２０の能動面２２１はチップキャリア２１０の上表面２１１から離れて、従来のダイアタッチ材料を用いてチップ２２０の背面２２２をチップキャリア２１０の上表面２１１或いは他のチップ上に粘着し（図に示していない）、且つ伝統的なワイヤボンディングで形成した複数のボンディングワイヤ２４０を使ってそれらのボンディングパッド２２３とチップキャリア２１０のインナーフィンガー（inner finger、図に示していない）とを接続する。   The chip 220 is installed on the upper surface 211 of the chip carrier 210 and is electrically connected to the chip carrier 210. Specifically, the chip 220 has an active surface 221 and a back surface 222 opposite to the active surface 221, and a plurality of bonding pads 223 are formed on the active surface 221, and a known wire bonding or flip chip bonding method is used. Is electrically connected to the chip carrier 210. In this embodiment, the active surface 221 of the chip 220 is separated from the upper surface 211 of the chip carrier 210, and the back surface 222 of the chip 220 is placed on the upper surface 211 of the chip carrier 210 or another chip using a conventional die attach material. Adhering (not shown) and using a plurality of bonding wires 240 formed by traditional wire bonding, the bonding pads 223 and the inner fingers of the chip carrier 210 (not shown) Connect.

なお、図３に示すように、封止体２３０はモルドアレイプロセス（Mold Array Process）技術で実質的にチップキャリア２１０の上表面２１１を覆いながらチップ２２０を密封する。図４を参考にして、封止体２３０の両側にそれぞれモルド流動限定部２３１が形成され、それらのモルド流動限定部２３１は封止体２３０の中央頂面２３３より低くなり且つ対応のチップキャリア２１０の分割縁部２１３と一列に並んでいる。本実施例では、半導体パッケージ構造２００は長方体の形であり、両モルド流動限定部２３１は帯状となり、そして、封止体２３０の他の両側にはモルド流動限定部２３１を形成しない。図３に示すように、それらの側頂面２３４からチップキャリア２１０の上表面２１１までの第一高度Ｈ１は、封止体２３０の中央頂面２３３からチップ２２０の能動面２２１までの第二高度Ｈ２に接近するため、低くされることによって、モルドアレイプロセスで封止体２３０を形成する過程でチップ２２０の厚さに一致或いは接近するように両モルド流動限定部２３１の高さを下げることが可能である。図６に示すモルドフロウ方向２３２では、チップキャリア２１０の両側モルドフロウ速度は、チップ２２０に障害されるチップキャリア２１０の中央モルドフロウ速度に相当するように、遅くされる。従って、後段製造工程に対しチップ２２０の側面に起きるＭＡＰ実装気泡を防止することが可能である。   As shown in FIG. 3, the sealing body 230 seals the chip 220 while substantially covering the upper surface 211 of the chip carrier 210 by a Mold Array Process technique. Referring to FIG. 4, mold flow limiting portions 231 are formed on both sides of the sealing body 230, respectively, and these mold flow limiting portions 231 are lower than the central top surface 233 of the sealing body 230 and correspond to the chip carrier 210. Are aligned with the divided edge portion 213. In this embodiment, the semiconductor package structure 200 has a rectangular shape, both the mold flow limiting portions 231 have a band shape, and the mold flow limiting portions 231 are not formed on the other sides of the sealing body 230. As shown in FIG. 3, the first height H1 from the side top surfaces 234 to the upper surface 211 of the chip carrier 210 is the second height from the central top surface 233 of the sealing body 230 to the active surface 221 of the chip 220. By approaching H2, the height of both mold flow limiting portions 231 can be lowered so as to match or approach the thickness of the chip 220 in the process of forming the sealing body 230 by the mold array process. It is. In the mold flow direction 232 shown in FIG. 6, the two-sided mold flow speed of the chip carrier 210 is slowed to correspond to the central mold flow speed of the chip carrier 210 obstructed by the chip 220. Therefore, it is possible to prevent MAP mounting bubbles that occur on the side surface of the chip 220 in the subsequent manufacturing process.

また、図３と図４を参考にして、それらのモルド流動限定部２３１の広さはチップ２２０の側面を超えず、且つそれらのモルド流動限定部２３１とチップ２２０の側面との隙間Ｓ１は前記第一高度Ｈ１と大体一致或いはより短いので、封止体２３０は帽子形断面が有るようになりチップキャリア２１０の両側モルドフロウ速度は中央モルドフロウ速度ともっと一致する。
それ以外に、半導体パッケージ構造２００は、他にチップキャリア２１０の下表面２１２上に接合される複数個の外接端子２５０を有し、本実施例においてそれらの外接端子２５０は半田ボールを有する。 3 and 4, the width of the mold flow limiting portion 231 does not exceed the side surface of the chip 220, and the gap S1 between the mold flow limiting portion 231 and the side surface of the chip 220 is Since the first height H1 is approximately the same or shorter, the sealing body 230 has a hat-shaped cross section, and the two-sided mold flow speed of the chip carrier 210 is more consistent with the center mold flow speed.
In addition, the semiconductor package structure 200 has a plurality of external terminals 250 bonded to the lower surface 212 of the chip carrier 210. In the present embodiment, the external terminals 250 have solder balls.

故に、前記の半導体パッケージ構造２００において、ＭＡＰで封止体２３０を形成する時にチップキャリア２１０の中央と側辺のモルドフロウ速度はほぼ一致しチップ２２０の側面にＭＡＰ実装気泡という現象は発生しなくなる。このように封止体２３０形状を変化させることだけで周知の障碍物使用技術によりチップキャリア２１０の両側で封止体２３０が流れる速度を遅らせる効果を達成することができる。   Therefore, in the semiconductor package structure 200 described above, when the sealing body 230 is formed by MAP, the mold flow speeds of the center and the side of the chip carrier 210 substantially coincide with each other, and the phenomenon of MAP mounting bubbles on the side surface of the chip 220 does not occur. Thus, the effect of delaying the flow rate of the sealing body 230 on both sides of the chip carrier 210 can be achieved only by changing the shape of the sealing body 230 by a known obstacle use technique.

以下、半導体パッケージ構造２００のＭＡＰ製造過程について更に説明する。まず、図５Ａと図６を参考にして、基板を提供して、この基板はアレイ（Array）に配置され且つ一体化されて連結される複数個のチップキャリア２１０を有する。また、図５Ｂに示すように、それらのチップキャリア２１０の上表面２１１に複数個のチップ２２０が設置され、それらのボンディングワイヤ２４０で電気的にそれらのチップ２２０とそれらのチップキャリア２１０とを接続する。なお、図５Ｃと図６に示すように、トランスファーモルディング（Transfer Molding）方式を用いて封止体２３０を形成し、つまり、上鋳型１０と下鋳型２０を用いて基板を挟持し、封止体２３０の形成用として上鋳型１０は非平面なキャビティ（cavity）を有する。封止体２３０は一体化且つ実質的にそれらのチップキャリア２１０の上表面２１１を覆いながらそれらのチップ２２０を密封する。各チップキャリア２１０に対応する封止体２３０の両側にそれぞれモルド流動限定部２３１が形成され、各モルド流動限定部２３１は封止体２３０の中央頂面２３３より低くになることで両側のモルドフロウ速度を緩めることが可能である。図６に示すように、モルドフロウ方向によれば、各チップキャリア２１０に対応する封止体２３０の両側モルドフロウ速度は封止体２３０の中央モルドフロウ速度に相当するように緩められる。図５Ｄに示すように、鋳型から取り出した後、障碍物使用技術の代わりに周知のＭＡＰ実装気泡の問題を解決することができる。最後に、ソーイング（sawing）方式で封止体２３０と基板とを個別的に分離させて図３及び図４に示すような複数個の半導体パッケージ構造２００を得ることができる。よって、各チップキャリア２１０は上表面２１１と下表面２１２との間にある複数個の分割縁部２１３を有して、個別的に切開された後に封止体２３０のモルド流動限定部２３１は対応のチップキャリア２１０の分割縁部２１３と一列に並んでいる。   Hereinafter, the MAP manufacturing process of the semiconductor package structure 200 will be further described. First, referring to FIGS. 5A and 6, a substrate is provided, and the substrate includes a plurality of chip carriers 210 arranged in an array and connected integrally. Further, as shown in FIG. 5B, a plurality of chips 220 are installed on the upper surface 211 of the chip carriers 210, and the chips 220 and the chip carriers 210 are electrically connected by their bonding wires 240. To do. As shown in FIGS. 5C and 6, the sealing body 230 is formed by using a transfer molding method, that is, the substrate is sandwiched between the upper mold 10 and the lower mold 20 and sealed. For forming the body 230, the upper mold 10 has a non-planar cavity. The sealing body 230 seals the chips 220 integrally and substantially covering the upper surface 211 of the chip carriers 210. Mold flow limiting portions 231 are formed on both sides of the sealing body 230 corresponding to each chip carrier 210, and each mold flow limiting portion 231 is lower than the central top surface 233 of the sealing body 230, so that the mold flow speeds on both sides are reduced. Can be loosened. As shown in FIG. 6, according to the mold flow direction, the both-side mold flow speed of the sealing body 230 corresponding to each chip carrier 210 is reduced so as to correspond to the central mold flow speed of the sealing body 230. As shown in FIG. 5D, after taking out from the mold, the well-known MAP mounting bubble problem can be solved instead of the obstacle use technique. Finally, the sealing body 230 and the substrate are individually separated by a sawing method to obtain a plurality of semiconductor package structures 200 as shown in FIGS. Therefore, each chip carrier 210 has a plurality of divided edges 213 between the upper surface 211 and the lower surface 212, and the mold flow restricting portion 231 of the sealing body 230 corresponds after being individually cut. The chip carrier 210 is aligned with the dividing edge 213 of the chip carrier 210.

図７に参考にして、本発明の第二実施例において、ＭＡＰ型半導体パッケージ構造３００は、チップキャリア３１０、少なくとも一つのチップ３２０、及び封止体３３０を備える。チップキャリア３１０は上表面３１１、下表面３１２、及び上表面３１１と下表面３１２との間にある複数個の分割縁部３１４を有する。チップ３２０はチップキャリア３１０の上表面３１１に設置され、また、電気的にチップキャリア３１０と接続される。本実施例では、パッケージ構造はウインドウボールグリッドアレイ（Window Ball Grid Array、ＢＧＡ）である。チップ３２０の能動面３２１はチップキャリア３１０の上表面３１１に貼着され、チップ３２０の複数個のボンディングパッド３２２はチップキャリア３１０の孔３１３に位置合わせされて複数個のボンディングワイヤ３４０で孔３１３を貫通して電気的にそれらのボンディングパッド３２２とチップキャリア３１０とを接続する。   Referring to FIG. 7, in the second embodiment of the present invention, the MAP type semiconductor package structure 300 includes a chip carrier 310, at least one chip 320, and a sealing body 330. The chip carrier 310 has an upper surface 311, a lower surface 312, and a plurality of divided edges 314 between the upper surface 311 and the lower surface 312. The chip 320 is installed on the upper surface 311 of the chip carrier 310 and is electrically connected to the chip carrier 310. In this embodiment, the package structure is a window ball grid array (BGA). The active surface 321 of the chip 320 is attached to the upper surface 311 of the chip carrier 310, and the plurality of bonding pads 322 of the chip 320 are aligned with the holes 313 of the chip carrier 310 and the holes 313 are formed by the plurality of bonding wires 340. The bonding pads 322 and the chip carrier 310 are electrically connected by penetrating.

封止体３３０は、実質的にチップキャリア３１０の上表面３１１を覆い、孔３１３を充填してチップ３２０とそれらのボンディングワイヤ３４０を密封する。封止体３３０の上表面３１１両側にそれぞれモルド流動限定部３３１が形成され、各モルド流動限定部３３１は封止体３３０の中央頂面３３２より低くなり且つ対応のチップキャリア３１０の分割縁部３１４と一列に並んでいる。   The sealing body 330 substantially covers the upper surface 311 of the chip carrier 310 and fills the holes 313 to seal the chips 320 and their bonding wires 340. Mold flow limiting portions 331 are formed on both sides of the upper surface 311 of the sealing body 330, and each mold flow limiting portion 331 is lower than the central top surface 332 of the sealing body 330 and the divided edge 314 of the corresponding chip carrier 310. Are in a row.

従って、障碍物を使用しない限り中央と側辺とのモルドフロウがお互いにバランスを取ることができ、チップ３２０の側辺にＭＡＰ実装気泡の現象は発生しなくなる。また、両側のモルド流動限定部３３１は封止体３３０の中央より低くなって、より小さい分割面を得ること及び切断工具の研磨損失を低減することができる。
本発明の保護範囲は特許申請範囲で限定されて、この保護範囲に基準して、本発明の精神と範囲内に触れるどんな変更や修正も本発明の保護範囲に属する。 Therefore, unless the obstacle is used, the mold flow at the center and the side can be balanced with each other, and the phenomenon of MAP mounting bubbles on the side of the chip 320 does not occur. Further, the mold flow limiting portions 331 on both sides are lower than the center of the sealing body 330, so that a smaller dividing surface can be obtained and the polishing loss of the cutting tool can be reduced.
The scope of protection of the present invention is limited by the scope of patent application, and any change or modification that comes within the spirit and scope of the present invention based on this scope of protection belongs to the scope of protection of the present invention.

周知のＭＡＰ型半導体パッケージ構造を示す断面図である。It is sectional drawing which shows a known MAP type semiconductor package structure. 周知のＭＡＰ製造過程中に封止体がアレイ型基板上に流れる速度の差を示す平面図である。It is a top view which shows the difference in the speed which a sealing body flows on an array type | mold board | substrate during a well-known MAP manufacturing process. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造を示す断面図である。1 is a cross-sectional view showing a MAP type semiconductor package structure according to a first embodiment of the present invention. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造を示す上面図である。1 is a top view showing a MAP type semiconductor package structure according to a first embodiment of the present invention. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造の製造過程を示す断面図である。It is sectional drawing which shows the manufacture process of the MAP type | mold semiconductor package structure by 1st Example of this invention. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造の製造過程を示す断面図である。It is sectional drawing which shows the manufacture process of the MAP type | mold semiconductor package structure by 1st Example of this invention. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造の製造過程を示す断面図である。It is sectional drawing which shows the manufacture process of the MAP type | mold semiconductor package structure by 1st Example of this invention. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造の製造過程を示す断面図である。It is sectional drawing which shows the manufacture process of the MAP type | mold semiconductor package structure by 1st Example of this invention. 本発明の第一実施例によるＭＡＰ型半導体パッケージ構造の製造過程中に封止体がアレイ型基板上に流れる速度の一致を示す平面図である。It is a top view which shows the coincidence of the speed which a sealing body flows on an array type | mold board | substrate during the manufacture process of the MAP type semiconductor package structure by 1st Example of this invention. 本発明の第二実施例によるＭＡＰ型半導体パッケージ構造を示す断面図である。It is sectional drawing which shows the MAP type | mold semiconductor package structure by 2nd Example of this invention.

符号の説明Explanation of symbols

１０ 上鋳型、２０ 下鋳型、２００ ＭＡＰ型半導体パッケージ構造、２１０ チップキャリア、２１１ 上表面、２１２ 下表面、２１３ 分割縁部、２２０ チップ、２２１ 能動面、２２２ 背面、２２３ ボンディングパッド、２３０ 封止体、２３１ モルド流動限定部、２３２ モルドフロウ方向、２３３ 中央頂面、２３４ 側頂面、２４０ ボンディングワイヤ、２５０ 外接端子、３００ ＭＡＰ型半導体パッケージ構造、３１０ チップキャリア、３１１ 上表面、３１２ 下表面、３１３ 孔、３１４ 分割縁部、３２０ チップ、３２１ 能動面、３２２ ボンディングパッド、３３０ 封止体、３３１ モルド流動限定部、３３２ 中央頂面、３４０ ボンディングワイヤ、３５０ 外接端子、Ｈ１ 第一高度、Ｈ２ 第二高度、Ｓ１ 隙間   10 upper mold, 20 lower mold, 200 MAP type semiconductor package structure, 210 chip carrier, 211 upper surface, 212 lower surface, 213 split edge, 220 chip, 221 active surface, 222 back surface, 223 bonding pad, 230 sealing body 231 Mold flow restriction part, 232 Mold flow direction, 233 Central top surface, 234 side top surface, 240 Bonding wire, 250 External terminal, 300 MAP type semiconductor package structure, 310 Chip carrier, 311 Upper surface, 312 Lower surface, 313 hole 314 Dividing edge, 320 chip, 321 active surface, 322 bonding pad, 330 sealing body, 331 mold flow limiting portion, 332 center top surface, 340 bonding wire, 350 external terminal, H1 first altitude, H2 second altitude , S1 Gap

Claims (18)

上表面、下表面、及び上表面と下表面との間にある複数個の分割縁部を有するチップキャリアと、
チップキャリアの上表面に設置され且つ電気的にチップキャリアと接続される少なくとも一つのチップと、
実質的にチップキャリアの上表面を覆いながらチップを封止し、両側にそれぞれモルド流動限定部が形成され、各モルド流動限定部が中央頂面より低くなり且つ対応のチップキャリアの分割縁部と一列に並んでいる封止体と、
を備えることを特徴とするＭＡＰ型半導体パッケージ。 A chip carrier having an upper surface, a lower surface, and a plurality of split edges between the upper surface and the lower surface;
At least one chip installed on the upper surface of the chip carrier and electrically connected to the chip carrier;
The chip is sealed while substantially covering the upper surface of the chip carrier, and mold flow limiting portions are formed on both sides, respectively, each mold flow limiting portion is lower than the central top surface, and the divided edge of the corresponding chip carrier Sealing bodies arranged in a row;
A MAP type semiconductor package comprising: 各モルド流動限定部は、側頂面を有し、各側頂面からチップキャリアの上表面までの高さを第一高度と呼び、封止体の中央頂面からチップの能動面までの高さを第二高度と呼び、第一高度と第二高度とが接近するように第一高度を低くすることを特徴とする請求項１に記載のＭＡＰ型半導体パッケージ。   Each mold flow restricting portion has a side top surface, and the height from each side top surface to the top surface of the chip carrier is called a first height, and the height from the central top surface of the sealing body to the active surface of the chip. The MAP type semiconductor package according to claim 1, wherein the first altitude is lowered so that the first altitude and the second altitude are close to each other. 長方体の形であり、両モルド流動限定部は帯状となり、また、封止体（２３０）の他の両側にはモルド流動限定部を形成しないことを特徴とする請求項１に記載のＭＡＰ型半導体パッケージ。   The MAP according to claim 1, which is in the shape of a rectangular parallelepiped, both mold flow limiting portions are band-shaped, and no mold flow limiting portions are formed on the other sides of the sealing body (230). Type semiconductor package. 各モルド流動限定部の広さはチップの側面に超えず、また、各モルド流動限定部と対応のチップ側面との隙間は前記第一高度と大体一致或いはより短いことを特徴とする請求項２に記載のＭＡＰ型半導体パッケージ。   3. The width of each mold flow restricting portion does not exceed the side surface of the chip, and the gap between each mold flow restricting portion and the corresponding chip side surface is substantially coincident with or shorter than the first altitude. The MAP type semiconductor package described in 1. 他に複数個のボンディングワイヤを有し、前記ボンディングワイヤが電気的にチップとチップキャリアとの接続用として用いられることを特徴とする請求項１に記載のＭＡＰ型半導体パッケージ。   The MAP type semiconductor package according to claim 1, further comprising a plurality of bonding wires, wherein the bonding wires are used for electrically connecting a chip and a chip carrier. チップの能動面がチップキャリアの上表面に貼着され、チップの複数個のボンディングパッドはチップキャリアの孔に位置合わせされて前記ボンディングワイヤで孔を貫通して電気的に前記ボンディングパッドとチップキャリアとを接続することを特徴とする請求項５に記載のＭＡＰ型半導体パッケージ。   The active surface of the chip is attached to the upper surface of the chip carrier, and the plurality of bonding pads of the chip are aligned with the holes of the chip carrier and penetrate the holes with the bonding wires to electrically connect the bonding pads and the chip carrier. The MAP type semiconductor package according to claim 5, wherein: チップの能動面はチップキャリアの上表面から離れ、ボンディングワイヤを用いてチップ能動面上にあるボンディングパッドとチップキャリアとを電気的に接続することを特徴とする請求項５に記載のＭＡＰ型半導体パッケージ。   6. The MAP type semiconductor according to claim 5, wherein an active surface of the chip is separated from an upper surface of the chip carrier, and a bonding pad on the chip active surface is electrically connected to the chip carrier using a bonding wire. package. 他にチップキャリアの下表面に接合される複数個の外接端子を有することを特徴とする請求項１に記載のＭＡＰ型半導体パッケージ。   2. The MAP type semiconductor package according to claim 1, further comprising a plurality of external terminals joined to the lower surface of the chip carrier. 前記外接端子は半田ボールを有することを特徴とする請求項８に記載のＭＡＰ型半導体パッケージ。   9. The MAP type semiconductor package according to claim 8, wherein the external terminal has a solder ball. アレイに設置され、且つ一体化されて連結され上表面と下表面とを有する複数個のチップキャリアを備える基板を提供するステップと、
複数個のチップを前記チップキャリアの上表面に設置するステップと、
前記チップと前記チップキャリアとを電気的に接続するステップと、
一体化且つ実質的に前記チップキャリアの上表面を覆いながら前記チップを密封し、各チップキャリアに対応する両側にそれぞれモルド流動限定部が形成され、各モルド流動限定部が中央頂面より低くなることで両側モルドフロウ速度を緩めることが可能である封止体をトランスファーモルディング（Transfer Molding）方式を用いて形成するステップと、
封止体と基板とを分割し、各チップキャリアが上表面と下表面との間にある複数個の分割縁部を有し、個別的に切開された後に封止体のモルド流動限定部が対応のチップキャリアの分割縁部と一列に並べられるステップと、
を少なくとも含むことを特徴とする半導体パッケージのＭＡＰ製造方法。 Providing a substrate comprising a plurality of chip carriers installed in an array and integrally connected and having an upper surface and a lower surface;
Installing a plurality of chips on the upper surface of the chip carrier;
Electrically connecting the chip and the chip carrier;
The chip is sealed while integrally and substantially covering the upper surface of the chip carrier, and mold flow limiting portions are formed on both sides corresponding to each chip carrier, and each mold flow limiting portion is lower than the central top surface. Forming a sealing body that can relax the mold flow velocity on both sides by using a transfer molding method,
The sealing body and the substrate are divided, and each chip carrier has a plurality of dividing edges between the upper surface and the lower surface, and the mold flow limiting portion of the sealing body is formed after being individually cut. Being aligned with the split edge of the corresponding chip carrier;
A MAP manufacturing method for a semiconductor package, comprising: 各モルド流動限定部は側頂面を有し、各側頂面からチップキャリアの上表面までの高さを第一高度と呼び、封止体の中央頂面からチップの能動面までの高さを第二高度と呼び、第一高度が第二高度に接近するように第一高度を低くすることを特徴とする請求項１０に記載の半導体パッケージのＭＡＰ製造方法。   Each mold flow limiting portion has a side top surface, and the height from each side top surface to the top surface of the chip carrier is called a first height, and the height from the central top surface of the sealing body to the active surface of the chip The semiconductor package MAP manufacturing method according to claim 10, wherein the first height is lowered so that the first height approaches the second height. 分割した後に複数個のパッケージは長方体の形であり、前記モルド流動限定部は帯状となり、また、封止体（２３０）の他の両側にはモルド流動限定部を形成しないことを特徴とする請求項１０に記載の半導体パッケージのＭＡＰ製造方法。   After dividing, the plurality of packages are in the shape of a rectangular parallelepiped, the mold flow restricting portion has a band shape, and no mold flow restricting portion is formed on the other side of the sealing body (230). The MAP manufacturing method of a semiconductor package according to claim 10. 前記モルド流動限定部の広さはチップの側面に超えず、また、前記モルド流動限定部と対応のチップ側面との隙間は前記第一高度と大体一致或いはより短くなることを特徴とする請求項１２に記載の半導体パッケージのＭＡＰ製造方法。   The width of the mold flow limiting portion does not exceed the side surface of the chip, and the gap between the mold flow limiting portion and the corresponding chip side surface is substantially the same as or shorter than the first altitude. 12. A MAP manufacturing method of a semiconductor package according to 12. 電気的に接続するステップにおいて、複数個のボンディングワイヤを用いて電気的にチップとチップキャリアとを接続することを特徴とする請求項１０に記載の半導体パッケージのＭＡＰ製造方法。   11. The method of manufacturing a MAP of a semiconductor package according to claim 10, wherein in the step of electrically connecting, the chip and the chip carrier are electrically connected using a plurality of bonding wires. チップの能動面がチップキャリアの上表面に貼着され、チップの複数個のボンディングパッドはチップキャリアの孔に位置合わせされて前記ボンディングワイヤで孔を貫通して電気的にそれらのボンディングパッドとチップキャリアとを接続することを特徴とする請求項１４に記載の半導体パッケージのＭＡＰ製造方法。   The active surface of the chip is attached to the upper surface of the chip carrier, and a plurality of bonding pads of the chip are aligned with the holes of the chip carrier and penetrate the holes with the bonding wires to electrically connect the bonding pads and the chip. 15. The method of manufacturing a MAP of a semiconductor package according to claim 14, wherein the MAP is connected to a carrier. チップの能動面はチップキャリアの上表面から離れ、ボンディングワイヤを用いてチップ能動面上にあるボンディングパッドとチップキャリアとを電気的に接続することを特徴とする請求項１４に記載の半導体パッケージのＭＡＰ製造方法。   15. The semiconductor package according to claim 14, wherein an active surface of the chip is separated from an upper surface of the chip carrier, and a bonding pad on the chip active surface is electrically connected to the chip carrier using a bonding wire. MAP manufacturing method. 他にチップキャリアの下表面に接合される複数個の外接端子を有することを特徴とする請求項１０に記載の半導体パッケージのＭＡＰ製造方法。   11. The semiconductor package MAP manufacturing method according to claim 10, further comprising a plurality of external terminals joined to the lower surface of the chip carrier. 前記外接端子は半田ボールを有することを特徴とする請求項１７に記載の半導体パッケージのＭＡＰ製造方法。



18. The method of manufacturing a MAP of a semiconductor package according to claim 17, wherein the external terminal has a solder ball.



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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016684A (en) * 2011-07-05 2013-01-24 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
KR101388892B1 (en) * 2012-08-20 2014-04-29 삼성전기주식회사 Package substrate, manufacturing method thereof and manufacturing mold thereof
CN105761703A (en) * 2016-05-20 2016-07-13 京东方科技集团股份有限公司 Array substrate, display device and charging control method
WO2017179326A1 (en) * 2016-04-11 2017-10-19 株式会社村田製作所 Module

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016684A (en) * 2011-07-05 2013-01-24 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
KR101388892B1 (en) * 2012-08-20 2014-04-29 삼성전기주식회사 Package substrate, manufacturing method thereof and manufacturing mold thereof
US9064882B2 (en) 2012-08-20 2015-06-23 Samsung Electro-Mechanics Co., Ltd. Package substrate, manufacturing method thereof, and mold therefor
WO2017179326A1 (en) * 2016-04-11 2017-10-19 株式会社村田製作所 Module
JPWO2017179326A1 (en) * 2016-04-11 2019-02-21 株式会社村田製作所 module
US10872853B2 (en) 2016-04-11 2020-12-22 Murata Manufacturing Co., Ltd. Module
CN105761703A (en) * 2016-05-20 2016-07-13 京东方科技集团股份有限公司 Array substrate, display device and charging control method

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