201128718 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之製造技術，特別係有關 於一種陣列模封方法及其使用之模具。 【先前技術】 按現有半導體晶片封裝之陣列模封技術是為了方便 大量封裝晶片與方便地切割單離出封裝構造，晶片設置 方式是在基板上呈矩陣排列。基板上供一次模封的晶片 •數量日漸增加，在進行陣列模封製程時，多個晶片越發 緊密地容納於一模具内’而且由晶片上方至模具上壁之 間的空間亦會愈來愈小。例如，當晶片堆疊的數量越來 越多時，晶片方面至模具之間所能提供的模流空間也越 小，使得封膠製程中模封樹脂因模流速度不均衡而形成 氣泡（void)或氣洞，或稱之「回包現象（AirTrapeffect)」， 其將使半導體晶片的封裝品質大受影響。 Φ 如第1圖所示，為習知的陣列模封方法中設置複數個 晶片120於一基板110時之立體示意圖。該基板11〇係 具有複數個矩陣陣列之基板單元m、複數個在該些基 板單111之問的切割道i丨2以及兩側與模流方向同向 之邊緣區113。該些晶片120係設置於該基板u〇之一 上表面114並位於對應之該些基板單元U1内。 如第2圖所示’上述陣列模封方法之封膠過程中，藉 由一模具130形成一模封膠體ι4〇於該基板11〇之該上 表面114，在灌入該模封膠體14〇時，由於該些基板單 201128718 元111設有該些晶片12 0而使得流經該些基板單元η j 上之模流速度降低，而流經該些邊緣區丨丨3上的模流速 度則相對較快’而產生嚴重的回包現象（Air Trap effect)。所謂的「回包現象」又稱之氣洞現象，係指空 氣滞留（air trap)於模穴内’在封膠時該模封膠體14〇無 法填滿該些基板單元111上的模封空間，於是該模封膠 體140内會產生填隙不良（P〇or fiu)和内部氣洞（inner voids)之現象，甚至導致封裝外觀不良，進而生產不良 率增加。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於一赛 陣列模封方法及其使用之模具，彳改善回包現象，並能 有效改善外觀不良問題，進而提升生產良率。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示—種陣列模封方法纟要包含 有以下步驟.冑供-基板，係具有複數個矩陣陣列之基 板單元、複數個在該些基板單元之間的㈣道以及兩側 與模流方向同向之邊緣區。設置複數個第-晶片於該基 板之一上表面並位於對應之該些基板單元内。設置一模 具於該基板之該上表面，該模具係具有—卫字型模寫， 該工字型模窩之兩側係内縮為對稱之模流限制冑，用以 減縮該些邊緣區上的描φ Α 上的模流寬度。形成一模封膠體於該基 板之該上表面’灌庄未固化前之模封膠體時，藉由該些 模流限制部限制該模封膠體在該㈣緣區上之流量，:201128718 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to an array molding method and a mold for use thereof. [Prior Art] The array molding technique according to the conventional semiconductor chip package is for facilitating a large number of packaged wafers and for conveniently cutting a single-out package structure, and the wafer arrangement is arranged in a matrix on the substrate. The number of wafers for one-time molding on the substrate is increasing. When the array molding process is performed, the plurality of wafers are more closely packed in a mold' and the space between the upper side of the wafer and the upper wall of the mold is also getting more and more. small. For example, when the number of wafer stacks is increasing, the mold flow space that can be provided between the wafer side and the mold is smaller, so that the molding resin in the seal molding process forms a bubble due to the uneven mold flow velocity. Or a gas hole, or "AirTrapeffect", will greatly affect the packaging quality of semiconductor wafers. Φ As shown in Fig. 1, a perspective view of a plurality of wafers 120 disposed on a substrate 110 in a conventional array molding method is shown. The substrate 11 is a substrate unit m having a plurality of matrix arrays, a plurality of dicing streets i 丨 2 in the substrate sheets 111, and edge regions 113 on both sides in the same direction as the mold flow direction. The wafers 120 are disposed on one of the upper surfaces 114 of the substrate u and are located in the corresponding substrate units U1. As shown in Fig. 2, in the encapsulation process of the above array molding method, a mold encapsulant ι4 is formed on the upper surface 114 of the substrate 11 by a mold 130, and the molding compound 14 is poured therein. At this time, since the substrate sheets 201128718 111 are provided with the wafers 120, the mold flow velocity flowing through the substrate units η j is lowered, and the mold flow velocity flowing through the edge regions 丨丨3 is Relatively fast' and a serious Air Trap effect. The so-called "returning phenomenon", also known as the air hole phenomenon, refers to the air trap in the cavity. The molding encapsulant 14〇 cannot fill the molding space on the substrate unit 111 during the sealing process. Therefore, the phenomenon of poor interstitial (P〇or fiu) and inner voids in the mold encapsulant 140 may result in poor appearance of the package and an increase in the production defect rate. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide an array pattern sealing method and a mold for use thereof, which can improve the returning phenomenon and effectively improve the appearance defect, thereby improving the production yield. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses an array sealing method which comprises the following steps: a substrate-substrate, a substrate unit having a plurality of matrix arrays, a plurality of (four) tracks between the substrate units, and both sides and a mold flow direction The same edge area. A plurality of first wafers are disposed on an upper surface of the substrate and located in the corresponding substrate units. Forming a mold on the upper surface of the substrate, the mold has a U-shaped mold, and the two sides of the I-shaped mold cavity are contracted into a symmetrical mold flow restriction 胄 for reducing the edge regions The width of the mold flow on the trace φ Α. Forming a molding compound on the upper surface of the substrate when the uncured pre-molding molding compound is sealed, the flow of the molding compound on the (four) edge region is restricted by the mold flow restricting portions:
[SI 4 201128718 改善回包現象，使該模㈣體覆蓋該基板包含該些基板 本發明另揭示應 可採用以下技術 單元之該上表面並密封該些第一晶片。 用於上述陣列模封方法之模具。 本發明的目的及解決其技術問題還 措施進一步實現。 在前述之陣列模封方法中，該模具係可具有複數個位 於同-侧邊之以口，該些模流限制部係相對靠近設有 該些注澆口之侧邊。 在前述之陣列模封方法中，上沭祜 iL被减縮在兩側邊緣區 上的模流寬度係可不大於兮此筮 於該些第一晶片之間的模流寬 度。 ，在前述之陣列模封方法中，可另包含之步驟係為：設 置複數個第一晶片於該些第一晶片上。 在前述之陣列模封方法中，每[SI 4 201128718 improves the phenomenon of back-to-package, such that the mold (four) body covers the substrate comprising the substrates. The invention further discloses that the upper surface of the following technical unit should be used and the first wafers sealed. A mold for the above array molding method. The object of the present invention and the technical problems thereof are further solved. In the above array molding method, the mold may have a plurality of ports located on the same side, and the mold flow restricting portions are relatively close to the side edges of the gates. In the array patterning method described above, the width of the mold stream which is reduced on the side edge regions of the upper jaw iL may be no more than the width of the mold flow between the first wafers. In the foregoing array molding method, the method further includes the step of: providing a plurality of first wafers on the first wafers. In the foregoing array molding method, each
對與模流方向平行之短邊以及—對與模流方向垂直之長 邊，該長邊之長度係不小於該短邊之長度。 由以上技術方案可以看出，本發明之陣列模封方法及 其使用之模具，有以下優點與功效： 一、可藉由模具之工字型模 一技術手段，由於工字 之模流限制部，並藉由 基板之邊緣區上之流量 並能有效改善外觀不良 【實施方式】 窩之特定組合關係作為其中 型模窩之兩側係内縮為對稱 模流限制部限制模封膠體在 。因此，可改善回包現象， 問題’進而提升生產良率。 201128718The length of the long side is not less than the length of the short side, the short side parallel to the direction of the mold flow and the long side perpendicular to the direction of the mold flow. It can be seen from the above technical solution that the array sealing method of the present invention and the mold used therein have the following advantages and effects: 1. The die-shaped die-limiting part of the die can be made by the die-shaped die-technical means of the die And by the flow rate on the edge region of the substrate and can effectively improve the appearance defect [Embodiment] The specific combination relationship of the nest is as the symmetry of the mold cavity restricting the molding cavity on both sides of the mold cavity. Therefore, the phenomenon of returning can be improved, and the problem can further increase the production yield. 201128718
以下將配合所附圖示.詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種陣列模封方法舉例 說明於第3A至.3D圖繪示各步驟之元件立體示意圖第 4圖繪示其模封膠體覆蓋於基板之上視示意圖以及第5 圖繪示其模具之立體示意圖。該陣列模封方法，主要包 含以下步驟：提供一基板、設置第一晶片於基板之上表 面、設置-帛具於基板之上表面以及形成一模封膠體於 基板之上表面，在各步驟上表現元件請參閱第3A1 3D 圖，說明如下所示。 請參閱第3A圖所示，提供一基板21〇，係具有複數 個矩陣陣列之基板單元21卜複數個在該些基板單元211 之間的切割道2 12以及兩側與模流方向同向之邊緣區 213。具體而言，該基板210係可為一 印刷電路板（printed circuit b〇ard，PCB)，作為整體封裝結構之主要承載與電 性連接之媒介物。此外，該基板21〇係 丨Τ' j具有一上表面 214與一下表面（圖中未標示，即相對於該上表面214之 表面），該上表面2 14係可作為一封膠表 ^ 礅下表面係 201128718 可供設置複數個外接端子（圖中未繪出），以提供對外連 接之作用。 明參閱第3B圖所示，設置複數個第一晶片22〇於該 基板210之該上表面214並位於對應之該些基板單元2ΐι 内。在一實施例中，該些第一晶片22〇係可藉由打線或 覆曰a等方式電性連接至對應之該些基板單元211。具體 而e，該些第一晶片220之尺寸係可與該些基板單元211 之尺寸接近’而可為晶片尺寸封裝型態。 •請參閱第3C圖所示，設置一模具23〇於該基板21〇 之該上表面214,該模具230係具有一工字型模窩231， 該工子型模窩23 1之兩側係内縮為對稱之模流限制部 232,用以減縮該些邊緣區213上的模流寬度。在本實施 例中，該些模流限制部232係以朝向該些第一晶片22〇 之方向而在該工字型模窩231内橫向突出，進而佔據該 些邊緣區213上之模流空間，以縮小該些模流限制部232 φ 與相對之該些第—晶片220之間的間隙，故能達到減縮 侧邊模流寬度之功效。在本實施例中，可參閱第5圖， 該模具230係可具有複數個位於同一側邊之注澆口 233，該些模流限制部232係相對靠近設有該些注澆口 233之侧邊。詳細而言，該些注澆口 233係在澆注系統 (Feed System)中是連接流道（Runner)與該工字型模窩 23 1的模流通道。此外，該些模流限制部232係可為偏 移設置於該工字型模窩231内，而使得該工字型模寫231 在遠離該些注澆口 233之側邊形成有一較為開闊之模流 201128718 緩衝側234,故能提供一緩衝空間，以降低回包現象之 產生或使回包現象不會形成在該些封裝單元上。利用該 工字型模窩231的形狀亦不影響該些注濟口 233的配置 空間。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide more Clear description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to an embodiment of the present invention, an array molding method is illustrated in FIG. 3A to FIG. 3D, and a schematic view of the components of each step is shown in FIG. 4 . The figure shows a schematic view of the mold. The array molding method mainly comprises the steps of: providing a substrate, disposing a first wafer on an upper surface of the substrate, disposing a cooker on the upper surface of the substrate, and forming a molding compound on the upper surface of the substrate, in each step For the performance component, please refer to the 3D1 3D diagram, as shown below. Referring to FIG. 3A, a substrate 21 is provided. The substrate unit 21 having a plurality of matrix arrays has a plurality of dicing streets 12 12 between the substrate units 211 and both sides are in the same direction as the mold flow direction. Edge area 213. Specifically, the substrate 210 can be a printed circuit board (PCB) as a main carrier and electrical connection medium of the overall package structure. In addition, the substrate 21 has an upper surface 214 and a lower surface (not shown, that is, a surface opposite to the upper surface 214), and the upper surface 2 14 can be used as a rubber sheet. The lower surface system 201128718 can be used to set a plurality of external terminals (not shown) to provide an external connection. Referring to FIG. 3B, a plurality of first wafers 22 are disposed on the upper surface 214 of the substrate 210 and are located in the corresponding substrate units 2?. In one embodiment, the first wafers 22 can be electrically connected to the corresponding substrate units 211 by wire bonding or overlay a or the like. Specifically, the size of the first wafers 220 may be close to the size of the substrate units 211 and may be a wafer size package. • Referring to FIG. 3C, a mold 23 is disposed on the upper surface 214 of the substrate 21, and the mold 230 has an I-shaped mold cavity 231, and the two sides of the mold cavity 23 1 are The condensed mold flow restricting portion 232 is configured to reduce the width of the mold flow on the edge regions 213. In this embodiment, the mold flow restricting portions 232 protrude laterally in the I-shaped mold cavity 231 toward the first wafer 22, thereby occupying the mold flow space on the edge regions 213. In order to reduce the gap between the mold flow restricting portions 232 φ and the opposing first wafers 220, the effect of reducing the width of the side mold flow can be achieved. In this embodiment, referring to FIG. 5, the mold 230 can have a plurality of gates 233 on the same side, and the mold flow restricting portions 232 are relatively close to the side where the gates 233 are provided. side. In detail, the gates 233 are connected to a flow path of the runner and the I-shaped mold cavity 23 1 in a feeding system. In addition, the mold flow restricting portions 232 may be offset in the I-shaped mold cavity 231, so that the I-shaped mold writing 231 is formed on the side away from the gates 233 to be relatively open. The mold flow 201128718 buffer side 234, so it can provide a buffer space to reduce the occurrence of the return phenomenon or make the return packet phenomenon not formed on the package units. The shape of the I-shaped mold cavity 231 does not affect the arrangement space of the zipper ports 233.
請參閱第3D圖所示，形成一模封膠體24〇於該基板 210之該上表面214’由該些注澆口 233灌注未固化前之 模封膠體240時，藉由該些模流限制部232限制該模封 膠體240在該些邊緣區213上之流量，以改善回包現象， 使該模封膠體240覆蓋該基板21〇包含該些基板單元2ΐι 之該上表面214並密封該些第一晶片22〇。具體而言， 在此步驟中，Ιϋ由一模壓機擠壓注入該模封膠體至該 模具230内，以充填該工字型模窩231。在本實施例中， 該模封膠體240係可為一環氧樹脂（Ep〇xy则⑻叫 compound’ EMC)，可作為包覆該些第一晶片22〇的材 料，以提供適當的機械、電性以及熱傳性f並保護該些 第一晶片220不受外界環境的干擾。 在本發明中，可藉由模且之工空别财办 棋再之工予型模窩之特定組合關 係作為其中-技術手段’由於該工字型模离231之兩側 係内縮為兩對稱之模流限制部232，並藉由該些模流限 制部232限制該模封膠體240名兮| 。，八 m Z4U在該基板210之該些邊緣 區213上之流量。因此，玎奸M ^ U此可改善回包現象（Air trai effect)，並能有效改善外顴 Γ規不艮問題，進而提升生產良 率。如第4圖所示，其為太麻 兵馮本發明之陣列模封方法繪示形 成模封膠體之過程的上箱千咅固 低J上硯不意圖。因為該些基板單元21: 201128718 上設置有該些第一晶片220,導致流經該些基板單元211 上之模流速度減慢，但由於該些模流限制部232限制了 兩側之邊緣區2 1 3上之模流空間，使得流經該些邊緣區 213上之模流速度與流量降低，故該模封膠體240流經 該些基板單元211上之模流速度與該些邊緣區213上之 模流速度能較為接近，在灌入該模封膠體240之後，該 模封膠體240能順利地填滿該些基板單元2 11上的模封 鲁 空間，亦可避免在該模封膠體240内產生空洞之情況。 特別是，上述被減縮在兩側邊緣區2 1 3上的模流寬度 係可不大於該些第一晶片220之間的模流寬度，故該模 封膠體240於該些第一晶片22〇之間的流量係可稍較大 於該模封膠體240於該些邊緣區213上的流量。由於該 模封膠體240在流經該些第一晶片220之間時，會受到 該些第一晶片220之阻礙而降低流速，但因為該模封膠 體240於該些第一晶片22〇之間具有稍微較大的流量， 鲁相對地該些模流限制部232限制了該模封膠體240之流 動路徑，因此通過該些第一晶片220之間與該些邊緣區 2 1 3之模流速度能較為接近’而能平穩地充滿於該工字 型模窩231内，以有效包覆該些第一晶片22〇。 請再參閱第3B圖所示，在本實施例中，每一第一晶 片220係可具有一對與模流方向平行之短邊22丨以及一 對與模流方向垂直之長邊222,該長邊222之長度係不 小於該短邊221之長度。具體而言，該些第一晶片22〇 之形狀係可為長方形’並且該些短邊221係平行鄰靠於 201128718 — 該些邊緣區213。由於本發明相對於習知的陣列模封方 法，重新變更了該些第一晶片22〇之設置位置，使得在 該些紐邊221與該些邊緣區213之間隙（即晶片至模穴之 間隙）以及兩相鄰之該些短邊221之間隙（即晶片與晶片 之間的間隙）更加縮小，並且由於該些短邊221係較短於 該些長邊222，使得該模封膠體24〇所需通過該些第一 曰曰片220上之路徑更為縮短，故具有上述改善回包現象 之增進功效。 本發明還揭不一種陣列模封之模具23〇舉例說明於 第5圖該陣列模封之模具230，係具有一工字型模窩 23卜該工字型模窩231之兩侧係内縮為對稱之模流限制 部232，用以減縮一基板21〇之兩側邊緣區213上的模 流寬度（如第3C圖所示）。詳細而言，該模具23〇係可具 有複數個位於同一側邊之注澆口 233，該些模流限制部 232係相對靠近設有該些注澆口 233之侧邊。其中，該 籲些/主澆口 233之深度係不大於該工字型模窩231之深 度此外’上述被減縮在兩側邊緣區2 1 3上的模流寬度 係可不大於在該基板21〇之切割道212上晶片間隙的模 流寬度（請參酌第3C圖所示）。在一較佳實施例中，該模 具230之材質係可選用金屬材料，例如：鋼、銅、鋁等。 依據本發明之一變化實施例，主要應用該陣列模封方 法並進一步達到多晶片堆疊封裝之模封製程，舉例說明 於第6A至6C圖。在本實施例中，所揭示之步驟係可接 續於上述設置該些第一晶片22〇於該基板21〇之該上表 10 201128718 面214之後，故該些第一晶片220係與該基板21〇完成 連接關係。其中相同的主要元件將以相同符號標示，不 再祥予贅述。 請參閱第6A圖所示’在設置該些第一晶片22〇於該 基板210上之後，可另設置複數個第二晶片250於該些 第一晶片220上。具體而言’該些第二晶片250與該些 第一晶片220係可為相同尺寸與功能之半導體晶片，其 係已形成積體電路（integrated circuit，1C)並由一晶圓 ® (wafer)分割而成。其中’可另設置有複數個黏晶層（圖中 未繪出）於該些第二晶片250與該些第一晶片220之間， 以使得該些第二晶片250立體堆疊於該些第一晶片220 之上。在一較佳實施例中，該些第一晶片220與該些第 二晶片250係可形成有複數個矽穿孔（ThroUgh Silicon Via，TSV圖中未繪出），以垂直貫通方式達成該基板 210、該些第一晶片220與該些第二晶片250之電性導 • 通，故基板上方可堆疊更多晶片。 請參閱第6B圖所示，設置該模具230於該基板210 之該上表面214。在本實施例中，因為該些第一晶片220 上堆疊該些第二晶片250，該工字型模窩231内在晶片 上方的模流空間更為減小。然而，由於該工字型模窩23 1 之該些模流限制部232，能夠減縮該些邊緣區2 1 3上的 模流寬度’同樣能達到模流平衡之作用。 請參閱第6C圖所示，形成一模封膠體240於該基板 210之該上表面214，使得該模封膠體240覆蓋該基板 201128718 - 210之該上表面214並密封該些第一晶片220與該些第 二晶片250，而可形成為多層晶片封裝（MCp Assemble)。 較佳地，在灌注未固化之模封膠體24〇時，藉由該些模 流限制部232限制該模封膠體24〇在該些邊緣區213上 之流量，即使在該模具230内堆疊了更多數量的晶片， 依然能夠有效地改善回包現象，並避免因回包現象所產 生之種種不良問題。 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，.雖然本發明已以較佳實施例 揭露如上’然而並非用以限定本發明，任何熟悉本項技 術者’在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修佛，均仍屬於本發明的技術範圍 内0 【圖式簡單說明】 圖為I知的陣列模封方法綠示其晶片設置於基板 # 之立體示意圖。 第2圖.為習知的陣列模封方法繪示其形成模封膠 基板時之上視示意圖。 、 第3A至圖：依據本發明之一具體實施例的一種陣列 模封方法中各步驟之元件立體示意圖。 依據本發明之一具體實施例的陣列模封方法繪 示其形成模封膠體於基板時之上視示意圖。、 依據本發明之一具體實施例的一種陣列模封模 具之立體示意圖。Referring to FIG. 3D, a mold encapsulant 24 is formed on the upper surface 214 ′ of the substrate 210 when the uncured pre-molding encapsulant 240 is filled by the gate 233, and the mold flow is restricted by the mold flow. The portion 232 limits the flow of the molding compound 240 on the edge regions 213 to improve the returning phenomenon, so that the molding compound 240 covers the substrate 21 and includes the upper surface 214 of the substrate units 2ΐ and seals the portions The first wafer 22 is. Specifically, in this step, the mold is pressed into the mold 230 by a molding machine to fill the I-shaped mold cavity 231. In this embodiment, the molding compound 240 can be an epoxy resin (Ep〇xy (8) is called compound 'EMC), which can be used as a material for coating the first wafers 22 to provide appropriate mechanical, Electrical and heat transfer properties f and protect the first wafers 220 from external environment. In the present invention, the specific combination relationship of the mold cavity can be used as a technical means by the mold and the work of the work, and the two sides of the I-shaped mold separation 231 are reduced to two. The symmetrical mold flow restricting portion 232, and the mold sealing body 240 is restricted by the mold flow restricting portion 232. , the flow rate of the eight m Z4U on the edge regions 213 of the substrate 210. Therefore, the rape of M ^ U can improve the Air trai effect, and can effectively improve the problem of foreign law and regulations, thereby improving production yield. As shown in Fig. 4, it is the array sealing method of the invention of the invention. The upper case of the process of forming the mold sealing body is not intended. Because the first wafers 220 are disposed on the substrate units 21: 201128718, the velocity of the mold flowing through the substrate units 211 is slowed, but the edge regions of the two sides are limited by the mold flow restricting portions 232. The mold flow space on the 2 1 3 is such that the mold flow velocity and the flow rate flowing through the edge regions 213 are reduced, so that the mold flow speed of the mold seal body 240 flowing through the substrate units 211 and the edge regions 213 The upper mold flow speed can be relatively close. After filling the mold seal body 240, the mold seal body 240 can smoothly fill the mold seal space on the substrate units 2 11 and can also avoid the mold sealant. A cavity is created in 240. In particular, the width of the mold flow reduced on the side edge regions 2 1 3 may not be greater than the width of the mold flow between the first wafers 220, so that the molding compound 240 is disposed on the first wafers 22 The flow rate between the two can be slightly larger than the flow rate of the molding compound 240 on the edge regions 213. Since the molding compound 240 is blocked by the first wafers 220 while flowing between the first wafers 220, the flow rate is lowered, because the molding compound 240 is between the first wafers 22 With a slightly larger flow rate, the mold flow restricting portions 232 restrict the flow path of the molding compound 240, and thus the mold flow velocity between the first wafers 220 and the edge regions 2 1 3 The material can be relatively close to and can be smoothly filled in the I-shaped mold cavity 231 to effectively coat the first wafers 22〇. Referring to FIG. 3B again, in the embodiment, each of the first wafers 220 may have a pair of short sides 22 平行 parallel to the direction of the mold flow and a pair of long sides 222 perpendicular to the direction of the mold flow. The length of the long side 222 is not less than the length of the short side 221 . Specifically, the first wafers 22A may be in the shape of a rectangle ‘and the short sides 221 are parallel to the 201128718—the edge regions 213. Since the present invention re-changes the positions of the first wafers 22 to the gaps between the edge portions 213 (ie, the gap between the wafers and the cavity), compared to the conventional array molding method. And the gap between the two adjacent short sides 221 (i.e., the gap between the wafer and the wafer) is further reduced, and since the short sides 221 are shorter than the long sides 222, the molding compound 24〇 The path required to pass through the first cymbals 220 is further shortened, so that the above-mentioned improved returning phenomenon is enhanced. The present invention also discloses an array-molded mold 23, which is illustrated in FIG. 5, the array-molded mold 230 has an I-shaped mold cavity 23 and the two sides of the I-shaped mold cavity 231 are retracted. The symmetrical mold flow restricting portion 232 is for reducing the width of the mold flow on the side edge regions 213 of the substrate 21 (as shown in FIG. 3C). In detail, the mold 23 can have a plurality of gates 233 on the same side, and the mold flow restricting portions 232 are relatively close to the side edges of the gates 233. Wherein, the depth of the portion/main gate 233 is not greater than the depth of the I-shaped mold cavity 231. Further, the width of the mold flow reduced on the side edge regions 2 1 3 may be no greater than that on the substrate 21 . The mold flow width of the wafer gap on the scribe line 212 (please refer to Figure 3C). In a preferred embodiment, the material of the mold 230 is made of a metal material such as steel, copper, aluminum or the like. According to a variant embodiment of the invention, the array sealing method is mainly applied and the molding process of the multi-wafer stack package is further achieved, as illustrated in Figs. 6A to 6C. In this embodiment, the steps are performed after the first wafer 22 is disposed on the upper surface 10 of the substrate 21, and the first wafer 220 is connected to the substrate 21. 〇 Complete the connection relationship. The same main components will be denoted by the same symbols and will not be described again. Referring to FIG. 6A, after the first wafers 22 are disposed on the substrate 210, a plurality of second wafers 250 may be additionally disposed on the first wafers 220. Specifically, the second wafers 250 and the first wafers 220 can be semiconductor chips of the same size and function, which have formed an integrated circuit (1C) and are made of a wafer® (wafer). Split into. Wherein, a plurality of adhesive layers (not shown) may be disposed between the second wafers 250 and the first wafers 220 such that the second wafers 250 are stereoscopically stacked on the first ones. Above the wafer 220. In a preferred embodiment, the first wafers 220 and the second wafers 250 may be formed with a plurality of turns (ThroUgh Silicon Via, not shown in the TSV) to achieve the substrate 210 in a vertical through manner. The first wafers 220 and the second wafers 250 are electrically conductive, so that more wafers can be stacked above the substrate. Referring to FIG. 6B, the mold 230 is disposed on the upper surface 214 of the substrate 210. In this embodiment, because the second wafers 250 are stacked on the first wafers 220, the mold flow space above the wafers in the I-shaped mold cavity 231 is further reduced. However, due to the mold flow restricting portions 232 of the I-shaped mold cavity 23 1 , the mold flow width ‘ on the edge regions 2 1 3 can be reduced to achieve the effect of the mold flow balance. Referring to FIG. 6C, a molding compound 240 is formed on the upper surface 214 of the substrate 210 such that the molding compound 240 covers the upper surface 214 of the substrate 201128718-210 and seals the first wafers 220. The second wafers 250 can be formed as a multilayer chip package (MCp Assemble). Preferably, when the uncured molding compound 24 is filled, the flow of the molding compound 24 on the edge regions 213 is restricted by the mold flow restricting portions 232 even if stacked in the mold 230. A larger number of wafers can still effectively improve the returning phenomenon and avoid the various problems caused by the returning phenomenon. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, however, it is not intended to limit the invention. Any simple modification, equivalent change, and modification made by the skilled person within the technical scope of the present invention are still within the technical scope of the present invention. [Simplified description of the drawing] The sealing method green shows a schematic view of the wafer disposed on the substrate #. Fig. 2 is a top plan view showing a conventional array molding method for forming a molding substrate. 3A to 3D is a perspective view showing the components of each step in the array sealing method according to an embodiment of the present invention. An array molding method according to an embodiment of the present invention shows a top view of a mold encapsulant formed on a substrate. A perspective view of an array of molding dies according to an embodiment of the present invention.
LSI 12 201128718 一 第6A至6C圖：依據本發明之一變化實施例的一種陣列 模封方法中各步驟之元件立體示意圖。 【主要元件符號說明】 110 基板 111 基板 單 元 112 切 割 道 113 邊 緣 區 114 上表 面 120 晶片 130 模 具 140 模 封 膠體 210 基板 211 基板 單 元 212 切 割 道 213 邊 緣 區 214 上表 面 220 第一 晶 片 221 長 邊 222 短 邊 230 模具 23 1 工字 型 模窩 232 模 流 限制部 233 注 洗 a 234 模流 緩 衝側 240 模封 膠 體 250 第 _ - 晶片LSI 12 201128718 A 6A to 6C is a perspective view showing the components of each step in the array sealing method according to a variant embodiment of the present invention. [Main component symbol description] 110 substrate 111 substrate unit 112 dicing street 113 edge region 114 upper surface 120 wafer 130 mold 140 molding compound 210 substrate 211 substrate unit 212 dicing street 213 edge region 214 upper surface 220 first wafer 221 long side 222 Short side 230 Mold 23 1 I-shaped mold cavity 232 Mold flow restricting part 233 Note a 234 Mold buffer side 240 Molding paste 250 No. _ - Wafer
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