TWI480986B - Semiconductor package and method of forming same - Google Patents
Semiconductor package and method of forming same Download PDFInfo
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- TWI480986B TWI480986B TW101131510A TW101131510A TWI480986B TW I480986 B TWI480986 B TW I480986B TW 101131510 A TW101131510 A TW 101131510A TW 101131510 A TW101131510 A TW 101131510A TW I480986 B TWI480986 B TW I480986B
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
本發明係有關於一種半導體封裝件及其製法，尤指一種具有導熱金屬層之半導體封裝件及其製法。The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a thermally conductive metal layer and a method of fabricating the same.
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發體積微小、高性能、高功能、與高速度化的半導體封裝件，藉以符合電子產品之要求。With the advancement of the times, today's electronic products are developing towards miniaturization, multi-function, high-power and high-speed operation. In order to cope with this development trend, the semiconductor industry is not actively developing small size, high performance, high function, and high. Speed-oriented semiconductor packages to meet the requirements of electronic products.
一般半導體封裝件需要接置散熱件，以保持半導體晶片之正常作動，如第1至3圖所示，係各種習知之具有散熱件之半導體封裝件之剖視圖。In general, a semiconductor package requires a heat sink to be attached to maintain normal operation of the semiconductor wafer. As shown in FIGS. 1 to 3, there are various cross-sectional views of a conventional semiconductor package having a heat sink.
第1圖所示者係將一散熱片11設置於封裝基板10上，之後再進行包覆封裝膠體12，並使該散熱片11之頂面外露。In the first embodiment, a heat sink 11 is placed on the package substrate 10, and then the encapsulant 12 is covered, and the top surface of the heat sink 11 is exposed.
第2圖所示者係於半導體晶片21接置於封裝基板20後，先形成封裝膠體22，再於該封裝膠體22上貼設有一散熱片23。In the second embodiment, after the semiconductor wafer 21 is placed on the package substrate 20, the encapsulant 22 is formed, and a heat sink 23 is attached to the encapsulant 22.
第3圖所示者係於半導體晶片31接置於封裝基板30後，堆疊置放一大一小的矽材質之虛設晶粒(dummy die)32於該半導體晶片31上，由於矽(Si)亦為不錯之導熱材料，故以此取代一般之金屬散熱片。As shown in FIG. 3, after the semiconductor wafer 31 is placed on the package substrate 30, a dummy die 32 of a large and small germanium material is stacked on the semiconductor wafer 31 due to germanium (Si). It is also a good thermal conductive material, so it replaces the general metal heat sink.
惟，前述習知之散熱方式仍有如下之缺點：However, the aforementioned conventional heat dissipation methods still have the following disadvantages:
1.散熱件離半導體晶片太遠，故散熱效果不佳。(如 第1或2圖所示)1. The heat sink is too far away from the semiconductor wafer, so the heat dissipation effect is not good. (Such as Figure 1 or 2)
2.將散熱件貼附於半導體晶片或封裝膠體上，增加半導體封裝件之整體厚度。(如第1、2或3圖所示)2. Attach the heat sink to the semiconductor wafer or the encapsulant to increase the overall thickness of the semiconductor package. (as shown in Figures 1, 2 or 3)
3.散熱件或虛設晶粒須逐一對位並貼附於半導體晶片或封裝膠體上，其產出率(throughput)低，故產品之生產速度慢。(如第1或3圖所示)3. The heat sink or the dummy die must be attached to the semiconductor wafer or the encapsulant on a one-by-one basis, and the throughput is low, so the production speed of the product is slow. (as shown in Figure 1 or 3)
因此，如何避免上述習知技術中之種種問題，並解決半導體封裝件之散熱效果不佳、厚度過大以及生產速度較慢等缺失，實已成為目前亟欲解決的課題。Therefore, how to avoid various problems in the above-mentioned prior art, and to solve the lack of heat dissipation effect, excessive thickness, and slow production speed of the semiconductor package has become a problem to be solved at present.
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：基板本體，係具有相對之第一表面與第二表面，該基板本體中設有導熱金屬路徑，且該第二表面具有連接該導熱金屬路徑的散熱墊；半導體晶片，係接置於該基板本體之第一表面上，且藉由打線方式電性連接該基板本體；圖案化之導熱金屬層，係形成於該基板本體之第一表面及半導體晶片之頂面與側面上，且連接該導熱金屬路徑；以及封裝膠體，係形成於該基板本體之第一表面上，以包覆該半導體晶片。In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor package comprising: a substrate body having opposite first and second surfaces, wherein the substrate body is provided with a thermally conductive metal path, and the second surface a heat dissipating pad connected to the thermally conductive metal path; the semiconductor wafer is attached to the first surface of the substrate body, and electrically connected to the substrate body by wire bonding; and the patterned thermally conductive metal layer is formed on the substrate The first surface of the body and the top surface and the side surface of the semiconductor wafer are connected to the thermally conductive metal path; and the encapsulant is formed on the first surface of the substrate body to encapsulate the semiconductor wafer.
本發明提供另一種半導體封裝件，係包括：導線架；半導體晶片，係接置於該導線架之一表面上，且藉由打線方式電性連接該導線架；圖案化之導熱金屬層，係形成於該導線架之該表面及半導體晶片之頂面與側面上；以及封裝膠體，係形成於該導線架之該表面上，以包覆該半導體 晶片。The present invention provides another semiconductor package, comprising: a lead frame; a semiconductor wafer attached to a surface of the lead frame and electrically connected to the lead frame by wire bonding; a patterned thermally conductive metal layer Formed on the surface of the lead frame and the top surface and the side surface of the semiconductor wafer; and an encapsulant formed on the surface of the lead frame to encapsulate the semiconductor Wafer.
本發明復提供一種半導體封裝件之製法，係包括：於一基板本體之第一表面上接置半導體晶片，該基板本體具有相對該第一表面之第二表面；於該基板本體之第一表面及半導體晶片之頂面與側面上形成圖案化之導熱金屬層，該導熱金屬層係藉由該基板本體中之導熱金屬路徑連接該第二表面之散熱墊；以打線方式電性連接該半導體晶片與該基板本體；以及於該基板本體之第一表面上形成包覆該半導體晶片的封裝膠體。The invention provides a method for fabricating a semiconductor package, comprising: connecting a semiconductor wafer on a first surface of a substrate body, the substrate body having a second surface opposite to the first surface; and a first surface of the substrate body And forming a patterned thermally conductive metal layer on the top surface and the side surface of the semiconductor wafer, wherein the thermally conductive metal layer is connected to the heat dissipating pad of the second surface by a thermally conductive metal path in the substrate body; electrically connecting the semiconductor wafer by wire bonding And the substrate body; and forming an encapsulant covering the semiconductor wafer on the first surface of the substrate body.
本發明復提供另一種半導體封裝件之製法，係包括：於一導線架之一表面上接置半導體晶片；於該導線架之該表面及半導體晶片之頂面與側面上形成圖案化之導熱金屬層；以打線方式電性連接該半導體晶片與該導線架；以及於該導線架之該表面上形成包覆該半導體晶片的封裝膠體。The invention provides a method for fabricating another semiconductor package, comprising: connecting a semiconductor wafer on a surface of a lead frame; forming a patterned heat conductive metal on the surface of the lead frame and the top surface and the side surface of the semiconductor wafer; a layer; electrically connecting the semiconductor wafer and the lead frame in a wire bonding manner; and forming an encapsulant covering the semiconductor wafer on the surface of the lead frame.
由上可知，因為本發明係將導熱金屬層直接形成在半導體晶片上，故可有效地將熱迅速地傳導至外界；此外，該導熱金屬層之厚度遠較習知之散熱件還薄，所以可大幅縮減整體厚度；又，本發明之導熱金屬層能一次在未切單之大版面的複數半導體封裝件上同時形成，因此整體產出率遠較習知技術來得高。As can be seen from the above, since the present invention directly forms the thermally conductive metal layer on the semiconductor wafer, heat can be efficiently conducted to the outside world; in addition, the thickness of the thermally conductive metal layer is much thinner than conventional heat sinks, so The overall thickness is greatly reduced; in addition, the thermally conductive metal layer of the present invention can be simultaneously formed on a plurality of semiconductor packages of unscheduled large layouts, so that the overall yield is much higher than that of the prior art.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解 本發明之其他優點及功效。The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily understand the contents disclosed in the present specification. Other advantages and effects of the present invention.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「頂」、「側」、「圖案化」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "top", "side", "pattern" and "one" are used in this specification for convenience of description only, and are not intended to limit the invention. The scope of the invention, the change or adjustment of its relative relationship, is also considered to be within the scope of the invention.
第4A至4G圖所示者，係本發明之半導體封裝件及其製法之第一實施例的示意圖，其中，第4A至4F圖係俯視圖，第4G圖係剖視圖。4A to 4G are schematic views showing a first embodiment of the semiconductor package of the present invention and a method of manufacturing the same, wherein the 4A to 4F are plan views and the 4Gth is a cross-sectional view.
如第4A圖所示，提供一具有相對之第一表面40a與第二表面40b之基板本體40，該基板本體40之第一表面40a可選擇性地形成導熱孔或導熱槽400，或者，該基板本體40之第一表面40a可選擇性地形成有導熱墊(未圖示)，該基板本體40中設有連接該導熱槽400的導熱金屬路徑401(圖示於第4G圖)，該導熱金屬路徑401係可包括散熱金屬線路、散熱金屬孔或散熱金屬柱，該第二表面40b係具有連接該導熱金屬路徑401的散熱墊402(圖示於第4G 圖)。As shown in FIG. 4A, a substrate body 40 having a first surface 40a and a second surface 40b opposite to each other is provided. The first surface 40a of the substrate body 40 can selectively form a heat conducting hole or a heat conducting groove 400. The first surface 40a of the substrate body 40 is selectively formed with a thermal pad (not shown). The substrate body 40 is provided with a thermally conductive metal path 401 (shown in FIG. 4G) connecting the heat conducting slot 400. The metal path 401 may include a heat dissipating metal line, a heat dissipating metal hole or a heat dissipating metal post, and the second surface 40b has a heat dissipating pad 402 connected to the heat conducting metal path 401 (illustrated in the 4G Figure).
如第4B圖所示，於該基板本體40之第一表面40a上接置半導體晶片41。As shown in FIG. 4B, the semiconductor wafer 41 is attached to the first surface 40a of the substrate body 40.
如第4C圖所示，於該基板本體40之第一表面40a與該半導體晶片41上形成具有阻層開口420的阻層42，該阻層42可為感光性乾膜，且該阻層42係覆蓋該半導體晶片41之電極墊(未圖示)及其周緣，並覆蓋該基板本體40之銲墊(未圖示)及其周緣。As shown in FIG. 4C, a resist layer 42 having a resist opening 420 is formed on the first surface 40a of the substrate body 40 and the semiconductor wafer 41. The resist layer 42 may be a photosensitive dry film, and the resist layer 42 The electrode pad (not shown) of the semiconductor wafer 41 and its periphery are covered, and a pad (not shown) of the substrate body 40 and its periphery are covered.
如第4D圖所示，進行金屬濺鍍或電鍍步驟。As shown in Fig. 4D, a metal sputtering or plating step is performed.
如第4E圖所示，移除該阻層42，以於該基板本體40之第一表面40a及半導體晶片41之頂面與側面上定義出圖案化之導熱金屬層43，該導熱金屬層43係藉由該基板本體40中之導熱金屬路徑401連接該第二表面40b之散熱墊402。As shown in FIG. 4E, the resist layer 42 is removed to define a patterned thermally conductive metal layer 43 on the top surface 40a of the substrate body 40 and the top and sides of the semiconductor wafer 41. The thermally conductive metal layer 43 is formed. The thermal pad 402 of the second surface 40b is connected by a thermally conductive metal path 401 in the substrate body 40.
要補充說明的是，由於前述第4C至4E圖之方式雖對位精度較高，但所花費的成本也較高，故在該導熱金屬層43之對位精度之需求較低的情況下，為了降低整體成本，亦可改用下述之方式：先於該基板本體40之第一表面40a與該半導體晶片41之上方設置模板(未圖示)，且該模板具有對應該導熱金屬層43的模板開口(未圖示)，並進行濺鍍步驟，再移除該模板，且該模板可再重複使用。由於本替代方式係本發明所屬技術領域具有通常知識者依據本說明書而能瞭解者，故不在此加以圖示與說明。It should be noted that, since the method of the above 4C to 4E has a higher alignment accuracy, but the cost is also high, in the case where the demand for the alignment accuracy of the heat conductive metal layer 43 is low, In order to reduce the overall cost, a template (not shown) may be disposed on the first surface 40a of the substrate body 40 and above the semiconductor wafer 41, and the template has a conductive metal layer 43 corresponding thereto. The template is opened (not shown) and the sputtering step is performed, the template is removed, and the template can be reused. Since the present invention is known to those of ordinary skill in the art to which the present invention pertains, it will not be illustrated or described herein.
如第4F圖所示，以打線方式電性連接該半導體晶片 41之電極墊與該基板本體40之銲墊。As shown in FIG. 4F, the semiconductor wafer is electrically connected by wire bonding The electrode pad of 41 and the pad of the substrate body 40.
如第4G圖所示，於該基板本體40之第一表面40a上形成包覆該半導體晶片41的封裝膠體44，並於該散熱墊402上接置例如銲球的散熱元件45，且可藉由該散熱元件45將熱傳導至另一電路板(未圖示)上。As shown in FIG. 4G, an encapsulant 44 covering the semiconductor wafer 41 is formed on the first surface 40a of the substrate body 40, and a heat dissipating component 45 such as a solder ball is attached to the thermal pad 402. Heat is conducted by the heat dissipating element 45 to another circuit board (not shown).
第5A至5D圖所示者，係本發明之半導體封裝件及其製法之第二實施例的示意圖，本實施例之作法係大致相同於前一實施例，故在此僅進行簡單的說明。5A to 5D are schematic views of a second embodiment of the semiconductor package of the present invention and a method of manufacturing the same, and the embodiment of the present embodiment is substantially the same as the previous embodiment, and therefore, only a brief description will be made herein.
如第5A圖所示，於一導線架50之一表面上接置半導體晶片51。As shown in FIG. 5A, the semiconductor wafer 51 is attached to one surface of a lead frame 50.
如第5B圖所示，於該導線架50之該表面與該半導體晶片51上形成具有阻層開口520的阻層52，該阻層52可為感光性乾膜，且該阻層52係覆蓋該半導體晶片51之電極墊(未圖示)及其周緣，並覆蓋該導線架50之銲墊(未圖示)及其周緣。As shown in FIG. 5B, a resist layer 52 having a resist opening 520 is formed on the surface of the lead frame 50 and the semiconductor wafer 51. The resist layer 52 may be a photosensitive dry film, and the resist layer 52 is covered. An electrode pad (not shown) of the semiconductor wafer 51 and its periphery cover the pad (not shown) of the lead frame 50 and its periphery.
如第5C圖所示，進行金屬濺鍍或電鍍步驟。As shown in Fig. 5C, a metal sputtering or plating step is performed.
如第5D圖所示，移除該阻層52，以於該導線架50之該表面及半導體晶片51之頂面與側面上定義出圖案化之導熱金屬層53，並以打線方式電性連接該半導體晶片51與該導線架50，並於該導線架50之該表面上形成包覆該半導體晶片51的封裝膠體(未圖示)，最後，可視需要進行切割步驟。As shown in FIG. 5D, the resist layer 52 is removed to define a patterned thermally conductive metal layer 53 on the surface of the lead frame 50 and the top and side surfaces of the semiconductor wafer 51, and electrically connected by wire bonding. The semiconductor wafer 51 and the lead frame 50 form an encapsulant (not shown) covering the semiconductor wafer 51 on the surface of the lead frame 50. Finally, a cutting step can be performed as needed.
本發明復提供一種半導體封裝件，係包括：基板本體 40，係具有相對之第一表面40a與第二表面40b，該基板本體40中設有導熱金屬路徑401，該第二表面40b係具有連接該導熱金屬路徑401的散熱墊402；半導體晶片41，係接置於該基板本體40之第一表面40a上，且藉由打線方式電性連接該基板本體40；圖案化之導熱金屬層43，係形成於該基板本體40之第一表面40a及半導體晶片41之頂面與側面上，且連接該導熱金屬路徑401；以及封裝膠體44，係形成於該基板本體40之第一表面40a上，以包覆該半導體晶片41。The invention further provides a semiconductor package, comprising: a substrate body 40, having a first surface 40a opposite to the second surface 40b, the substrate body 40 is provided with a thermally conductive metal path 401, the second surface 40b having a heat dissipation pad 402 connecting the thermally conductive metal path 401; a semiconductor wafer 41, The substrate is disposed on the first surface 40a of the substrate body 40, and is electrically connected to the substrate body 40 by wire bonding. The patterned thermally conductive metal layer 43 is formed on the first surface 40a of the substrate body 40 and the semiconductor. The top surface and the side surface of the wafer 41 are connected to the heat conductive metal path 401; and the encapsulant 44 is formed on the first surface 40a of the substrate body 40 to cover the semiconductor wafer 41.
於本發明之半導體封裝件中，復包括導熱孔或導熱槽400，係形成於該基板本體40之第一表面40a，且該導熱金屬層43復形成於該導熱孔或導熱槽400中。In the semiconductor package of the present invention, a heat conducting hole or a heat conducting groove 400 is formed on the first surface 40a of the substrate body 40, and the heat conducting metal layer 43 is formed in the heat conducting hole or the heat conducting groove 400.
本發明復提供另一種半導體封裝件，係包括：導線架50；半導體晶片51，係接置於該導線架50之一表面上，且藉由打線方式電性連接該導線架50；圖案化之導熱金屬層53，係形成於該導線架50之該表面及半導體晶片51之頂面與側面上；以及封裝膠體，係形成於該導線架50之該表面上，以包覆該半導體晶片51。The present invention further provides another semiconductor package, comprising: a lead frame 50; a semiconductor wafer 51, which is attached to one surface of the lead frame 50, and electrically connected to the lead frame 50 by wire bonding; The heat conductive metal layer 53 is formed on the surface of the lead frame 50 and the top surface and the side surface of the semiconductor wafer 51; and an encapsulant is formed on the surface of the lead frame 50 to cover the semiconductor wafer 51.
綜上所述，相較於習知技術，由於本發明係將導熱金屬層直接形成在半導體晶片上，故可有效地將熱迅速地傳導至外界；此外，該導熱金屬層之厚度遠較習知之散熱件還薄，所以可大幅縮減整體厚度；又，本發明之導熱金屬層能一次在未切單之大版面的複數半導體封裝件上同時形成，因此整體產出率遠較習知技術來得高。In summary, compared with the prior art, since the present invention directly forms a thermally conductive metal layer on a semiconductor wafer, heat can be efficiently conducted to the outside world; in addition, the thickness of the thermally conductive metal layer is much higher than that of the conventional technology. It is known that the heat dissipating member is thin, so that the overall thickness can be greatly reduced. Moreover, the thermally conductive metal layer of the present invention can be simultaneously formed on a plurality of semiconductor packages of an uncut single layout, so that the overall yield is much higher than that of the prior art. high.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10、20、30‧‧‧封裝基板10, 20, 30‧‧‧ package substrate
11、23‧‧‧散熱片11, 23‧‧ ‧ heat sink
12、22、44‧‧‧封裝膠體12, 22, 44‧‧‧Package colloid
21、31、41、51‧‧‧半導體晶片21, 31, 41, 51‧‧‧ semiconductor wafers
32‧‧‧虛設晶粒32‧‧‧Virtual dies
40‧‧‧基板本體40‧‧‧Substrate body
40a‧‧‧第一表面40a‧‧‧ first surface
40b‧‧‧第二表面40b‧‧‧ second surface
400‧‧‧導熱槽400‧‧‧thermal bath
401‧‧‧導熱金屬路徑401‧‧‧thermal metal path
402‧‧‧散熱墊402‧‧‧Fast pad
42、52‧‧‧阻層42, 52‧‧ ‧ resistance layer
420、520‧‧‧阻層開口420, 520‧‧‧ barrier opening
43、53‧‧‧導熱金屬層43, 53‧‧‧ Thermal metal layer
45‧‧‧散熱元件45‧‧‧Heat components
50‧‧‧導線架50‧‧‧ lead frame
第1至3圖所示者係各種習知之具有散熱件之半導體封裝件之剖視圖；第4A至4G圖所示者，係本發明之半導體封裝件及其製法之第一實施例的示意圖，其中，第4A至4F圖係俯視圖，第4G圖係剖視圖；以及第5A至5D圖所示者，係本發明之半導體封裝件及其製法之第二實施例的示意圖。1 to 3 are cross-sectional views of various conventional semiconductor packages having heat sinks; and FIGS. 4A to 4G are schematic views showing a first embodiment of the semiconductor package of the present invention and a method of manufacturing the same, wherein 4A to 4F are plan views, and Fig. 4G is a cross-sectional view; and Figs. 5A to 5D are schematic views showing a second embodiment of the semiconductor package of the present invention and a method of manufacturing the same.
40‧‧‧基板本體40‧‧‧Substrate body
40a‧‧‧第一表面40a‧‧‧ first surface
40b‧‧‧第二表面40b‧‧‧ second surface
400‧‧‧導熱槽400‧‧‧thermal bath
401‧‧‧導熱金屬路徑401‧‧‧thermal metal path
402‧‧‧散熱墊402‧‧‧Fast pad
41‧‧‧半導體晶片41‧‧‧Semiconductor wafer
43‧‧‧導熱金屬層43‧‧‧thermal metal layer
44‧‧‧封裝膠體44‧‧‧Package colloid
45‧‧‧散熱元件45‧‧‧Heat components
Claims (12)
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| US20090104735A1 (en) * | 2005-12-14 | 2009-04-23 | Lsi Logic Corporation | Semiconductor package having increased resistance to electrostatic discharge |
| JP2011096830A (en) * | 2009-10-29 | 2011-05-12 | Toyota Motor Corp | Semiconductor device |
| TW201220444A (en) * | 2010-11-02 | 2012-05-16 | Global Unichip Corp | Semiconductor package device with a heat dissipation structure and the packaging method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20090104735A1 (en) * | 2005-12-14 | 2009-04-23 | Lsi Logic Corporation | Semiconductor package having increased resistance to electrostatic discharge |
| JP2011096830A (en) * | 2009-10-29 | 2011-05-12 | Toyota Motor Corp | Semiconductor device |
| TW201220444A (en) * | 2010-11-02 | 2012-05-16 | Global Unichip Corp | Semiconductor package device with a heat dissipation structure and the packaging method thereof |
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