JP2011096830A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011096830A
JP2011096830A JP2009248935A JP2009248935A JP2011096830A JP 2011096830 A JP2011096830 A JP 2011096830A JP 2009248935 A JP2009248935 A JP 2009248935A JP 2009248935 A JP2009248935 A JP 2009248935A JP 2011096830 A JP2011096830 A JP 2011096830A
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substrate
heat
semiconductor device
hole
semiconductor
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Atsushi Hiei
淳 比叡
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Toyota Motor Corp
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Toyota Motor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of at least reducing warpage of a substrate by suppressing a temperature change on upper and lower surfaces of the substrate due to heat generation in using the semiconductor device, and accordingly capable of effectively suppressing fatigue failure of a solder layer joining the substrate and a semiconductor package. <P>SOLUTION: In a semiconductor device 100, a semiconductor package 10 comprising a semiconductor element 1, a heat dissipation pad 3 and a sealing resin 7 for sealing the semiconductor element and the heat dissipation pad is joined to a substrate 8 via a solder layer 93. A through-hole 81 extending from one surface 8a facing the semiconductor package 10 to another surface 8b is formed at a position at least corresponding to the heat dissipation pad 3 in the substrate 8, and the through-hole 81 is closed with a heat conductive material having a relatively high thermal conductivity as compared with the substrate 8. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置に関し、より詳しくは、半導体装置使用時の発熱によって生じる少なくとも基板の反りを抑制ないしは低減し、もって基板と半導体パッケージを接合する半田層の疲労破壊や、基板の配線パターンの剥離を効果的に抑止することのできる、半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly, suppresses or reduces at least the warpage of a substrate caused by heat generation when the semiconductor device is used. The present invention relates to a semiconductor device capable of effectively suppressing peeling.

近年、電子機器製品の多機能化、高性能化および小型化に伴って、製品内部の半導体部品もその小型化が要求されており、半導体パッケージの半導体基板への高密度実装や、半導体パッケージ自体の高密度化が図られている。しかし、半導体パッケージの小型化(薄型化)や高密度化に伴い、半導体装置使用時の半導体パッケージの温度は上昇し、半導体パッケージや基板の上下面の温度差が大きくなる。特に剛性の高い基板の上下面の温度差が大きくなり、この温度差に起因して基板の変形(反り)が大きくなると、基板と半導体パッケージを繋ぐ半田層を剥離させる等、半導体装置が故障に至り得るという問題が顕在化しており、当該分野における重要な解決課題の一つである。   In recent years, with the increase in functionality, performance, and miniaturization of electronic product products, there is a demand for miniaturization of semiconductor components inside the product. High-density mounting of a semiconductor package on a semiconductor substrate and the semiconductor package itself Densification is attempted. However, with the miniaturization (thinning) and high density of the semiconductor package, the temperature of the semiconductor package when the semiconductor device is used increases, and the temperature difference between the upper and lower surfaces of the semiconductor package and the substrate increases. In particular, when the temperature difference between the upper and lower surfaces of a highly rigid substrate increases and the deformation (warpage) of the substrate increases due to this temperature difference, the semiconductor device may fail, such as peeling off the solder layer that connects the substrate and the semiconductor package. This is one of the important solutions in this field.

ところで、半導体パッケージの小型化(薄型化)に伴い、近年市場に導入されているのが、リードレスタイプの表面実装型半導体パッケージであり、BGAパッケージ(Ball Grid Array)やCSP(Clip Size Package)がその例である。表面実装型パッケージは、電極端子の一部もしくは全部を樹脂中に封止させずに半導体パッケージの底面や側面に露出させ、もってリード線を出さないので実装面積を縮小することができる。   By the way, along with the downsizing (thinning) of semiconductor packages, leadless type surface mount semiconductor packages have recently been introduced into the market, such as BGA packages (Ball Grid Array) and CSPs (Clip Size Packages). Is an example. In the surface mount type package, part or all of the electrode terminals are not sealed in the resin, but are exposed on the bottom and side surfaces of the semiconductor package, and lead wires are not taken out, so that the mounting area can be reduced.

また、半導体パッケージの放熱性向上の観点から、基板への実装面に放熱板を備えた構成の半導体パッケージが近年導入されている。より具体的には、放熱板の機能を有するダイパッド(放熱性パッド)の一部を樹脂中に封止させずに露出させる構造のものや、別体の放熱板を内蔵する構造のものなどがあり、放熱板を有していることで放熱性が良好となり、発熱量の多い半導体素子を搭載する場合に好適である。   Further, from the viewpoint of improving the heat dissipation of the semiconductor package, a semiconductor package having a structure in which a heat sink is provided on the mounting surface of the substrate has been recently introduced. More specifically, there is a structure in which a part of a die pad (heat dissipating pad) having a function of a heat sink is exposed without being sealed in a resin, or a structure in which a separate heat sink is built in. In addition, having a heat dissipation plate improves heat dissipation and is suitable for mounting a semiconductor element that generates a large amount of heat.

上記するリードレスタイプであり、かつ、放熱性パッドの一部が露出された構造の半導体パッケージが基板に実装された、半導体装置の一実施例を、図8,9に示している。なお、図8はその縦断面図であり、図9は図8のIX−IX矢視図である。   FIGS. 8 and 9 show an embodiment of a semiconductor device in which a semiconductor package of the leadless type described above and having a structure in which a part of the heat dissipating pad is exposed is mounted on a substrate. 8 is a longitudinal sectional view thereof, and FIG. 9 is a view taken along arrow IX-IX in FIG.

図8,9において、半導体素子aは、導電性接着剤などのダイボンディング材bによって接合された姿勢で放熱性パッドc上に搭載され、電極d1,d2(最外周側がd1)と導線eによって電気的に接続されている。さらに、放熱性パッドcおよび電極d1、d2双方の一部が露出するように、半導体素子a、放熱性パッドc、電極d1、d2および導線eが一体に封止樹脂体fにて封止され、半導体パッケージPが形成される。この半導体パッケージPにおける、放熱性パッドcと電極d1、d2双方の露出部分と、基板gとが、半田層hによって接合されることにより、半導体装置Hが形成される。   8 and 9, a semiconductor element a is mounted on a heat-dissipating pad c in a posture bonded by a die bonding material b such as a conductive adhesive, and electrodes d1, d2 (the outermost peripheral side is d1) and a conductive wire e. Electrically connected. Further, the semiconductor element a, the heat dissipating pad c, the electrodes d1, d2, and the conductive wire e are integrally sealed with the sealing resin body f so that a part of both the heat dissipating pad c and the electrodes d1, d2 are exposed. A semiconductor package P is formed. In this semiconductor package P, the exposed portion of both the heat dissipating pad c and the electrodes d1, d2 and the substrate g are joined by the solder layer h, whereby the semiconductor device H is formed.

ところで、図8,9に示されるような従来の半導体装置Hにおいては、半導体装置Hの使用時に半導体素子aから発生する熱で基盤gの上下面の温度差が生じ、それにともなって、基板gの上下面の膨張差が変化することから、基盤gの反りが発生することが知られている。   By the way, in the conventional semiconductor device H as shown in FIGS. 8 and 9, the temperature difference between the upper and lower surfaces of the substrate g is generated by the heat generated from the semiconductor element a when the semiconductor device H is used, and accordingly, the substrate g It is known that warping of the base g occurs because the difference in expansion between the upper and lower surfaces changes.

つまり、図8のように、半導体パッケージPの略中央位置に半導体素子aが配された半導体パッケージPにおいては、基板gが、基板gの半導体素子a側に凸であって、半導体素子aから離れた位置の電極d1、d2付近で半導体パッケージPに対して反対側に反る変形モード(図8の一点鎖線)を呈する。   That is, as shown in FIG. 8, in the semiconductor package P in which the semiconductor element a is disposed at a substantially central position of the semiconductor package P, the substrate g is convex toward the semiconductor element a side of the substrate g. A deformation mode (a chain line in FIG. 8) that warps in the opposite direction with respect to the semiconductor package P in the vicinity of the electrodes d1 and d2 at the separated positions.

この変形モードにより、半導体パッケージPの外周に配された電極d1、d2と基板gを繋ぐ半田層hに剪断力や引張力が作用して、半田層hに剥離や亀裂が生じ易くなり、あるいは、基板gの配線パターンが剥離し易くなってしまう。   By this deformation mode, a shearing force or a tensile force acts on the solder layer h connecting the electrodes d1 and d2 disposed on the outer periphery of the semiconductor package P and the substrate g, and the solder layer h is likely to be peeled off or cracked. The wiring pattern of the substrate g is easily peeled off.

上記する種々の課題を解決する発明技術の一つとして、特許文献1に開示の半導体装置を挙げることができる。この半導体装置は、半導体パッケージを実装する基板に貫通孔を備え、この貫通孔は半導体パッケージに対応した位置に配されているので、半導体装置使用時において発生する熱を貫通孔を通して基板の裏面(半導体パッケージの実装面と反対の面)に排熱することにより、基板の反りを抑制することができる。   As one of the invention techniques for solving the various problems described above, a semiconductor device disclosed in Patent Document 1 can be cited. Since this semiconductor device includes a through hole in a substrate on which a semiconductor package is mounted, and this through hole is arranged at a position corresponding to the semiconductor package, heat generated when the semiconductor device is used is transferred to the back surface of the substrate through the through hole ( By exhausting heat to the surface opposite to the mounting surface of the semiconductor package, warping of the substrate can be suppressed.

特開2003−297965号公報JP 2003-297965 A

特許文献1に開示の半導体装置は、ガラス−エポキシ基板の表面に、パワーデバイスを収容した半導体パッケージが、半田層を介して接続されたものである。また、半導体パッケージの実装面には銅製の放熱板が埋設され、放熱板の一部が半導体パッケージの実装面に露出している。更に、この基板には、半導体パッケージが実装される範囲に複数の貫通孔が、縦横にほぼ等間隔で(格子状に)整列配置されている。そして、各々の貫通孔にはホール導電体が配設され、各ホール導電体は、貫通孔の内壁を覆う筒部と、筒部の一端に続いて基板の表面(半導体パッケージが実装される面)に拡がる環状の第一平面部と、筒部の他端に続いて基板の裏面に拡がる環状の第二平面部とを備えている。この基板に設けられたホール導電体は、典型的には金属材料を主体に構成されており、その金属材料としては熱伝導率の高い材料が適していて、例えば、銅、銀、金、白金、ニッケル、コバルト、亜鉛等の純金属、及び、それらを含む合金が好ましく使用される。このように、熱伝導率の高いホール導電体が基板の裏面側まで延びていることによって、半導体パッケージから生じる熱を基板の裏面側へ逃がす効果が得られる。   In the semiconductor device disclosed in Patent Document 1, a semiconductor package containing a power device is connected to the surface of a glass-epoxy substrate via a solder layer. Also, a copper heat sink is embedded in the mounting surface of the semiconductor package, and a part of the heat sink is exposed on the mounting surface of the semiconductor package. Further, on this substrate, a plurality of through holes are aligned and arranged at substantially equal intervals in a vertical and horizontal direction (in a lattice pattern) in a range where the semiconductor package is mounted. Each through hole is provided with a hole conductor, and each hole conductor has a cylindrical portion covering the inner wall of the through hole, and one end of the cylindrical portion, followed by the surface of the substrate (the surface on which the semiconductor package is mounted). And an annular first flat surface portion extending to the back surface of the substrate following the other end of the cylindrical portion. The hole conductor provided in this substrate is typically composed mainly of a metal material, and a material with high thermal conductivity is suitable as the metal material, for example, copper, silver, gold, platinum Pure metals such as nickel, cobalt and zinc, and alloys containing them are preferably used. As described above, the hole conductor having high thermal conductivity extends to the back surface side of the substrate, so that an effect of releasing heat generated from the semiconductor package to the back surface side of the substrate can be obtained.

上記の構成において、貫通孔の位置を最適化することにより、半導体装置使用時における、半導体パッケージと基板の間に篭もる熱を貫通孔及び導電体を介して基板の裏面側に放熱することができ、もって、基板と半導体パッケージの反りを低減して、半田層の接合不良を抑制することができる。また、貫通孔を設けることにより、半導体素子から発生した熱による基板の熱膨張を貫通孔の中空部が吸収可能となるため、貫通孔がない場合と比較して、相対的に変形量を抑制することができるという効果を奏することもできる。   In the above configuration, by optimizing the position of the through hole, the heat trapped between the semiconductor package and the substrate is dissipated to the back side of the substrate through the through hole and the conductor when the semiconductor device is used. Therefore, the warpage between the substrate and the semiconductor package can be reduced, and the bonding failure of the solder layer can be suppressed. In addition, by providing a through hole, the hollow portion of the through hole can absorb the thermal expansion of the substrate due to the heat generated from the semiconductor element, so that the amount of deformation is relatively suppressed compared to the case without the through hole. The effect that it can be done can also be produced.

しかし、ガラス−エポキシ基板やホール伝導体と比較して、中空の導電体内に存在する空気は相対的に熱伝導率が低く、放熱性を低下させる要因となりかねない。たとえば、基板に使用されるエポキシ樹脂の熱伝導率が0.21W/mK、引用文献1のホール導電体の例として挙げられている銅の熱伝導率が398W/mKであるのに対して、空気の熱伝導率は、0.024W/mK程度であり、空気の熱伝導性能は極めて低いものである。   However, compared to glass-epoxy substrates and hole conductors, air present in hollow conductors has a relatively low thermal conductivity, which can be a factor in reducing heat dissipation. For example, the thermal conductivity of the epoxy resin used for the substrate is 0.21 W / mK, whereas the thermal conductivity of copper cited as an example of the hole conductor in the cited document 1 is 398 W / mK, The thermal conductivity of air is about 0.024 W / mK, and the thermal conductivity of air is extremely low.

また、空気の流動性を生かして、例えば、半導体装置の外部からの働きかけによって空気を対流させ、半導体パッケージと基板の間に篭もる熱を強制的に排熱する対策も考えられるが、通常、上記の熱が篭もる部位は空気だまりの形状となっており、外部からの働きかけによって強制的に排熱しようとしても、空気の対流が不十分であるために排熱も不完全となる。   In addition, taking advantage of the fluidity of air, for example, it is possible to consider a measure to convect air by acting from the outside of the semiconductor device and forcibly remove heat trapped between the semiconductor package and the substrate. The part where the heat is trapped is in the shape of an air pocket, and even if you try to exhaust heat forcibly by external action, the exhaust heat is incomplete due to insufficient air convection. .

さらに検討するに、熱を基板の裏面から放出する構造よりも、熱を基板の上下面で均一化し、基板の上下面での膨張差を低減するほうが、基板の反りは抑制され、半田層の剥離や亀裂による接合不良は抑制される。   For further examination, it is more effective to reduce the difference in expansion between the upper and lower surfaces of the substrate and to reduce the difference in expansion between the upper and lower surfaces of the substrate, compared to the structure in which heat is released from the back surface of the substrate. Bonding failure due to peeling or cracking is suppressed.

本発明は、上述する問題に鑑みてなされたものであり、半導体装置の基板に簡単な加工を施すことで、半導体装置使用時の発熱による少なくとも基板の反りの発生を抑制ないしは低減し、基板と半導体パッケージを接合する半田層の疲労破壊を効果的に抑止することのできる、半導体装置を提供することを目的とする。   The present invention has been made in view of the above-described problems, and by performing simple processing on a substrate of a semiconductor device, at least generation of warpage of the substrate due to heat generation during use of the semiconductor device is suppressed or reduced. It is an object of the present invention to provide a semiconductor device capable of effectively suppressing fatigue failure of a solder layer for joining a semiconductor package.

本発明者等は、上記課題を解決すべく、半導体パッケージが実装される基板に開設された貫通孔を、基板に比して相対的に熱伝導性に優れた熱伝導材で閉塞していることで、半導体装置使用時の発熱によって生じる基板の上下面の熱膨張に起因した基板の反りが効果的に抑制されることを見出し、本発明の半導体装置に至っている。   In order to solve the above-mentioned problems, the present inventors have closed the through-hole formed in the substrate on which the semiconductor package is mounted with a heat conductive material having relatively higher thermal conductivity than the substrate. Thus, it has been found that the warpage of the substrate due to the thermal expansion of the upper and lower surfaces of the substrate caused by the heat generated when the semiconductor device is used is effectively suppressed, and the semiconductor device of the present invention has been achieved.

すなわち、本発明の半導体装置は、放熱性パッドと、該放熱性パッドの一方面に固定された半導体素子と、該放熱性パッドの他方面を露出するようにして、少なくとも前記半導体素子を封止する封止樹脂体と、を具備する半導体パッケージと、前記半導体パッケージを実装する基板と、放熱性パッドの前記他方面と前記基板を接合する半田層と、からなる半導体装置において、前記基板のうち、少なくとも前記放熱性パッドに対応する位置には、前記半導体パッケージと対向する一方面から他方面に延びる貫通孔が開設されており、前記貫通孔は、前記基板に比して相対的に熱伝導率の高い熱伝導材で閉塞されていることを特徴とするものである。   That is, the semiconductor device of the present invention seals at least the semiconductor element so that the heat dissipating pad, the semiconductor element fixed to one surface of the heat dissipating pad, and the other surface of the heat dissipating pad are exposed. In a semiconductor device comprising: a semiconductor package comprising: a sealing resin body; a substrate on which the semiconductor package is mounted; and a solder layer that joins the other surface of the heat dissipating pad to the substrate. In addition, a through hole extending from one surface facing the semiconductor package to the other surface is formed at least at a position corresponding to the heat dissipating pad, and the through hole is relatively thermally conductive as compared to the substrate. It is characterized by being blocked by a heat conductive material having a high rate.

本発明の半導体装置は、基板の上下面での温度を均一化して、上下面での熱膨張差を低減し、基板の反りを抑制することを目的としている。そのためには、半導体パッケージと基板の間に篭もる熱を効率的に基板の裏面に伝熱することが必要となる。   An object of the semiconductor device of the present invention is to equalize the temperature on the upper and lower surfaces of the substrate, reduce the difference in thermal expansion between the upper and lower surfaces, and suppress the warpage of the substrate. For this purpose, it is necessary to efficiently transfer heat accumulated between the semiconductor package and the substrate to the back surface of the substrate.

そこで本発明の半導体装置は、少なくとも放熱性パッドに対応する位置に開設した貫通孔を、基板に比して相対的に熱伝導率の高い熱伝導体で閉塞するという構成を適用したものであり、この構成により、半導体装置使用時の半導体パッケージと基板の間に篭もる熱を基板よりも効率的に基板の裏面に伝熱することが可能となり、基板の上下面での温度をより短時間で均一化することを可能としている。   Therefore, the semiconductor device according to the present invention applies a configuration in which a through-hole opened at least at a position corresponding to a heat radiating pad is closed with a heat conductor having a relatively high thermal conductivity compared to the substrate. This configuration makes it possible to transfer heat trapped between the semiconductor package and the substrate when the semiconductor device is used to the back surface of the substrate more efficiently than the substrate, and to reduce the temperature on the top and bottom surfaces of the substrate. It is possible to make uniform in time.

ここで、前記貫通孔と、これを閉塞する熱伝導材双方の基数は、所望する伝熱効果が得られれば、その基数は何等限定されるものではなく、貫通孔の配設位置、断面形状や大きさも同様である。   Here, the number of bases of both the through hole and the heat conducting material that closes the through hole is not limited as long as a desired heat transfer effect is obtained. The same applies to the size.

また、上記する構造の更なる変形形態として、前記基板に比して相対的に熱伝導率の高い中空部材が、前記貫通孔の内部に配設され、該中空部材を前記熱伝導材が閉塞している構造であってもよい。   Further, as a further modification of the structure described above, a hollow member having a relatively high thermal conductivity as compared with the substrate is disposed inside the through hole, and the heat conductive material is blocked by the hollow member. It may be a structure.

ここで、前記熱伝導材は、前記半田層を形成した後の半田が前記貫通孔の内部に流れ込んで硬化したものであるのが望ましい。基板への半田層形成時に、熱伝導材の形成も同時に実行できるため、熱伝導材を別途製造して貫通孔もしくは中空部材に配設する手間が省け、製造効率を高めることができる。   Here, it is preferable that the heat conductive material is a material in which the solder after forming the solder layer flows into the through hole and is hardened. Since the formation of the heat conductive material can be performed simultaneously with the formation of the solder layer on the substrate, it is possible to save the trouble of separately manufacturing the heat conductive material and disposing it in the through hole or the hollow member, thereby improving the manufacturing efficiency.

その場合において、貫通孔内部に流れ込む半田の主成分は一般にすずであり、その熱伝導率は65W/mK程度であることから、すずに比して熱伝導率の高い銅等からなる中空部材を追加することで、より効率的に熱を基板の裏面に伝熱でき、より短時間で基板の上下面の温度を均一化することができる。さらに、一般的には、基板に開設された貫通孔に比して、別体に形成された中空部材の表面粗さが少ない、すなわち、表面の流体流動性が良好であることより、中空部材の内部に半田を流して硬化させることで、半田の高い流動性と、これに起因する製造時間の短縮を図ることもできる。   In that case, the main component of the solder flowing into the through hole is generally tin, and its thermal conductivity is about 65 W / mK. Therefore, a hollow member made of copper or the like having a higher thermal conductivity than tin is used. By adding, heat can be more efficiently transferred to the back surface of the substrate, and the temperature of the upper and lower surfaces of the substrate can be made uniform in a shorter time. Further, in general, the hollow member formed separately is less in surface roughness than the through-hole formed in the substrate, that is, the surface has good fluid fluidity, so that the hollow member Solder is allowed to flow inside and hardened, so that the high fluidity of the solder and the manufacturing time resulting therefrom can be shortened.

さらに、前記基板において、前記他方面にヒートシンクが配設され、該ヒートシンクは前記貫通孔を閉塞している前記熱伝導体と直接的もしくは間接的に連設されており、平面視で前記放熱性パッドに比して相対的に大きな外部寸法を有する構造とすることによって、基板の広範囲に亘って効率的に、基板の裏面の温度を均一化することができる。   Furthermore, a heat sink is disposed on the other surface of the substrate, and the heat sink is directly or indirectly connected to the heat conductor that closes the through hole. By adopting a structure having a relatively large external dimension compared to the pad, the temperature of the back surface of the substrate can be made uniform efficiently over a wide range of the substrate.

本発明の半導体装置の他の実施形態として、さらに、前記封止樹脂体のうち前記半導体素子から離れた位置には、該半導体素子と導線を介して連通する電極がその一部を前記基板側に露出するようにして埋設されており、前記半導体パッケージが、前記電極の露出した面において、前記基板に別途の半田層を介して接合されている半導体装置において、前記熱伝導体で閉塞された別途の貫通孔が、前記基板の前記電極に対応する位置に配設されており、前記熱伝導体は、前記別途の半田層、前記電極、及び、前記導線を介して、前記半導体素子と連通しているものであってもよい。   As another embodiment of the semiconductor device of the present invention, an electrode that communicates with the semiconductor element via a conductive wire is disposed at a position away from the semiconductor element in the sealing resin body. In the semiconductor device in which the semiconductor package is bonded to the substrate via a separate solder layer on the exposed surface of the electrode, the semiconductor package is blocked by the thermal conductor. A separate through hole is disposed at a position corresponding to the electrode of the substrate, and the thermal conductor communicates with the semiconductor element via the separate solder layer, the electrode, and the conductive wire. It may be what you are doing.

この実施形態によれば、半導体素子から発生する熱を、該半導体素子直下の熱伝導材以外にも、導線を介して基板の半導体素子から離れた位置にある別途の熱伝導材に伝熱することができるため、基板裏面への伝熱効果は一層高いものとなり、基板の上下面の温度をより広域的に均一化することができる。   According to this embodiment, the heat generated from the semiconductor element is transferred to a separate heat conducting material located at a position away from the semiconductor element on the substrate via the conducting wire, in addition to the heat conducting material directly under the semiconductor element. Therefore, the effect of heat transfer to the back surface of the substrate is further enhanced, and the temperature of the top and bottom surfaces of the substrate can be made more uniform over a wider area.

なお、ここでいう「広域的」とは、基板上下面双方の全面の他、双方のほぼ全面を含む意味である。   Note that the term “broad area” as used herein means that the entire surface of both the upper and lower surfaces of the substrate, as well as the substantially entire surface of both.

また、前記基板において、前記他方面に別途のヒートシンクが配設され、該別途のヒートシンクは、前記別途の貫通孔を閉塞している前記熱伝導体と連設されており、平面視で前記別途の貫通孔の外部寸法より相対的に大きな外部寸法を有することによって、基板の上下面の温度の広域的な均一化を一層保障することができる。   In the substrate, a separate heat sink is disposed on the other surface, and the separate heat sink is connected to the thermal conductor that closes the separate through hole, and the separate heat sink is provided in a plan view. By having an external dimension that is relatively larger than the external dimension of the through-hole, it is possible to further ensure the uniform temperature over the wide area of the upper and lower surfaces of the substrate.

本発明の半導体装置によれば、半導体パッケージが実装される基板に開設された貫通孔を、基板に比して相対的に熱伝導性の優れた熱伝導材が閉塞していることで、基板の上下面の熱膨張差に起因した、基板に生じる反りを効果的に抑制することができる。このことにより、基板と半導体パッケージを接合する半田層の疲労破壊を抑制でき、半田の接合不良を改善でき、それと同時に、基板の配線パターンの剥離防止を図ることができる。更には、半導体素子の高温時の到達温度を低下させることもでき、このことは、半導体素子の寿命(すなわち、半導体の最大使用回数)の増加に繋がるものである。   According to the semiconductor device of the present invention, the through hole formed in the substrate on which the semiconductor package is mounted is closed by the heat conductive material having relatively higher thermal conductivity than the substrate. Warpage generated in the substrate due to the difference in thermal expansion between the upper and lower surfaces can be effectively suppressed. As a result, fatigue failure of the solder layer joining the substrate and the semiconductor package can be suppressed, solder joint failure can be improved, and at the same time, peeling of the wiring pattern on the substrate can be prevented. Furthermore, the temperature reached by the semiconductor element at a high temperature can be lowered, which leads to an increase in the life of the semiconductor element (that is, the maximum number of times the semiconductor is used).

本発明の半導体装置の第1の実施の形態の縦断面図である。1 is a longitudinal sectional view of a first embodiment of a semiconductor device of the present invention. 図1のII−II矢視図である。It is an II-II arrow line view of FIG. 図1のIII−III矢視図であり、特に基板に設けられた貫通孔の一実施の形態を説明した平面図である。FIG. 3 is a view taken along the line III-III in FIG. 1, and is a plan view specifically illustrating an embodiment of a through hole provided in a substrate. 本発明の半導体装置の第2の実施の形態の縦断面図である。It is a longitudinal cross-sectional view of 2nd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第3の実施の形態の縦断面図である。It is a longitudinal cross-sectional view of 3rd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第4の実施の形態の縦断面図である。It is a longitudinal cross-sectional view of 4th Embodiment of the semiconductor device of this invention. 図6のVII−VII矢視図であり、特にヒートシンクの他の実施の形態を説明した平面図である。It is a VII-VII arrow line view of Drawing 6, and is a top view explaining other embodiments of a heat sink especially. 従来の半導体装置の縦断面図である。It is a longitudinal cross-sectional view of the conventional semiconductor device. 図8のIX−IX矢視図である。It is the IX-IX arrow line view of FIG.

以下、図面を参照して、本発明の半導体装置の実施の形態を説明する。なお、図示する半導体素子、放熱性パッド、封止樹脂体および基板はいずれも、それらの平面視形状が正方形であるが、これらの平面視形状は長方形、円形、楕円形等であってもよく、さらには、それらのいずれかの組み合わせであってもよい。さらに図示例は、内側の電極、最外周の電極は2列の電極配置形態を示すものであるが、1列や3列以上の電極配置形態等、図示例に限定されるものではない。   Hereinafter, embodiments of a semiconductor device of the present invention will be described with reference to the drawings. In addition, all of the semiconductor element, the heat dissipation pad, the sealing resin body, and the substrate shown in the figure have a square shape in plan view, but the shape in plan view may be rectangular, circular, elliptical, or the like. Further, any combination thereof may be used. Further, in the illustrated example, the inner electrode and the outermost electrode indicate a two-row electrode arrangement form, but are not limited to the illustrated example such as an electrode arrangement form of one row or three or more rows.

図1は、本発明の半導体装置の第1の実施の形態の縦断面図であり、図2は、第1の実施の形態における半導体パッケージの半導体素子や電極の配列位置、図3は、半導体装置の基板に設けられた貫通孔の一実施の形態を説明した図である。図4ないし図6は、本発明の半導体装置の他の実施の形態の縦断面図であり、図7は、基板裏面に設けられたヒートシンクの他の実施の形態を説明した図である。   FIG. 1 is a longitudinal sectional view of a first embodiment of a semiconductor device according to the present invention, FIG. 2 is an arrangement position of semiconductor elements and electrodes of a semiconductor package in the first embodiment, and FIG. It is the figure explaining one Embodiment of the through-hole provided in the board | substrate of an apparatus. 4 to 6 are longitudinal sectional views of other embodiments of the semiconductor device of the present invention, and FIG. 7 is a diagram illustrating another embodiment of the heat sink provided on the back surface of the substrate.

図1で示す本発明の半導体装置100は、半導体パッケージ10と基板8が半田層93,94,95を介して接合されたものである。   A semiconductor device 100 of the present invention shown in FIG. 1 is obtained by bonding a semiconductor package 10 and a substrate 8 via solder layers 93, 94, 95.

まず、半導体パッケージ10の構成について説明する。Agペーストからなる導電性接着剤などのダイボンディング材2により放熱性パッド3(ダイパッド)の上面に半導体素子1が接着され、放熱性パッド3の外側には内側の電極4および最外周の電極5が配設されており、半導体素子1は内側の電極4および最外周の電極5と導線6によって電気的に接続されている。この状態で、半導体素子1等がトランスファモールド金型に装填され、放熱性パッド3および電極4,5それぞれの一部が露出するように、半導体素子1、放熱性パッド3、電極4,5および導線6が、半導体封止用エポキシを用いた封止樹脂体7によって一体に封止され、半導体パッケージ10が形成される。   First, the configuration of the semiconductor package 10 will be described. The semiconductor element 1 is bonded to the upper surface of the heat dissipating pad 3 (die pad) by a die bonding material 2 such as a conductive adhesive made of Ag paste, and an inner electrode 4 and an outermost electrode 5 are disposed outside the heat dissipating pad 3. The semiconductor element 1 is electrically connected to the inner electrode 4 and the outermost electrode 5 by a conductive wire 6. In this state, the semiconductor element 1, etc. are loaded in the transfer mold, and the semiconductor element 1, the heat dissipating pad 3, the electrodes 4, 5 and so on are exposed so that a part of each of the heat dissipating pad 3 and the electrodes 4, 5 is exposed. The conducting wire 6 is integrally sealed by a sealing resin body 7 using a semiconductor sealing epoxy, and a semiconductor package 10 is formed.

ここで、放熱性パッド3は、放熱性能を有し半導体素子を搭載できるものであれば、その大きさや材質などは特に限定されるものではない。もっとも、安定性や放熱性の観点から言えば、放熱性パッドの方が半導体より大きい方が好ましく、また、熱伝導性の高い材料が適していて、例えば、銅、銀、金、白金、ニッケル、コバルト、亜鉛等の純金属、及び、それらを含む合金が好ましく使用される。また、放熱性パッド3および電極4,5の露出した表面には半田漏れ性の良い金属(ニッケル、クロム、金等)がメッキされていてもよい。   Here, the size and material of the heat dissipating pad 3 are not particularly limited as long as the heat dissipating pad 3 has heat dissipating performance and can be mounted with a semiconductor element. However, from the viewpoint of stability and heat dissipation, it is preferable that the heat dissipation pad is larger than the semiconductor, and materials with high thermal conductivity are suitable, for example, copper, silver, gold, platinum, nickel Pure metals such as cobalt and zinc, and alloys containing them are preferably used. Further, the exposed surfaces of the heat dissipating pad 3 and the electrodes 4 and 5 may be plated with a metal (nickel, chromium, gold, etc.) having good solder leakage.

次に、基板8について説明する。上記半導体パッケージ10の形成工程とは別途の工程において、半導体パッケージ10が実装される基板8には、ドリル加工により貫通孔81が予め開通されている。   Next, the substrate 8 will be described. In a process separate from the process of forming the semiconductor package 10, a through hole 81 is previously opened in the substrate 8 on which the semiconductor package 10 is mounted by drilling.

たとえば、基板8としては、ガラス基板、ガラス−エポキシ基板、アルミナ基板、ジルコニア基板等の各種の基板を用いることができ、一般的には、空気よりも熱伝導率が高く、銅等の金属よりも熱伝導率が低い材料が使用される。さらに、基板として使用されるのは、単層および積層の構造のいずれのものでもよい。また、貫通孔の加工方法としても、上記のドリル加工以外にも、パンチングなどの機械加工やエキシマレーザや炭酸ガスレーザなどのレーザ加工等の方法により開通することができるし、基板形成と同時に貫通孔を設ける方法でもよい。   For example, as the substrate 8, various substrates such as a glass substrate, a glass-epoxy substrate, an alumina substrate, and a zirconia substrate can be used. Generally, the substrate 8 has a higher thermal conductivity than air and is higher than a metal such as copper. Also, a material with low thermal conductivity is used. Furthermore, the substrate may be either a single layer or a laminated structure. Also, as a through hole processing method, in addition to the above drill processing, it can be opened by a method such as punching or laser processing such as excimer laser or carbon dioxide laser. The method of providing may be sufficient.

上記の半導体パッケージ10および基板8を形成する前工程の後、半導体パッケージ10は、半田ペースト(ボール半田等を含む)が塗布された基板8の実装面8a上に配設される。次いで、これらをリフロー炉内に配置し、半田をリフローすることによって、半導体パッケージ10を構成する放熱性パッド3、電極4,5それぞれの露出部分と、基板8とが、半田層93,94,95を介して接合される。ここで、リフロー時に溶解した半田の一部は、半田層93直下に配設された貫通孔81の内部に流れ込み、これが硬化してなる半田82によって貫通孔81は閉塞される。   After the pre-process of forming the semiconductor package 10 and the substrate 8 described above, the semiconductor package 10 is disposed on the mounting surface 8a of the substrate 8 to which a solder paste (including ball solder or the like) is applied. Next, these are placed in a reflow furnace and the solder is reflowed, whereby the exposed portions of the heat dissipating pads 3 and the electrodes 4 and 5 constituting the semiconductor package 10 and the substrate 8 are solder layers 93, 94, 95 is joined. Here, a part of the solder melted at the time of reflow flows into the through-hole 81 disposed immediately below the solder layer 93, and the through-hole 81 is closed by the solder 82 formed by curing.

さらに、基板8の裏面8bには、貫通孔81を閉塞している半田82と連設されており、平面視で放熱性パッド3に比して相対的に大きな外部寸法を有したヒートシンク11が配設されることにより、半導体装置100が形成される。   Further, the back surface 8b of the substrate 8 is connected to the solder 82 blocking the through hole 81, and the heat sink 11 having a relatively large external dimension as compared with the heat dissipating pad 3 in plan view. By being disposed, the semiconductor device 100 is formed.

ここで、ヒートシンク11の形成素材としては、一般に熱伝導性に優れた金属が使用されるのが好ましく、貫通孔81が半田82で閉塞された後に、溶着や接着によって基板8の裏面8bに配設されてもよいし、配線パターンを併用する等して、基板8の形成時に基板8の裏面8bに予め設置されていてもよい。   Here, as a material for forming the heat sink 11, it is generally preferable to use a metal having excellent thermal conductivity. After the through hole 81 is closed with the solder 82, the heat sink 11 is disposed on the back surface 8 b of the substrate 8 by welding or adhesion. It may be provided, or may be provided in advance on the back surface 8b of the substrate 8 when the substrate 8 is formed by using a wiring pattern in combination.

また、貫通孔81はリフロー時に流れ込んだ半田によって閉塞されるものであるが、これ以外にも、リフローの前工程の基板形成時に放熱性パッドに用いるような熱伝導率の高い材料で予め閉塞しておいてもよい。より具体的には、機械加工やレーザ加工等によって基板に貫通孔を開通した後に、銅等の熱伝導率の高い材料で貫通孔を閉塞しておくものである。   Further, the through hole 81 is blocked by the solder that flows in during reflow, but in addition to this, the through hole 81 is blocked in advance by a material having a high thermal conductivity such as that used for a heat dissipating pad when forming the substrate in the pre-reflow process. You may keep it. More specifically, after the through hole is opened in the substrate by machining or laser processing, the through hole is closed with a material having high thermal conductivity such as copper.

図2に示した半導体素子1、放熱性パッド3、電極4,5の位置に対応する、貫通孔81の一実施の形態が図3に示されており、放熱性パッド3の各辺に対応する位置に、円形の貫通孔81が一つずつ配設されている。なお、図3に示した貫通孔の配置以外でも、所望する伝熱効果が得られれば、その基数は何等限定されるものではなく、貫通孔の配置位置も、例えば、放熱性パッドの対角線上に対応する位置に配設されてもよいし、半導体素子の放熱が多い位置に重点的に配置される等して、その配置位置に対称性がなくてもよい。勿論、貫通孔の断面形状や大きさも同様であることは言うまでもない。   One embodiment of the through hole 81 corresponding to the positions of the semiconductor element 1, the heat dissipating pad 3 and the electrodes 4, 5 shown in FIG. 2 is shown in FIG. 3, and corresponds to each side of the heat dissipating pad 3. One circular through hole 81 is provided at each position. In addition to the arrangement of the through holes shown in FIG. 3, the number of bases is not limited as long as a desired heat transfer effect is obtained, and the arrangement position of the through holes is, for example, on the diagonal line of the heat dissipation pad. It may be arranged at a position corresponding to the above, or the arrangement position may not be symmetric, for example, by being intensively arranged at a position where the heat radiation of the semiconductor element is large. Of course, it goes without saying that the cross-sectional shape and size of the through holes are the same.

次に、半導体装置100が使用される際に発熱源である半導体素子1からの伝熱の態様を説明する。   Next, an aspect of heat transfer from the semiconductor element 1 that is a heat source when the semiconductor device 100 is used will be described.

図1の貫通孔81を閉塞している半田82の主成分であるすずの熱伝導率は65W/mK程度であり、基盤8に多く用いられるエポキシ樹脂の熱伝導率0.21W/mKに比して熱伝導性が良いことから、半導体装置使用時において半導体パッケージ10と基板8の間に篭もろうとする熱は、主として半田82を介して基板8の裏面8b側に伝熱されることになる。   The thermal conductivity of tin, which is the main component of the solder 82 that closes the through-hole 81 in FIG. 1, is about 65 W / mK, compared to the thermal conductivity of 0.21 W / mK of the epoxy resin often used for the substrate 8. Since the heat conductivity is good, the heat that is about to be trapped between the semiconductor package 10 and the substrate 8 when the semiconductor device is used is mainly transferred to the back surface 8b side of the substrate 8 through the solder 82.

まず、半導体使用開始時には、半導体素子1の温度が上昇する。半導体素子1から発生した熱は、ダイボンディング材2を介して直下の放熱性パッド3に伝熱し、放熱性パッド3の温度が上昇し、次いで半田層93の温度が上昇する。半田層93の温度上昇により、半田層93と接する半田82および基板8それぞれの温度も上昇するが、基板8のみで熱を伝熱する場合と比較して、熱伝導率の高い半田82を介することでより短時間に基板8の裏面8bに伝熱されることになる(矢印A)。なお、半田層93の温度とヒートシンク11の温度が一定となるまで伝熱は継続される。図示例のように、ヒートシンク11が平面視で放熱性パッド3に比して相対的に大きな外部寸法を有している形態では、その熱ひき性能が一段と高くなり、基板8の上下面での温度差をより短時間で解消することができる。   First, at the start of semiconductor use, the temperature of the semiconductor element 1 rises. The heat generated from the semiconductor element 1 is transferred to the heat dissipating pad 3 directly below through the die bonding material 2, the temperature of the heat dissipating pad 3 rises, and then the temperature of the solder layer 93 rises. As the temperature of the solder layer 93 rises, the temperature of each of the solder 82 and the substrate 8 in contact with the solder layer 93 also rises. However, as compared with the case where heat is transferred only by the substrate 8, the solder 82 has a higher thermal conductivity. Thus, heat is transferred to the back surface 8b of the substrate 8 in a shorter time (arrow A). Heat transfer is continued until the temperature of the solder layer 93 and the temperature of the heat sink 11 become constant. In the form in which the heat sink 11 has a relatively large external dimension as compared to the heat dissipating pad 3 in plan view as in the illustrated example, the heat sink performance is further enhanced, The temperature difference can be eliminated in a shorter time.

ここで、第1の実施の形態における貫通孔81を閉塞する半田82は、リフロー時に半田層93を形成した後の半田が流れ込んで硬化したものであるが、貫通孔81を半田で閉塞する手法として、リフロー時に基板8の裏面8bから半田供給器(図示せず)によって半田を供給する手法を挙げることができる。この方法では、リフロー時に基板8の裏面8bから貫通孔81に供給された半田は、毛管作用によって自然に基板8の実装面8aに向かって上昇していき、貫通孔81を閉塞する。なお、この毛管作用を促進させるべく、貫通孔81を連通させる不図示の脱気孔を適所に配しておくのがよい。   Here, the solder 82 that closes the through hole 81 in the first embodiment is one in which the solder after forming the solder layer 93 flows and hardens during reflow, but the method of closing the through hole 81 with solder is used. As a method, solder may be supplied from the back surface 8b of the substrate 8 by a solder supply device (not shown) during reflow. In this method, the solder supplied to the through hole 81 from the back surface 8b of the substrate 8 at the time of reflow rises naturally toward the mounting surface 8a of the substrate 8 by capillary action, and closes the through hole 81. In order to promote this capillary action, a deaeration hole (not shown) that allows the through-hole 81 to communicate with each other is preferably arranged at an appropriate position.

図4は、本発明の半導体装置の第2の実施の形態の縦断面図であり、図1と同じ部品に関する詳細説明は省略する。   FIG. 4 is a longitudinal cross-sectional view of the second embodiment of the semiconductor device of the present invention, and a detailed description of the same components as those in FIG. 1 is omitted.

図4において、基板8Aに配設された貫通孔81の内部には、基板8Aに比して相対的に熱伝導率の高い中空部材83が配設されており、その他の構成に関しては第1の実施の形態と同様である。リフロー時において、半田層93を形成した後の半田はその直下に配設された貫通孔81に設けられた中空部材83の内部に流れ込み、これが硬化してなる半田84によって中空部材83が閉塞される。   In FIG. 4, a hollow member 83 having a relatively high thermal conductivity as compared with the substrate 8A is disposed inside the through hole 81 disposed in the substrate 8A. This is the same as the embodiment. At the time of reflow, the solder after forming the solder layer 93 flows into the hollow member 83 provided in the through hole 81 disposed immediately below the solder layer 93, and the hollow member 83 is blocked by the solder 84 formed by curing the solder. The

また、中空部材83はリフロー時に流れ込んだ半田によって閉塞されたが、第1の実施の形態と同様、リフローの前工程の基板形成時に、放熱性パッドに用いるような熱伝導率の高い材料で予め閉塞しておいてもよい。さらには、リフロー時に、基板8Aの裏面8Abから中空部材83に半田を供給してもよい。   Further, the hollow member 83 is closed by the solder that flows in at the time of reflow. However, in the same way as in the first embodiment, when the substrate is formed in the pre-reflow process, the hollow member 83 is previously made of a material having high thermal conductivity that is used for the heat dissipation pad. It may be occluded. Furthermore, solder may be supplied to the hollow member 83 from the back surface 8Ab of the substrate 8A during reflow.

第2の実施の形態によれば、中空部材83について、半田84より熱伝導性の高い銅等の純金属もしくは合金を使用することで、実装面8Aaから裏面8Abへの熱伝導をより一層促進することができる。また、一般的に、基板8Aに開設された貫通孔81に比して、別体に形成された中空部材83の表面粗さが少ない、すなわち、表面の流体流動性が良好であることより、リフロー時に中空部材83の内部に流れ込む半田の流動性も良好となり、中空部材83の閉塞に要する時間短縮を図ることができる。このことは、半導体装置100A自体の加熱時間の短縮をも意味しており、半導体装置100Aのサーマルショックによる損傷を抑制することにつながる。なお、基板8Aの裏面8Abから半田供給器で半田を供給し、中空部材83を閉塞させる場合についても同様である。   According to the second embodiment, by using a pure metal or alloy such as copper having higher thermal conductivity than the solder 84 for the hollow member 83, heat conduction from the mounting surface 8Aa to the back surface 8Ab is further promoted. can do. In general, compared to the through-hole 81 provided in the substrate 8A, the surface roughness of the hollow member 83 formed separately is small, that is, the fluid fluidity of the surface is good. The flowability of the solder flowing into the hollow member 83 during reflow is also improved, and the time required for closing the hollow member 83 can be reduced. This also means shortening the heating time of the semiconductor device 100A itself, which leads to suppressing damage to the semiconductor device 100A due to thermal shock. The same applies to the case where the solder is supplied from the back surface 8Ab of the substrate 8A with the solder supply device and the hollow member 83 is closed.

図5は、本発明の半導体装置の第3の実施の形態の縦断面図であり、図4に対して、中空部材とヒートシンクの構成を変形したものである。   FIG. 5 is a longitudinal sectional view of a third embodiment of the semiconductor device of the present invention, which is a modification of the configuration of the hollow member and the heat sink with respect to FIG.

図5において、中空部材85と、中空部材85を閉塞する半田86は、ヒートシンク12の厚み分だけ、基板8Bの裏面8Bbから突出した設定となっている。ヒートシンク12には、中空部材85に対応した位置に、平面視で中空部材85の外部寸法と同じ寸法を有する開口が設けられ、ヒートシンク12の開口の内部で中空部材85と当接している。   In FIG. 5, the hollow member 85 and the solder 86 that closes the hollow member 85 are set to protrude from the back surface 8Bb of the substrate 8B by the thickness of the heat sink 12. The heat sink 12 is provided with an opening having the same dimension as the external dimension of the hollow member 85 in a plan view at a position corresponding to the hollow member 85, and is in contact with the hollow member 85 inside the opening of the heat sink 12.

第3の実施の形態によれば、ヒートシンク12を中空部材85へ嵌合することで設置でき、溶着、接着等の工程を不要とできる。また、第1および第2の実施の形態においては、貫通孔内の脱気の観点から、貫通孔が半田により閉塞された後にヒートシンクが設置されることが好ましいが、第3の実施の形態を用いれば、既存の配線パターンが設定された基板に対して貫通孔を開設し、その配線パターンにヒートシンクとしての機能も追加することができるため、既存の製造工程をわずかに改良するだけでよい。   According to the third embodiment, it can be installed by fitting the heat sink 12 to the hollow member 85, and steps such as welding and adhesion can be eliminated. Further, in the first and second embodiments, from the viewpoint of deaeration in the through hole, it is preferable that the heat sink is installed after the through hole is closed by solder. If used, a through hole can be opened in a substrate on which an existing wiring pattern is set, and a function as a heat sink can be added to the wiring pattern. Therefore, the existing manufacturing process only needs to be improved slightly.

さらに、第3の実施の形態のヒートシンク12と中空部材85は一体成形されるものであってもよい。ヒートシンク12と中空部材85を一体とすることで、中空部材85を貫通孔81に嵌合する際に、同時にヒートシンク12を基板8Bに設置することができる。   Furthermore, the heat sink 12 and the hollow member 85 of the third embodiment may be integrally formed. By integrating the heat sink 12 and the hollow member 85, when the hollow member 85 is fitted into the through hole 81, the heat sink 12 can be simultaneously installed on the substrate 8B.

図6は、本発明の半導体装置の第4の実施の形態の縦断面図であり、第4の実施の形態における放熱性パッド3に対応する位置の貫通孔の構成は第1の実施の形態を使用しているが、第2および第3の実施の形態を使用しても同様な効果が得られることは言うまでもない。   FIG. 6 is a longitudinal sectional view of a semiconductor device according to a fourth embodiment of the present invention. The configuration of the through hole at a position corresponding to the heat dissipating pad 3 in the fourth embodiment is the first embodiment. However, it goes without saying that the same effect can be obtained even if the second and third embodiments are used.

第4の実施の形態では、半導体パッケージ10が実装される前の基板8Cには、上記の放熱性パッド3に対応する位置の貫通孔81とは別に、電極4,5に対応した位置に貫通孔87,89が開設されている。   In the fourth embodiment, the substrate 8C before the semiconductor package 10 is mounted penetrates to the position corresponding to the electrodes 4 and 5 separately from the through hole 81 corresponding to the heat dissipation pad 3. Holes 87 and 89 are opened.

前述の実施の形態と同様に、リフロー時に溶解した半田の一部は、半田層94,95直下に配設された貫通孔87,89の内部に流れ込み、これが硬化してなる半田88,90によって貫通孔87,89は閉塞される。   Similar to the above-described embodiment, a part of the solder melted at the time of reflow flows into the through holes 87 and 89 disposed immediately below the solder layers 94 and 95, and is cured by the solders 88 and 90 formed by curing. The through holes 87 and 89 are closed.

さらに、基板8Cの裏面8Cbは、貫通孔87,89を閉塞している半田88,90と連設されており、平面視で貫通孔87,89に比して相対的に大きな外部寸法を有するヒートシンク13,14が配設されることで、半導体装置100Cが形成される。
ここで、貫通孔87,89はリフロー時に流れ込んだ半田によって閉塞されるものであるが、基板形成時に、銅等の熱伝導性の高い材料で予め閉塞してもおいてもよい。例えば、一般に基板の剛性強化のために使用される銅のビヤを、上記の熱伝導材としての機能を併用する形態を挙げることができる。
Further, the back surface 8Cb of the substrate 8C is connected to the solders 88 and 90 closing the through holes 87 and 89, and has a relatively large external dimension as compared to the through holes 87 and 89 in a plan view. By disposing the heat sinks 13 and 14, the semiconductor device 100C is formed.
Here, the through holes 87 and 89 are closed by the solder that flows in at the time of reflow. However, the through holes 87 and 89 may be previously closed by a material having high thermal conductivity such as copper when the substrate is formed. For example, a copper via generally used for reinforcing the rigidity of a substrate may be used in combination with the above-described function as a heat conductive material.

次に、半導体装置100Cが使用される際に発熱源である半導体素子1からの電極部4,5を介した伝熱の態様を説明する。   Next, a mode of heat transfer from the semiconductor element 1 as a heat generation source through the electrode portions 4 and 5 when the semiconductor device 100C is used will be described.

まず、半導体使用開始時には、半導体素子1の温度が上昇する。半導体素子1から発生した熱は、主にボンディング材2を介して直下の放熱性パッド3に伝熱されるが、その一部は導線6を介して電極4,5に伝熱し(矢印C)、次いで半田層94,95の温度が上昇する。半田層94,95の温度上昇により、半田層94,95と接する半田88,90および基板8Cそれぞれの温度が上昇するが、基板8Cのみで熱を伝熱する場合と比較して、熱伝導率の高い半田88,90を介することでより短時間に基板8Cの裏面8Cbに伝熱されることになる(矢印D)。なお、半田層94,95の温度とヒートシンク13,14の温度が一定となるまで伝熱は継続され、基板8C全体では、半田層93,94,95の温度とヒートシンク11,13,14の温度が一定となるまで伝熱は継続される。図示例のように、ヒートシンク13,14が平面視で貫通孔87,89に比して相対的に大きな外部寸法を有している形態では、その熱ひき性能が一段と高くなり、基板8Cの上下面での温度差を更に短時間で解消することができる。   First, at the start of semiconductor use, the temperature of the semiconductor element 1 rises. The heat generated from the semiconductor element 1 is mainly transferred to the heat dissipating pad 3 directly below the bonding material 2, but part of the heat is transferred to the electrodes 4 and 5 via the conductor 6 (arrow C), Next, the temperature of the solder layers 94 and 95 rises. The temperature of the solder layers 94 and 95 raises the temperature of each of the solder 88 and 90 and the substrate 8C in contact with the solder layers 94 and 95, but the thermal conductivity is higher than that in the case where heat is transferred only by the substrate 8C. Heat is transferred to the back surface 8Cb of the substrate 8C in a shorter time by passing through the high solders 88 and 90 (arrow D). Heat transfer is continued until the temperature of the solder layers 94 and 95 and the temperature of the heat sinks 13 and 14 become constant, and the temperature of the solder layers 93, 94 and 95 and the temperature of the heat sinks 11, 13 and 14 in the entire substrate 8C. Heat transfer is continued until becomes constant. In the form in which the heat sinks 13 and 14 have relatively large external dimensions as compared to the through holes 87 and 89 in plan view as in the illustrated example, the heat sink performance is further enhanced, and the upper surface of the substrate 8C is increased. The temperature difference on the lower surface can be eliminated in a shorter time.

なお、図6では、半導体装置100Cの縦断面図における半導体装置中心より左側に設けられた電極部を介した熱の流れを説明したが、半導体装置中心より右側に設けられた電極部に関しても同様な熱の流れが発生することは言うまでもない。   6 illustrates the flow of heat through the electrode portion provided on the left side of the semiconductor device center in the vertical cross-sectional view of the semiconductor device 100C, the same applies to the electrode portion provided on the right side of the semiconductor device center. Needless to say, a heat flow is generated.

図7は、図6の実施の形態の半導体装置100Cの基板8Cを裏面側から見た図であるが、ヒートシンク11およびヒートシンク13,14は、お互いに当接しない位置に配設されている。第4の実施の形態では、ヒートシンク11およびヒートシンク13,14は平面視で正方形の形状であるが、長方形、円形、楕円形、または、その組み合わせ等、それらの形状は何等限定されるものではない。また、半導体素子1の放熱が大きい部位に接続されたヒートシンクを大きくする等、各々のヒートシンクの大きさも適宜変更可能である。さらに、第4の実施の形態のように全ての電極部にヒートシンクを配設する必要はなく、また、貫通孔の中心にヒートシンクの中心を合わせる必要もないことは言うまでもない。   FIG. 7 is a view of the substrate 8C of the semiconductor device 100C of the embodiment of FIG. 6 as viewed from the back side. The heat sink 11 and the heat sinks 13 and 14 are disposed at positions where they do not contact each other. In the fourth embodiment, the heat sink 11 and the heat sinks 13 and 14 have a square shape in a plan view, but the shape is not limited to a rectangle, a circle, an ellipse, or a combination thereof. . Also, the size of each heat sink can be changed as appropriate, for example, by increasing the size of the heat sink connected to the portion of the semiconductor element 1 where heat dissipation is large. Furthermore, it is needless to say that it is not necessary to dispose a heat sink on all electrode portions as in the fourth embodiment, and it is not necessary to align the center of the heat sink with the center of the through hole.

以上、本発明の実施の形態に関して図面を用いて詳述してきたが、具体的な構成はこの実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲における設計変更等があっても、それらは本発明に含まれるものである。   The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. They are also included in the present invention.

1…半導体素子、3…放熱性パッド、4…内側の電極、5…最外周の電極、7…封止樹脂体、8,8A,8B,8C…基板、10…半導体パッケージ、11,12,13,14…ヒートシンク、81,87,89…貫通孔、83,85…中空部材、93,94,95…半田層、100,100A,100B,100C…半導体装置   DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 3 ... Heat dissipation pad, 4 ... Inner electrode, 5 ... Outermost electrode, 7 ... Sealing resin body, 8, 8A, 8B, 8C ... Substrate, 10 ... Semiconductor package, 11, 12, DESCRIPTION OF SYMBOLS 13,14 ... Heat sink, 81, 87, 89 ... Through-hole, 83, 85 ... Hollow member, 93, 94, 95 ... Solder layer, 100, 100A, 100B, 100C ... Semiconductor device

Claims (6)

放熱性パッドと、該放熱性パッドの一方面に固定された半導体素子と、該放熱性パッドの他方面を露出するようにして、少なくとも前記半導体素子を封止する封止樹脂体と、を具備する半導体パッケージと、前記半導体パッケージを実装する基板と、放熱性パッドの前記他方面と前記基板を接合する半田層と、からなる半導体装置において、
前記基板のうち、少なくとも前記放熱性パッドに対応する位置には、前記半導体パッケージと対向する一方面から他方面に延びる貫通孔が開設されており、
前記貫通孔は、前記基板に比して相対的に熱伝導率の高い熱伝導材で閉塞されている、半導体装置。
A heat dissipating pad; a semiconductor element fixed to one surface of the heat dissipating pad; and a sealing resin body for sealing at least the semiconductor element so as to expose the other surface of the heat dissipating pad. In a semiconductor device comprising: a semiconductor package to be mounted; a substrate on which the semiconductor package is mounted; and a solder layer that bonds the other surface of the heat dissipating pad to the substrate.
A through hole extending from one surface facing the semiconductor package to the other surface is opened at least in a position corresponding to the heat dissipating pad in the substrate.
The semiconductor device, wherein the through hole is closed with a heat conductive material having a relatively high thermal conductivity as compared with the substrate.
前記基板に比して相対的に熱伝導率の高い中空部材が、前記貫通孔の内部に配設され、該中空部材を前記熱伝導材が閉塞している、請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a hollow member having a relatively high thermal conductivity as compared with the substrate is disposed inside the through hole, and the heat conductive material closes the hollow member. . 前記熱伝導材は、前記半田層を形成した後の半田が前記貫通孔の内部に流れ込んで硬化したものからなる、請求項1または2に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the heat conductive material is made of a material in which the solder after forming the solder layer flows into the through hole and is hardened. 4. 前記基板において、前記他方面にヒートシンクが配設され、該ヒートシンクは前記貫通孔を閉塞している前記熱伝導体と、直接的もしくは間接的に連設されており、平面視で前記放熱性パッドに比して相対的に大きな外部寸法を有する、請求項1ないし3のいずれか一項に記載の半導体装置。   In the substrate, a heat sink is disposed on the other surface, and the heat sink is directly or indirectly connected to the heat conductor closing the through hole, and the heat dissipating pad in plan view. The semiconductor device according to claim 1, wherein the semiconductor device has a relatively large external dimension as compared with the semiconductor device. 前記封止樹脂体のうち前記半導体素子から離れた位置には、該半導体素子と導線を介して連通する電極がその一部を前記基板側に露出するようにして埋設されており、前記半導体パッケージが、前記電極の露出した面において、前記基板に別途の半田層を介して接合されている半導体装置において、
前記熱伝導体で閉塞された別途の貫通孔が、前記基板の前記電極に対応する位置に配設されており、
前記熱伝導体は、前記別途の半田層、前記電極、及び、前記導線を介して、前記半導体素子と連通している、請求項1ないし4のいずれか一項に記載の半導体装置。
An electrode communicating with the semiconductor element via a conductor is embedded in the sealing resin body at a position away from the semiconductor element so that a part of the electrode is exposed to the substrate side. However, in the exposed surface of the electrode, in the semiconductor device joined to the substrate through a separate solder layer,
A separate through hole closed with the heat conductor is disposed at a position corresponding to the electrode of the substrate,
5. The semiconductor device according to claim 1, wherein the thermal conductor is in communication with the semiconductor element through the separate solder layer, the electrode, and the conductive wire.
前記基板において、前記他方面に別途のヒートシンクが配設され、該別途のヒートシンクは、前記別途の貫通孔を閉塞している前記熱伝導体と連設されており、平面視で前記別途の貫通孔の外部寸法より相対的に大きな外部寸法を有する、請求項5に記載の半導体装置。
In the substrate, a separate heat sink is disposed on the other surface, and the separate heat sink is connected to the thermal conductor closing the separate through hole, and the separate through hole is seen in a plan view. The semiconductor device according to claim 5, wherein the semiconductor device has an external dimension relatively larger than an external dimension of the hole.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI480986B (en) * 2012-08-30 2015-04-11 矽品精密工業股份有限公司 Semiconductor package and method of forming same
CN106031315A (en) * 2014-06-23 2016-10-12 三星电机株式会社 Circuit board and circuit board assembly
JP2017069547A (en) * 2015-08-31 2017-04-06 ジョンソン エレクトリック ソシエテ アノニム Thermally efficient electrical assembly
KR101796519B1 (en) * 2014-05-16 2017-11-15 삼성전기주식회사 Circuit board and circuit board assembly
US11931490B2 (en) 2018-10-05 2024-03-19 Seoul Viosys Co., Ltd. Air purification module and refrigerator comprising the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252047A (en) * 2004-03-05 2005-09-15 Rohm Co Ltd Semiconductor device
JP2006024755A (en) * 2004-07-08 2006-01-26 Fujitsu Ltd Circuit board
JP2006054481A (en) * 2005-09-22 2006-02-23 Denso Corp Electronic control device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252047A (en) * 2004-03-05 2005-09-15 Rohm Co Ltd Semiconductor device
JP2006024755A (en) * 2004-07-08 2006-01-26 Fujitsu Ltd Circuit board
JP2006054481A (en) * 2005-09-22 2006-02-23 Denso Corp Electronic control device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI480986B (en) * 2012-08-30 2015-04-11 矽品精密工業股份有限公司 Semiconductor package and method of forming same
KR101796519B1 (en) * 2014-05-16 2017-11-15 삼성전기주식회사 Circuit board and circuit board assembly
CN106031315A (en) * 2014-06-23 2016-10-12 三星电机株式会社 Circuit board and circuit board assembly
CN106031315B (en) * 2014-06-23 2019-06-28 三星电机株式会社 Circuit substrate and circuit substrate component
JP2017069547A (en) * 2015-08-31 2017-04-06 ジョンソン エレクトリック ソシエテ アノニム Thermally efficient electrical assembly
US11931490B2 (en) 2018-10-05 2024-03-19 Seoul Viosys Co., Ltd. Air purification module and refrigerator comprising the same

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