TWI467731B - Semiconductor package and method for fabricating the same - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package, and more particularly to a semiconductor package having a stacked wafer and a method of fabricating the same.

The early multi-chip package structure used side-by-side, which has the disadvantages of high packaging cost and large structure size. Therefore, in recent years, the vertical stacking method is used to increase the number of wafers to save the substrate. Space; the way of stacking depends on the design of the chip, and the wire bonding process is different depending on the stacking method, for example, the flash memory chip set by the memory card in the electronic device (flash memory) Chip) or a dynamic random access memory (DRAM) or the like.

As shown in FIG. 1A, the conventional semiconductor package 1 (with the illustration of the package encapsulation omitted) stacks the plurality of memory chips 11 on a carrier 10, and each of the memory chips 11 is stacked in a stepped manner and transmitted through The plurality of bonding wires 12 electrically connect the electrode pads 110 of the memory chips 11 to the electrical connection pads 100 of the carrier board 10.

However, the stepped stack is stacked after being offset by a distance, so that when the more wafers are stacked, the larger the area of the uppermost memory chip 11 covering the carrier 10 is, the more the use of the carrier 10 is increased. The area, that is, the increase of the inactive area L, is not conducive to the need for miniaturization of the package.

Moreover, each of the memory chips 11 has to be subjected to a wire bonding process, so that the more the number of the memory chips 11 are stacked, the more the number of wire bonding places is, so that the wire bonding wires 12 are densely arranged, resulting in the semiconductor. The package 1 requires more space for the bonding wires 12 to be disposed, which is disadvantageous for the reduction of the volume of the semiconductor package 1 , and the size of the semiconductor package 1 is difficult to meet the demand for miniaturization.

Therefore, 遂 developed an electrical connection technique applied to a stacked structure, such as US Patent No. 20090068790, which uses a redistribution layer (RDL) process on each wafer to form a plurality of outwardly protruding signal terminals. The wiring inside the wafer is used as a conduction path, so that after the wafers are vertically stacked on a substrate, the signal terminals can be electrically connected to the signal terminals by a plurality of conductive pastes, so that the required layout space is smaller than the soldering. The wire is a required space for the conventional package of the electrical connection medium, so that the size of the substrate can be reduced, so that the semiconductor package meets the requirement of miniaturization of the package.

Further, in the above manner, the semiconductor package 1 ′ as shown in FIG. 1B can be formed (the illustration of the encapsulant is omitted), that is, the stepped stacked structure formed by each of the memory wafers 11 passes through the plurality of conductive colloids. 12' is electrically connected to the carrier board 10.

However, in the above two conventional techniques of applying the conductive paste 12', the width of the conductive paste 12' is larger than the width of the conventional bonding wire 12, so that any two adjacent electrical connection pads 100 on the carrier 10 The distance D needs to be large enough (as shown in FIG. 1B', the spacing D is greater than about 200 um) to avoid short-circuiting of the conductive colloids 12', so that the carrier board 10 needs to have a large bearing area. The electrical connection pads 100 are disposed, so that the carrier board 10 still needs to maintain a certain size and is difficult to be further reduced, so that the package cannot be further miniaturized.

Furthermore, the process of forming the conductive paste 12' requires the formation of RDL on each of the memory chips 11, so that the cost is higher than that of the conventional wire bonding process, and the production capacity of the product is not mature due to the technical maturity ( Unit Per Hour (UPH) is lower; if only the signal terminal is added to form the RDL on the memory chip 11 for cost saving, the number of stacked chips will be limited.

Moreover, in the subsequent process, when a control wafer (not shown) is placed on the uppermost memory chip 11, if the control wafer is a defective product, the overall electrical yield of the product is directly affected.

In addition, the wafer polishing technology has reached a bottleneck, and the wafer is thinned to a certain extent, and the overall thickness of the semiconductor package needs to be added to the thickness of the control wafer, so that it is difficult to further thin the fabricated semiconductor package.

Therefore, how to overcome the various problems in the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor package comprising: an encapsulant having opposite first and second surfaces, and at least one opening formed on the first surface of the encapsulant a plurality of first semiconductor elements stacked on each other and embedded in the encapsulant; a conductive layer formed on a surface of the structure on which the first semiconductor elements are stacked to electrically conduct the first semiconductor elements, And at least one of the conductive layers on the first semiconductor component exposes the opening; and the first circuit layer is formed on the first surface of the encapsulant to electrically connect the conductive layer through the opening.

In the foregoing semiconductor package, the heat dissipation structure disposed on the second surface of the encapsulant is further included.

The present invention provides a method of fabricating a semiconductor package, comprising: stacking a plurality of first semiconductor elements on a carrier board; forming a conductive layer on the surface of the structure on which the first semiconductor elements are stacked, to electrically conduct the respective a first semiconductor component; forming an encapsulant on the carrier plate to cover each of the first semiconductor component and the conductive layer, and the encapsulant has opposite first and second surfaces, the second surface is bonded to the a carrier plate; forming at least one opening on the first surface of the at least one encapsulant to expose a portion of the conductive layer on the first semiconductor element; and forming a first circuit layer on the encapsulant On a surface, the first circuit layer is electrically connected to the conductive layer via the opening.

In the above method, the opening is formed by laser.

In the above manufacturing method, the carrier plate is a heat dissipation structure.

In the foregoing semiconductor package and the method of manufacturing the same, the stacking manner of the first semiconductor elements is a stepped stack.

In the foregoing semiconductor package and the method of fabricating the same, the insulating layer is formed on the surface of the first semiconductor element, and the insulating layer exposes a part of the surface of the first semiconductor element, and the conductive layer is formed on the insulating layer. on.

In the foregoing semiconductor package and method of fabricating the same, the carrier is removed to expose the first surface of the first semiconductor component and the encapsulant. Therefore, the second circuit layer is formed on the second surface of the encapsulant, the second circuit layer is electrically connected to the first semiconductor component, and at least one second semiconductor component is disposed on the second circuit layer. The second circuit layer is electrically connected.

In the above semiconductor package and method of manufacturing the same, the carrier board is provided with at least one second semiconductor component, the encapsulant is overcoated with the second semiconductor component, and the second semiconductor component is electrically connected to the first component. Semiconductor component. For example, the conductive layer is extended and formed on the surface of the carrier and the surface of the second semiconductor component, so that the second semiconductor component is electrically connected to the first semiconductor component.

In addition, the carrier board has a line build-up structure, the first and second semiconductor components are disposed on the line build-up structure and electrically connected to the line build-up structure, and the second surface system of the package colloid Combined with the line build-up structure. The line build-up structure has at least one dielectric layer and a second circuit layer formed on the dielectric layer, the second circuit layer electrically connecting the first and second semiconductor elements.

It can be seen from the above that in the semiconductor package and the manufacturing method of the present invention, the design of the conductive layer, the technique of forming the opening by the encapsulant, and the RDL process on the encapsulant reduce the process steps to reduce the cost, and Can achieve the purpose of product miniaturization.

Furthermore, compared with the wire bonding process, the present invention does not need to consider the height of the arc, so the height of the encapsulant can be reduced to facilitate the miniaturization of the product.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "bottom", "side", "first", "second" and "one" as used in this specification are also for convenience of description. Rather than limiting the scope of the invention, it is to be understood that the scope of the invention may be practiced. For example, in the present invention, the "first" of the first semiconductor element refers to the semiconductor element stacked on the carrier board, and does not define that all of the first semiconductor elements are the same element or wafer.

2A to 2F are cross-sectional views showing a first embodiment of the method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, the plurality of first semiconductor elements 21 are stacked on a carrier 20 in a stepped stack.

In this embodiment, the type of the carrier board 20 can be selected according to requirements, for example, only has a carrying function, a heat dissipating function, an electric function, etc., and in this embodiment, it is only used for carrying, so Quartz plate.

Furthermore, the carrier 20 is bonded to the first semiconductor element 21 of the lowermost layer by a fixing layer 200, and the fixing layer 200 is of various kinds, for example, an optical film (such as a UV film), a rubber layer, and a release film. The release film or the like is not particularly limited, and in the present embodiment, an optical film such as a UV film is exemplified.

Moreover, the first semiconductor elements 21 are memory chips and have a plurality of electrode pads 210, and the first semiconductor elements 21 are also bonded by an adhesive layer 211.

In addition, there are many ways to stack the first semiconductor elements 21, such as vertically aligned stacks, and are not limited to the above.

As shown in FIG. 2B, a conductive layer 22 is formed on the surface of the first semiconductor elements 21 to electrically connect the electrode pads 210 through the conductive layer 22, so that the first semiconductor elements 21 are mutually connected. Electrically conductive.

In this embodiment, the conductive layer 22 is a metal layer. For example, the conductive layer 22 is formed by a nano metal (such as nano silver) printing technique, and the conductive layer 22 is formed along the first semiconductor elements 21 . The stepped structure is disposed on the side surface of the electrode pad 210 and the first semiconductor elements 21.

In addition, an insulating layer (not shown) may be printed on the surface of the first semiconductor elements 21, and a plurality of openings may be formed on the insulating layer to expose the electrode pads 210 to be electrically conductive. And forming the conductive layer 22 on the insulating layer to select an object in which the first semiconductor elements 21 are electrically connected to each other; for example, the uppermost layer and the lowermost first semiconductor element shown in FIG. 2B 21 is electrically conductive, and the two first semiconductor elements 21 are electrically conductive.

As shown in FIG. 2C, following the process of FIG. 2B, an encapsulant 23 is formed on the carrier 20 to cover the first semiconductor component 21 and the conductive layer 22, and the encapsulant 23 has a first counterpart. The surface 23a (the upper surface in the drawing) and the second surface 23b (the lower surface in the drawing), and the second surface 23b are bonded to the fixing layer 200 of the carrier sheet 20.

Then, a plurality of openings 230 are formed on the first surface 23a of the encapsulant 23 by laser, so that at least one of the conductive layers 22 on the first semiconductor element 21 exposes the openings 230.

In the present embodiment, the first surface 23a of the encapsulant 23 is ablated out of the openings 230 by a UV laser ablation technique. Moreover, the openings 230 correspond to the conductive layer 22 on the electrode pad 210 of the first semiconductor element 21 of the uppermost layer.

Furthermore, compared with the wire bonding process, the present invention can reduce the height of the package glue 23 because it does not need to consider the height of the wire loop, thereby facilitating the miniaturization of the finished product.

As shown in FIG. 2D, a first circuit layer 24 is formed on the first surface 23a of the encapsulant 23 by a redistribution layer (RDL) process, and the first circuit layer 24 is opened. The hole 230 is electrically connected to the electrode pad 210 and the conductive layer 22.

In this embodiment, the first circuit layer 24 is coupled with a plurality of conductive elements 240, such as solder balls, to electrically connect other semiconductor packages (not shown) or electronic devices such as circuit boards (not shown).

As shown in FIG. 2E, the carrier 20 is removed to expose the first semiconductor component 21 and the second surface 23b of the encapsulant 23 so that the bottom of the first semiconductor component 21 can directly dissipate heat outward.

In this embodiment, the carrier 20 is removed by an ultraviolet laser exposure and stripping technique, and the fixing layer 200 can be selectively left on the second surface 23b of the encapsulant 23 for protecting the wafer. Or removed along with the carrier board 20.

Furthermore, as shown in FIG. 2E', in the process of fabricating the conductive layer 22 shown in FIG. 2B, the conductive layer 22' can extend onto the surface of the carrier 20; After the board 20, a second wiring layer 25 is formed on the second surface 23b of the encapsulant 23 and the first semiconductor component 21 by using a redistribution wiring layer (RDL) process, so that the second wiring layer 25 is electrically The first semiconductor element 21 is connected.

Moreover, the present invention can greatly reduce the overall thickness of the finished product by removing the carrier plate 20 and the fixing layer 200, so as to facilitate the demand for thinning.

In addition, in other embodiments, if the carrier board 20 has a heat dissipation function (such as a heat dissipation structure) or other functions, the carrier board 20 need not be removed.

As shown in Fig. 2F or 2F', the process of continuing the 2E or 2E' process is performed by a singulation process along the dicing path Y as shown in Fig. 2E to form a plurality of semiconductor packages 2, 2'.

The conductive layer 22 is produced by the nano metal printing technology of the present invention. Compared with the prior art, the conductive layer 22 is not only low in cost, but also can increase the production capacity of the product (Unit Per Hour, UPH) due to the mature technology.

Furthermore, the formation of the openings 230 by the ultraviolet laser stripping technique can also reduce the cost and increase the production capacity of the product.

Moreover, the RDL process is performed on the first surface 23a of the encapsulant 23 to form the first circuit layer 24, and the RDL process is not required to be performed on each of the memory chips 11 as in the prior art, so that the RDL process can be effectively reduced. Cost and capacity increase, and the number of stacked chips is not limited.

In addition, if the process of FIG. 2E is continued, a second semiconductor component 26 having a plurality of electrode pads 260 may be disposed on the second surface 23b of the encapsulant 23, and the second semiconductor component 26 is electrically connected to the second semiconductor component 26. Two circuit layers 25 are formed to form a package on package (POP) as shown in FIG. 2F'. Further, after the test, the semiconductor package 2' and the second semiconductor element 26 are stacked to ensure the yield.

In this embodiment, the second semiconductor component 26 is a logic control wafer. Since the second semiconductor component 26 is first tested and then stacked on the germanium wafer, the process problems caused by the back end thermal process can be reduced, such as The coefficient of thermal expansion (CTE) is less affected to avoid affecting the overall electrical yield of the finished product.

Please refer to FIGS. 3A to 3C for a cross-sectional view showing a second embodiment of the method for fabricating the semiconductor package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the manner in which the second semiconductor component 36 is disposed and electrically connected, and the other related processes are substantially the same, and the same process will not be described again.

As shown in FIG. 3A, when the first semiconductor elements 21 are stacked, at least one second semiconductor component 36 having a plurality of electrode pads 360 is disposed on the carrier 20, and the second semiconductor component 36 is located thereon. The side of the stepped structure formed by the first semiconductor elements 21 is formed.

Then, a conductive layer 32 is formed on the surface of the first semiconductor component 21, the surface of the carrier 20, and the surface of the second semiconductor component 36, so that the second semiconductor component 36 is electrically connected by the conductive layer 32. The first semiconductor element 21 is connected.

The electrical connection between the first and second semiconductor elements 21, 36 is various, and is not limited to the above, and may be wired or the second circuit layer 25 of the second embodiment.

As shown in FIG. 3B, the packaging process and the RDL process as shown in FIGS. 2C to 2D are performed.

As shown in FIG. 3C, the carrier 20 is removed to expose the second surface 23b of the encapsulant 23, the portion of the conductive layer 32, the first and second semiconductor elements 21, 36, and then perform a singulation process.

Furthermore, a redistribution wiring layer (RDL) process may be performed on the second surface 23b of the encapsulant 23 to electrically connect the second wiring layer (not shown) to the first and second semiconductor components 21, 36, and the second circuit layer can be externally connected to other electronic components (not shown).

Moreover, in the present invention, by providing the second semiconductor element 36 on the side of the stepped structure formed by the first semiconductor elements 21, the height of the overall structure can be reduced to overcome the influence of the bottleneck of the wafer polishing technology. Therefore, the design is conducive to the demand for thinning products.

In addition, even if the first and second semiconductor elements 21, 36 are electrically connected by wire bonding, the arc height does not affect the overall structure height, so that the thinning requirement can be achieved.

4A to 4B are cross-sectional views showing a third embodiment of the method of fabricating the semiconductor package 4 of the present invention. The difference between this embodiment and the second embodiment lies in the position of the second semiconductor component 46, the process of the second circuit layer 45, and the first circuit layer 44. The other related processes are substantially the same, and the same process will not be described again.

As shown in FIGS. 4A and 4A', a line build-up structure is formed on the carrier board 40. The line build-up structure has at least one dielectric layer 40a and a second circuit layer 45 disposed on the dielectric layer 40a. .

In this embodiment, the second circuit layer 45 has a plurality of electrical connection pads 45a, 45b, and the electrical connection pads 45a, 45b can be wire bonding pads, flip chip pads or other types.

Furthermore, the structure of the line build-up structure is numerous and is not limited to the aspects in the drawings, and is hereby stated.

As shown in FIG. 4B, in the subsequent process, the second semiconductor element 46 is disposed in the housing space S below the stepped structure formed by the first semiconductor elements 21, and the first semiconductor elements 21 are The electrical connection pad 45 is electrically connected to the electrical connection pad 45a, and the electrode pad 460 of the second semiconductor component 46 is electrically connected to the electrical connection pad 45b by a bonding wire 47.

Thereafter, the carrier plate 40 is removed. If the carrier plate 40 is made of a metal material, since it can serve as a heat dissipation plate, the carrier plate 40 need not be removed.

In this embodiment, the first circuit layer 44 is embedded in the first surface 23a of the encapsulant 23, and the second semiconductor component 46 is a control wafer.

Moreover, since the width of the conductive layer 42 is much smaller than that of the prior art, the distance between the electrical connection pads 45a on the carrier 40 can be greatly reduced, so that the size of the carrier 40 can be adjusted. The demand is reduced, which in turn reduces the size of the encapsulant 23, thereby facilitating the miniaturization of the finished product.

Moreover, when more wafers are stacked in a stepped manner, the second semiconductor component 46 can be placed by the storage space S below the stepped structure to effectively utilize the area on the carrier board 40, thereby avoiding the formation of the prior art. No action area.

In addition, placing the second semiconductor component 46 in the storage space S can reduce the use area of the carrier 40 (ie, the use area of the dielectric layer 40a) and reduce the height of the overall structure to overcome the wafer polishing technology. The impact of the bottleneck, so the design is conducive to the need for miniaturization of finished products.

The present invention further provides a semiconductor package 2, 2', 3, 4 comprising: an encapsulant 23 having a first surface 23a and a second surface 23b opposite thereto, stacked on each other and embedded in the encapsulant 23 The first semiconductor component 21, the conductive layers 22, 22', 32, 42 embedded in the encapsulant 23, and the first circuit layers 24, 44 formed on the first surface 23a of the encapsulant 22.

A plurality of openings 230 are formed on the first surface 23a of the encapsulant 23 .

The stacking manner of the first semiconductor elements 21 is a stepped stack.

The conductive layers 22, 22', 32, 42 are formed on the surfaces of the first semiconductor elements 21 to electrically conduct the first semiconductor elements 21, and the first semiconductor element 21 of the uppermost layer A portion of the conductive layers 22, 22', 32, 42 are exposed to the opening 230. Further, the surface of the first semiconductor component 21 may have an insulating layer (not shown), and the insulating layer exposes a part of the surface of the first semiconductor component, so that the conductive layer 22, 22', 32, 42 is formed in the insulating layer. The layer and the first semiconductor element 21 are exposed to the surface.

The first circuit layer 24, 44 is electrically connected to the first semiconductor component 21 and the conductive layer 22, 22', 32, 42 via the openings 230, and the first circuit layer 44 is selectively embedded. Buried in the first surface 23a of the encapsulant 23.

In one embodiment of the semiconductor package 2, 2', the first semiconductor component 21 is exposed on the second surface 23b of the encapsulant 23.

In an embodiment of the semiconductor package 2 ′, a second circuit layer 25 is disposed on the second surface 23 b of the encapsulant 23 for bonding a second semiconductor component 26 , and the second semiconductor The element 26 can be electrically connected to the first semiconductor element 21 by the second circuit layer 25.

In the embodiment of the semiconductor package 3, the second semiconductor component 36 is embedded in the second surface 23b of the encapsulant 23 and electrically connected to the first semiconductor component 21, for example, the conductive The layer 32 is extended on the second surface 23b of the encapsulant 23 and the surface of the second semiconductor component 36, so that the second semiconductor component 36 is electrically connected to the first semiconductor component 21 by the conductive layer 32. Furthermore, the second circuit layer 25 can also be electrically connected to the second semiconductor component 36.

In one embodiment of the semiconductor package 4, a circuit build-up structure is formed on the second surface 23b of the encapsulant 23 and electrically connected to the first and second semiconductor elements 21, 46.

The circuit layer-forming structure has at least one dielectric layer 40a and a second circuit layer 45 disposed on the dielectric layer 40a. The second circuit layer 45 is electrically connected to the first and second semiconductor elements 21, 46.

Further, the embedded second semiconductor elements 36, 46 may be located on the side of the stepped structure formed by the first semiconductor elements 21 or the storage space S below the stepped structure.

In summary, the semiconductor package and the method of the present invention mainly utilize the design of the conductive layer, the technique of forming the opening by the encapsulant, and the RDL process on the encapsulant to reduce the cost and improve the product of the wire structure. The competitiveness, and avoid the impact of the logic control chip yield rate on the overall product yield, and can achieve the purpose of product miniaturization.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1,1',2,2',3,4. . . Semiconductor package

10,20,40. . . Carrier board

100, 45a, 45b. . . Electrical connection pad

11. . . Memory chip

110,210,260,360,460. . . Electrode pad

12,47. . . Welding wire

12’. . . Conductive colloid

200. . . Fixing layer

twenty one. . . First semiconductor component

211. . . Adhesive layer

22,22’,32,42. . . Conductive layer

twenty three. . . Encapsulant

23a. . . First surface

23b. . . Second surface

230. . . Opening

24,44. . . First circuit layer

240. . . Conductive component

25,45. . . Second circuit layer

26,36,46. . . Second semiconductor component

40a. . . Dielectric layer

D. . . spacing

L. . . Inactive area

S. . . Storage space

Y. . . Cutting path

1A and 1B are schematic cross-sectional views of different embodiments of a conventional semiconductor package; wherein, the 1B' is a top view of the carrier plate of FIG. 1B;

2A to 2F are schematic cross-sectional views showing a first embodiment of a method of fabricating a semiconductor package of the present invention; wherein the second embodiment EE and 2F' are another embodiment of the second and second embodiments;

3A to 3C are schematic cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package of the present invention;

4A to 4B are schematic cross-sectional views showing a third embodiment of the method of fabricating a semiconductor package of the present invention; wherein the 4A' is a top view of Fig. 4A.

2. . . Semiconductor package

twenty one. . . First semiconductor component

twenty two. . . Conductive layer

twenty three. . . Encapsulant

23a. . . First surface

23b. . . Second surface

230. . . Opening

twenty four. . . First circuit layer

Claims (27)

A semiconductor package comprising: an encapsulant having opposite first and second surfaces, and at least one opening formed on a first surface of the encapsulant; and the plurality of first semiconductor elements stacked on each other and Buried in the encapsulant, each of the first semiconductor elements has a plurality of electrode pads, the first semiconductor elements stacked to expose the plurality of electrode pads; and a conductive layer formed on the first semiconductor elements The surface of the structure and the surface of the electrode pad electrically electrically connect the first semiconductor elements, and at least one of the conductive layers on the first semiconductor element exposes the opening; and the first circuit layer is formed on the encapsulant The first surface is electrically connected to the conductive layer via the opening. The semiconductor package of claim 1, wherein the first semiconductor elements are stacked in a stepped manner. The semiconductor package of claim 1, wherein the first semiconductor element has an insulating layer on a surface thereof, and the insulating layer exposes a portion of the surface of the first semiconductor element, and the conductive layer is formed on the insulating layer. The exposed surface of the first semiconductor element is electrically connected to the layer. The semiconductor package of claim 1, wherein the first semiconductor component is exposed on a second surface of the encapsulant. The semiconductor package of claim 1, further comprising a second circuit layer disposed on the second surface of the encapsulant and electrically The first semiconductor component is connected to the first. The semiconductor package of claim 5, further comprising at least one second semiconductor component disposed on the second circuit layer and electrically connected to the second circuit layer. The semiconductor package of claim 1, further comprising at least one second semiconductor component embedded in the second surface of the encapsulant. The semiconductor package of claim 7, wherein the second semiconductor component is electrically connected to the first semiconductor component. The semiconductor package of claim 8, wherein the conductive layer is formed on the second surface of the encapsulant and the surface of the second semiconductor component, and the second semiconductor component is electrically connected to the second semiconductor component. A semiconductor component. The semiconductor package of claim 7, further comprising a line build-up structure formed on the second surface of the encapsulant and electrically connected to the first and second semiconductor elements. The semiconductor package of claim 10, wherein the circuit build-up structure has at least one dielectric layer and a second circuit layer disposed on the dielectric layer, the second circuit layer being electrically connected The first and second semiconductor elements. The semiconductor package of claim 10, further comprising a heat dissipation structure disposed on the line buildup structure. The semiconductor package of claim 1, further comprising a heat dissipation structure disposed on the second surface of the encapsulant. A method of fabricating a semiconductor package, comprising: stacking a plurality of first semiconductor elements on a carrier board, each of the first semiconductor elements having a plurality of electrode pads, wherein the stacked first semiconductor elements expose the plurality of electrode pads; Forming a conductive layer on the surface of the first semiconductor element and forming a conductive layer on the surface of the electrode pad to electrically conduct the first semiconductor elements; forming an encapsulant on the carrier plate to cover each of the first semiconductor elements and a conductive layer, and the encapsulant has an opposite first surface and a second surface, the second surface is bonded to the carrier plate; and at least one opening is formed on the first surface of the encapsulant to make at least one of the a portion of the conductive layer on a semiconductor component exposes the opening; and a first circuit layer is formed on the first surface of the encapsulant, and the first circuit layer is electrically connected to the conductive layer via the opening. The method of fabricating a semiconductor package according to claim 14, wherein the stacking of the first semiconductor elements is a stepped stack. The method of fabricating a semiconductor package according to claim 14, further comprising forming an insulating layer on a surface of the first semiconductor elements before forming the conductive layer, and the insulating layer exposes a portion of the first semiconductor device The surface is such that the conductive layer is formed on the insulating layer. The method of fabricating a semiconductor package as described in claim 14 includes removing the carrier. The method of fabricating a semiconductor package according to claim 17, further comprising forming a second wiring layer on the second surface of the encapsulant, and the second wiring layer is electrically connected to the first semiconductor component. The method of fabricating a semiconductor package according to claim 18, further comprising: placing at least one second semiconductor component on the second circuit layer, wherein the second semiconductor component is electrically connected to the second circuit layer. The method of fabricating a semiconductor package according to claim 14, wherein the carrier board is provided with at least one second semiconductor component, and the encapsulant is overcoated with the second semiconductor component. The method of fabricating a semiconductor package according to claim 20, wherein the second semiconductor component is electrically connected to the first semiconductor component. The method of manufacturing a semiconductor package according to claim 21, wherein the conductive layer is further formed on a surface of the carrier and a surface of the second semiconductor component, and the second semiconductor component is electrically connected to the second semiconductor component. A semiconductor component. The method of manufacturing a semiconductor package according to claim 20, wherein the carrier board has a line build-up structure, and the first and second semiconductor elements are disposed on the line build-up structure and electrically The line build-up structure is connected, and the second surface of the encapsulant is combined with the line build-up structure. The method of fabricating a semiconductor package according to claim 23, wherein the circuit build-up structure has at least one dielectric layer and a second circuit layer formed on the dielectric layer, the second circuit layer is electrically The first and second semiconductor elements are connected to each other. The method of fabricating a semiconductor package according to claim 23, wherein the carrier is a heat dissipation structure. The method of fabricating a semiconductor package according to claim 14, wherein the carrier is a heat dissipation structure. The method of fabricating a semiconductor package according to claim 14, wherein the opening is formed by laser.