TW201603201A - Embedded package and packaging method - Google Patents

Abstract

The present invention discloses a embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.

Description

Embedded package and packaging method 【0001】

The present invention relates to a semiconductor package technology, and more particularly to an embedded package and package method for a lead frame, a ruthenium or a prefabricated wafer, and a copper metal sheet using a pre-filled seal.

【0002】

As shown in Figure 1, NXP has produced an embedded power field effect transistor (power MOSFET) technology in which the power field effect transistor (MOSFET) 11 is provided with a plating layer on both sides (upper plating layer 12 and lower plating layer). 13) The upper plating layer 12 is spaced apart from the drain region 121, the gate region 122 and the source region 123, wherein the gate region 122 and the source region 123 of the upper plating layer 12 respectively communicate with the gate and the source of the power MOSFET . The drain region 121 of the upper plating layer is connected to the lower plating layer 13, and the drain of the power MOSFET is led to the drain region 121 of the upper plating layer by the connection of the upper plating layer 12 and the lower plating layer 13, thereby realizing the power MOSFET device. The drain, gate and source are all placed on one side for easy packaging and the wafer package can be made thinner. In NXP's embedded power field effect transistor wafer, the field effect transistor wafer has a thickness of 150 microns, and the wafer solder patch is on a 36 micron copper foil. The entire package thickness is 200 microns and the size is 3.2 mm x 3.2. Millimeter.

[0003]

As shown in FIG. 2, AOS Corporation has produced a multi-chip power MOSFET package technology including a lead frame 21, a clip 22, and a pre-molded chip. The bottom layer is provided with a lead frame 21, the wafers 24 and 34 are disposed on the lead frame 21, the wafers 24 and 34 are provided with a metal piece 22, and the metal piece 22 is provided with a wafer 23. The metal piece 22 is electrically connected to the lead frame 21, and the wafer 35 is a prefabricated wafer provided with a silicon flip bond having a thickness of 100 μm, and the wafer 2 and the wafer 35 are bonded by a metal piece 22 The wafer one is an integrated circuit wafer which is connected to a lead by gold wire bonding. The entire package has a thickness of 1.1 mm and a size of 3.5 mm x 5 mm.

[0004]

NXP's packaging technology has a flexible package design; it achieves a very thin package technology; it is easier to implement system-in-package (SIP) under such a platform, but its disadvantage is that it has no good performance, the device The resistance is 7 to 8 milliohms; for high-power devices, the phenomenon of heat is severe.

[0005]

The above AOS company packaging technology has the advantages of better electrical and thermal performance; thinner die package by using prefabricated wafers; and good compatibility with conventional packaging processes. However, the disadvantage is that due to the line arc height and stacked structure of the wire, its technology cannot achieve a thin package; it is very difficult to implement system-in-package (SIP) in the subsequent process; due to the wire bond process Limiting the inflexible package design; the difficulty of wire bonding (WB) after solder cleaning process, low package yield, high cost, inflexibility; complex structure of lead frame and high temperature packaging technology The warpage deformation caused in the film also causes the problem of the mold flash; the power chip and the logic chip interconnection require expensive gold wires, and the cost is too high.

[0006]

The invention provides an embedded packaging and packaging method, which realizes high electrical performance performance and flexible packaging in a multi-wafer connected power field effect transistor and a logic chip hybrid device, and has better heat by reducing on-resistance and reducing power loss. Management performance, system-level packaging, reliability, low cost and compact size.

【0007】

To achieve the above object, the present invention provides an embedded package, comprising: a lead frame of pre-filled sealing material, and a plurality of wafers disposed thereon; a plurality of pins disposed around the lead frame; and a lead frame The molding material fills the lead frame hollow structure, so that the lead frame is formed into a plane without hollowing out; the metal piece is disposed on a part of the plurality of wafers, and the chips are electrically connected by the metal piece; the metal piece is electrically connected at one end To a pin; a first laminate layer overlying the wafer, the lead frame, the metal piece and the lead; corresponding to the pin and the area of each of the wafers for connecting the respective pins, the first laminate layer Providing via holes from the surface of the wafer or the leads to the outer surface of the first laminate; each of the vias is plated with a metal to form a conductive structure; and the conductive structures on the regions of the respective pads to be connected to the pins are respectively separated from the regions The conductive structures on the corresponding pins are electrically connected; or each wafer is electrically connected to other wafers by a corresponding conductive structure.

[0008]

A plurality of the above wafers include a first wafer, a second wafer, and a third wafer.

【0009】

The first wafer is a logic wafer.

[0010]

The first wafer is bonded to the lead frame by epoxy, and the top is respectively connected to the corresponding pin by a plurality of conductive structures.

[0011]

The second wafer is a MOSFET power chip.

[0012]

The bottom of the second wafer is electrically connected to the lead frame, and the top gate and the top source are respectively connected to corresponding pins by conductive structures.

[0013]

The third wafer is a MOSFET power flip chip.

[0014]

The bottom gate and the source of the third wafer are respectively provided with solder balls, and the lead frame is electrically connected by solder balls.

[0015]

The lead frame is connected to the gate of the third chip to be provided with a gate pin, and the solder ball at the gate of the third chip is connected to the gate pin.

[0016]

The lead frame includes a first stage and a second stage which are disposed separately, the first wafer and the second wafer are disposed on the first stage; and the third wafer is disposed on the second stage.

[0017]

The metal piece is disposed on the drain of the second wafer and the source of the third wafer, and the drain of the second wafer and the source of the third wafer are electrically connected by the metal piece.

[0018]

The above metal piece is a metal piece having a conductive property.

[0019]

The above metal piece is a copper piece or a nickel piece.

[0020]

The first laminate layer is a PP layer.

[0021]

The first laminate layer is further provided with a second laminate layer, and the second laminate layer is coated on the conductive structure and the extended portion thereof.

[0022]

The second laminate layer is a PP layer.

[0023]

The via hole is tapered, and the diameter of one end of the surface of the connecting wafer or the lead is smaller than the diameter of one end of the outer surface of the first laminate.

[0024]

The surface of the first laminate layer is further provided with a heat dissipation metal foil, and the heat dissipation metal foil is disposed at a position corresponding to the metal sheet or the wafer.

[0025]

The above heat dissipating metal foil is made of a metal having good thermal conductivity.

[0026]

The above heat dissipating metal foil is made of copper or aluminum.

[0027]

A plurality of intermediate laminate layers are further stacked between the first laminate layer and the second laminate layer.

[0028]

The above intermediate laminate layer is provided with electronic devices.

[0029]

A package method for an embedded package as described above, characterized in that the method comprises the steps of: placing a wafer patch on a lead frame of a pre-filled sealing material, and laying the first on the set wafer, lead frame and leads a laminate layer; corresponding to a region where the chip is to be connected to a pin and a corresponding pin, the first laminate layer is drilled through the hole, and a conductive structure is formed in each via hole, and the conductive structure is extended by the surface of the wafer or the lead To the surface of the first laminate layer; the conductive structures on the regions of the respective pads to be connected to the leads are electrically connected to the conductive structures on the corresponding pins of the regions; or the corresponding conductive between the wafers and the other wafers Structural electrical connection.

[0030]

Before the first laminate layer is drilled through the hole, a conductive layer is pre-laminated on the first laminate layer; after the conductive structure is formed in the via hole, the conductive layer is etched to form the wafer and its corresponding pins or other wafers. Electrical connection between the conductive structures.

[0031]

When the first laminate layer is laid, the first laminate layer has a metal foil on one side; after the conductive structure is formed in the via hole, the metal foil is etched to form a conductive structure of the wafer and its corresponding pin or other wafer. Electrical connection between the lines.

[0032]

After the electrical connection between the conductive structures is completed, a second laminate layer is laid over the first laminate layer, and the second laminate layer covers the conductive structures and their electrically connected lines.

[0033]

Before laying the first laminate layer, a metal piece is disposed on the plurality of power chips to realize electrical connection between the power chips, and the metal piece is more electrically connected to the corresponding pin.

[0034]

An embedded packaging and packaging method of the present invention has the advantage over the multi-chip packaging technology of the prior art in that the present invention mounts the multi-wafer on the lead frame of the pre-filled sealing material and is embedded in the laminated layer. In the process, each MOSFET power chip is connected by a metal piece, and the power chip, the integrated circuit chip and the pin are interconnected by the via plating metal to realize the hybrid integration of the power chip and the logic chip; the package thickness is reduced, the single chip The layer can be controlled within 650 microns, the thickness of the stacked wafer can be controlled within 900 microns; the thermal insulation performance is enhanced by the interconnection of metal layers, achieving better thermal and electrical properties; pre-filled sealing lead frame and lamination The layer design facilitates the flexible power and logic hybrid design; the three-dimensional stacking capability enables system-level packaging; the pre-filled sealing material lead frame has a fixed effect on the soldering position of the patch, which can prevent solder bridging and improve soldering quality; The pre-filled sealing lead frame is a closed, non-hollowed structure that allows for a good lamination technique.

【0121】

11‧‧‧Power field effect transistor
111‧‧‧Electrical connection lines
12‧‧‧Upper plating
121‧‧‧Bungee Area
122‧‧‧The gate area
123‧‧‧ source area
13‧‧‧Under plating
131, 151, 181‧‧ ‧ heat dissipation layer
171‧‧‧First power chip
172‧‧‧second power chip
173‧‧‧Logical Wafer
174‧‧‧ Passive devices
175‧‧‧Intermediate laminate
176‧‧‧copper island
21, 31‧‧‧ lead frame
22, 36‧‧‧metal pieces
23‧‧‧ wafer one
24‧‧‧ wafer two
25‧‧‧ wafer three
311‧‧‧First stage
312‧‧‧Second stage
32, 32'‧‧‧ pin
33‧‧‧First chip
34‧‧‧second chip
35‧‧‧ Third chip
37‧‧‧First laminate
38‧‧‧Second laminate
41, 42‧‧‧ Via
43,44‧‧‧Electrical structure
45‧‧‧gate pin
51‧‧‧Electroplating extension
91‧‧‧ Conductive layer

[0035]

FIG. 1 is a schematic diagram of a package structure of an embedded power field effect transistor in the prior art.
FIG. 2 is a schematic diagram of a multi-chip package structure of a prefabricated lead frame in the prior art.
FIG. 3 is a schematic structural view of the embedded package of the first embodiment of the present invention.
Fig. 4 is a cross-sectional view taken along line AA of Fig. 3 of the first embodiment.
Fig. 5 is a cross-sectional view taken along line BB of Fig. 3 of the first embodiment.
Figure 6 is a schematic view showing the second wafer and the third wafer patch in the embedded packaging method of the present invention.
Figure 7 is a schematic view showing the connection of metal sheets in the embedded packaging method of the present invention.
FIG. 8 is a schematic diagram of a first wafer patch in the embedded packaging method of the present invention.
Figure 9 is a schematic view showing the preparation of the first laminate layer and the conductive layer in the embedded packaging method of the present invention.
FIG. 10 is a schematic view showing an etched through hole in the embedded packaging method of the present invention.
11 is a schematic view showing the preparation of a conductive structure in the embedded packaging method of the present invention.
Figure 12 is a schematic view showing the preparation of the second laminate layer in the embedded packaging method of the present invention.
Figure 13 is a cross-sectional view along line AA of Figure 3 of the second embodiment of the present invention.
Figure 14 is a cross-sectional view taken along line BB of Figure 3 of the second embodiment of the present invention.
Fig. 15 is a cross-sectional view along line AA of Fig. 3 of the third embodiment of the present invention.
Figure 16 is a cross-sectional view taken along line BB of Figure 3 of the third embodiment of the present invention.
Figure 17 is a plan view showing a fourth embodiment of the embedded package of the present invention.
Figure 18 is a cross-sectional view taken along line AA of Figure 17.

[0036]

Specific embodiments of the present invention are further described below in conjunction with the drawings.

[0037]

Example 1:

[0038]

As shown in FIG. 3, it is a schematic diagram of the embedded package of the first embodiment, which comprises a pre-mold leadframe (pre-mold LDF) 31, and the lead frame 31 is made of copper. After being subjected to nickel plating, silver plating or gold plating, the lead frame 31 is provided with the first stage 311 and the second stage 312 having the same thickness on the same plane. A plurality of pins 32 are surrounded around the first stage 311 and the second stage 312, and some of the pins are separated from the first stage 311 or the second stage 312 and are electrically connected. They are connected to the first stage 311 or the second stage 312, respectively. The molding material on the lead frame fills the lead frame hollow structure, so that the lead frame forms a plane without hollowing out. The thickness of the molding material is the same as the thickness of the first stage 311 and the second stage 312.

[0039]

A first wafer 33 and a second wafer 34 are disposed on the first stage 311, and a third wafer 35 is disposed on the second stage 312. The first wafer 33 is a logic IC chip, the second wafer 34 is a MOSFET power chip, and the third wafer 35 is a MOSFET power flip chip. As shown in the figure, the first wafer 33 and the second wafer 34 are electrically connected, and the first wafer 33 and the second wafer 34 are electrically connected to respective ones of the plurality of pins 32, respectively.

[0040]

A clip 36 is disposed on the second wafer 34 and the third wafer 35, and the metal sheet 36 is in contact with and electrically connected to the top surfaces of the second wafer 34 and the third wafer 35, respectively, and the metal sheet 36 is not fully covered. The top surface of the second wafer 34 and the third wafer 35 cover only the portion of the top surface of the second wafer 34 and the third wafer 35 that needs to be connected to the lead, for example, the metal piece 36 is electrically connected to the top surface of the second wafer 34, The source of the top surface of the third wafer 35. The other end of the metal piece 36 is bonded to a pin 32' to effect electrical connection between the top surface of the second wafer 34 and the third wafer 35 and the pin 32. Preferably, the metal piece 36 is made of a copper piece, a nickel piece or other metal piece having a conductive property.

[0041]

As shown in FIG. 4 and in conjunction with FIG. 5, the first laminate 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal sheet 36, and the leads 32 are coated with the first laminate layer 37. The first laminate layer 37 employs a PP layer that fills the gap between the first wafer 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36, and the leads 32, and will be first The wafer 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36, and the lead 32 are hermetically sealed, and the structural dimensions of the first laminate layer 37 and the dimensions of the lead frame 31 and the leads 32 are enclosed. It is flush with the structure.

[0042]

As shown in FIG. 4 and in conjunction with FIG. 3, the first wafer 33 is bonded to the first stage 311 of the lead frame 31 by epoxy bonding. A hole is etched at a region on the top surface of the first wafer 33 corresponding to the connection pin 32 to form a via 41 from the surface of the first wafer 33 to the outer surface of the first laminate layer 37, while at the corresponding pin 32, A laminate layer also etches the vias to form vias 42 from the surface of the leads 32 to the outer surface of the first laminate layer 37. Metal is plated in the via holes 41, 42, respectively, to form conductive structures 43, 44, respectively. On the outer surface of the first laminate layer 37, the conductive structure 43 connected to a certain area of the first wafer 33 and the conductive structure 44 of the corresponding pin 32 of the area are plated and electrically connected to each other, thereby making the first wafer 33 The specific area is electrically connected to its corresponding pin 32.

[0043]

As shown in FIG. 5 and in conjunction with FIG. 3, the bottom of the second wafer 34 is electrically connected to the first stage 311 of the lead frame 31 by soldering. A gate or source region at the top of the second wafer 34 is etched into the first laminate layer 37 to form vias from the surface of the second wafer 34 to the outer surface of the first laminate layer 37, while correspondingly At the foot 32, the first laminate layer also etches the vias to form vias from the surface of the leads 32 to the outer surface of the first laminate layer 37. Metal is plated in each via to form a conductive structure. On the outer surface of the first laminate layer 37, the conductive structure connected to the gate or source region of the second wafer 34 and the conductive structure of the corresponding pin of the region are plated and electrically connected to each other, thereby electrically connecting the second wafer. A particular region of 34 is electrically coupled to its corresponding pin 32.

[0044]

At the same time, the first wafer 33 is further electrically connected to the second wafer 34 by the above-mentioned conductive structure.

[0045]

Preferably, the via hole drilled by the first laminate layer 37 is tapered, and the diameter of one end of the surface of the connecting wafer or the lead is smaller than the diameter of one end of the outer surface of the first laminate.

[0046]

As shown in FIG. 4 and in conjunction with FIG. 5, the third wafer 35 is disposed on the second stage 312 of the lead frame 31. The third wafer 35 is a MOSFET power flip chip, and the bottom portion is provided with a regulation. The third wafer 35 is electrically connected to the lead frame 31 by the solder balls. The bottom gate and the source of the third wafer 35 are respectively provided with solder balls, and are electrically connected by solder balls. Lead frame.

[0047]

A gate pin 45 (a groove shown in the figure) is disposed at a gate of the lead frame 31 correspondingly connected to the third wafer 33, and a solder ball at a gate of the third wafer 33 is disposed in the gate pin 45 to ensure The solder balls do not roll freely on the plane of the second stage 312.

[0048]

Further disposed on the first laminate layer 37 is a second laminate layer 38 overlying all of the conductive structures and their extensions, as well as the outer surface of the first laminate layer 37. The second laminate layer 38 has the same structural dimensions as the first laminate layer 37, and the second laminate layer 38 has a smaller thickness than the first laminate layer 37. The second laminate layer 38 is also formed from a PP layer, and the second laminate layer 38 hermetically encapsulates the outer surface of the first laminate layer 37 and the conductive structure to complete the completed package structure.

[0049]

As shown in FIGS. 6 to 12, the present invention further discloses a package method for the above-described embedded package, and FIGS. 6 and 7 are cross-sectional views of the AA plane in FIG. 3 in the packaging process, and FIGS. 8 to 12 are packaging processes. A cross-sectional view of the BB plane in the third diagram.

[0050]

The encapsulation method includes the following steps:

[0051]

First, the lead frame 31 is prefabricated, and the lead frame 31 includes a first stage 311 and a second stage 312 which are disposed apart from each other, and pins are disposed around the first stage 311 and the second stage 312. 32, a part of the pin 32 is electrically connected to the first stage 311 or the second stage 312, and is partially separated from the first stage 311 or the second stage 312. The lead frame 31 is pre-filled with a molding material, and the molding material on the lead frame fills the hollow frame of the lead frame 31 so that the lead frame 31 forms a flat surface without voiding. The thickness of the molding material is the same as the thickness of the first stage 311 and the second stage 312.

[0052]

As shown in FIG. 6, the bottom of the second wafer 34 is electrically connected to the first stage 311 of the lead frame 31 by soldering; the third wafer 35 is soldered to the lead frame 31 by a solder ball dot on the bottom surface thereof. On the second stage 312. The second wafer 34 and the third wafer 35 are power chips.

[0053]

As shown in FIG. 7, metal sheets 36 are disposed on the second wafer 34 and the third wafer 35, and the metal sheets 36 are electrically connected to the drains of the second wafer 34 and the source of the third wafer 35, respectively. One end of 36 is more bonded to the corresponding pin 32'. The electrical connection between the second wafer 34 and the third wafer 35 and the electrical connection between the second wafer 34 and the third wafer 35 and the pins 32' are realized.

[0054]

As shown in Fig. 8, the first wafer 33 is bonded to the first stage 311 of the lead frame 31 by epoxy. The first wafer 33 is a logic wafer.

[0055]

As shown in FIG. 9, the first laminate layer 37 is laid on the provided first wafer 33, second wafer 34, third wafer 35, lead frame 31, and leads 32. The first laminate layer 37 hermetically encapsulates the first wafer 33, the second wafer 34, the third wafer 35, and the leads 32, and the length and width structure of the first laminate layer 37 and the length and width dimensions of the lead frame 31. The same and completely covering the upper surface of the lead frame 31. The first laminate layer 37 is a PP layer such as a BT resin.

[0056]

After the first laminate layer 37 is completed, a conductive layer 91 is electroplated on the first laminate layer 37.

[0057]

Alternatively, the first laminate layer 37 is a PP plate of a predetermined copper foil, wherein the copper foil can be etched as needed to serve as the conductive layer.

[0058]

As shown in FIG. 10, corresponding to the areas where the first wafer 33 and the second wafer 34 are to be connected to the pins and the corresponding pins 32, the first laminate layer 37 is drilled through the holes, respectively.

[0059]

As shown in Fig. 11, the metal is plated in each via to form a conductive structure that extends from the surface of the wafer or pin to the surface of the first laminate layer 37. Preferably, the plating metal used to form the electrically conductive structure is copper.

[0060]

After the conductive structures are formed in the vias, the conductive layer 91 is etched to form electrical connection lines 111 between the conductive structures of the first wafer 33, the second wafer 34, and their corresponding leads 32. The conductive structure on the area of each of the wafers to which the pins are to be connected is electrically connected to the conductive structures on the corresponding pins of the respective areas.

[0061]

As shown in FIG. 12, after the electrical connection between the conductive structures is completed, a second laminate layer 38 is laid on the first laminate layer 37, and the second laminate layer 38 covers the conductive structure and its electrical connection lines. . At the same time, the structural dimension of the second laminate layer 38 is the same as that of the first laminate layer 37, and the thickness of the second laminate layer 38 is smaller than the thickness of the first laminate layer 37. The second laminate layer 38 is also a PP layer.

[0062]

After the second laminate layer 38 is laid, the complete packaging process is completed.

[0063]

Example 2:

[0064]

Referring to the top view (Fig. 3), the cross-sectional view in the A-A direction (Fig. 13), and the cross-sectional view in the B-B direction (Fig. 14), this embodiment 2 discloses another embodiment of an embedded package. It comprises a pre-mold leadframe (pre-mold LDF) 31, the lead frame 31 is made of copper, and the surface can be nickel-plated, silver-plated or gold-plated, and the lead frame 31 is The first stage 311 and the second stage 312 having the same thickness are disposed on the same plane. A plurality of pins 32 are surrounded around the first stage 311 and the second stage 312, and some of the pins are separated from the first stage 311 or the second stage 312 and are electrically connected. They are connected to the first stage 311 or the second stage 312, respectively. The molding material on the lead frame fills the lead frame hollow structure, so that the lead frame forms a flat surface without hollowing out.

[0065]

A first wafer 33 and a second wafer 34 are disposed on the first stage 311, and a third wafer 35 is disposed on the second stage 312. The first wafer 33 is a logic IC chip, the second wafer 34 is a MOSFET power chip, and the third wafer 35 is a MOSFET power flip chip. As shown in the figure, the first wafer 33 and the second wafer 34 are electrically connected, and the first wafer 33 and the second wafer 34 are electrically connected to respective ones of the plurality of pins 32, respectively.

[0066]

A clip 36 is disposed on the second wafer 34 and the third wafer 35, and the metal sheet 36 is in contact with and electrically connected to the top surfaces of the second wafer 34 and the third wafer 35, respectively, and the metal sheet 36 is not fully covered. The top surface of the second wafer 34 and the third wafer 35 cover only the portion of the top surface of the second wafer 34 and the third wafer 35 that needs to be connected to the lead, for example, the metal piece 36 is electrically connected to the top surface of the second wafer 34, The source of the top surface of the third wafer 35. The other end of the metal piece 36 is bonded to a pin 32' to effect electrical connection between the top surface of the second wafer 34 and the third wafer 35 and the pin 32. Preferably, the metal piece 36 is made of a copper piece, a nickel piece or other metal piece having a conductive property.

[0067]

As shown in FIG. 13 and in conjunction with FIG. 14, the first laminate 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal sheet 36 and the leads 32 are coated with a first laminate layer 37. The first laminate layer 37 employs a PP layer that fills the gap between the first wafer 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36, and the leads 32, and will be first The wafer 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36, and the lead 32 are hermetically sealed, and the structural dimensions of the first laminate layer 37 and the dimensions of the lead frame 31 and the leads 32 are enclosed. It is flush with the structure.

[0068]

As shown in FIG. 13 and in conjunction with FIG. 3, the first wafer 33 is bonded to the first stage 311 of the lead frame 31 by epoxy bonding. A hole is etched at a region on the top surface of the first wafer 33 corresponding to the connection pin 32 to form a via 41 from the surface of the first wafer 33 to the outer surface of the first laminate layer 37, while at the corresponding pin 32, A laminate layer also etches the vias to form vias 42 from the surface of the leads 32 to the outer surface of the first laminate layer 37. Metal is plated in the vias 41, 42, respectively, to form conductive structures 43, 44, respectively, which may be copper. On the outer surface of the first laminate layer 37, the conductive structure 43 connected to a certain area of the first wafer 33 and the conductive structure 44 of the corresponding pin 32 of the area are plated and electrically connected to each other, thereby making the first wafer 33 The specific area is electrically connected to its corresponding pin 32.

[0069]

As shown in FIG. 14 and in conjunction with FIG. 3, the bottom of the second wafer 34 is electrically connected to the first stage 311 of the lead frame 31 by soldering. A gate or source region at the top of the second wafer 34 is etched into the first laminate layer 37 to form vias from the surface of the second wafer 34 to the outer surface of the first laminate layer 37, while correspondingly At the foot 32, the first laminate layer also etches the vias to form vias from the surface of the leads 32 to the outer surface of the first laminate layer 37. Metal is plated in each via to form a conductive structure. On the outer surface of the first laminate layer 37, the conductive structure connected to the gate or source region of the second wafer 34 and the conductive structure of the corresponding pin of the region are plated and electrically connected to each other, thereby making the second wafer 34 The specific area is electrically connected to its corresponding pin 32.

[0070]

At the same time, the first wafer 33 is further electrically connected to the second wafer 34 by the above-mentioned conductive structure.

[0071]

Preferably, the via hole drilled by the first laminate layer 37 is tapered, and the diameter of one end of the surface of the connecting wafer or the lead is smaller than the diameter of one end of the outer surface of the first laminate.

[0072]

As shown in FIG. 13 and in conjunction with FIG. 14, the third wafer 35 is disposed on the second stage 312 of the lead frame 31, and the third wafer 35 is a MOSFET power flip chip, which is soldered and leaded. The frame 31 is electrically connected.

[0073]

A gate pin 45 is disposed at a gate of the lead frame 31 correspondingly connected to the third wafer 33, and a solder at a gate of the third wafer 33 is disposed in the gate pin 45 to ensure that the solder is not on the second stage Free scrolling on the 312 plane.

[0074]

As shown in FIGS. 13 and 14, a heat dissipation layer 131 is further disposed on the outer surface of the first laminate layer 37, and the heat dissipation layer 131 has a shape corresponding to the metal sheet 36 or the wafer for rewinding the metal sheet 36 or The heat of the wafer improves the thermal performance of the package. The heat dissipation layer 131 is a heat dissipation metal foil, the heat dissipation metal foil is made of a metal having good heat conduction characteristics, and the metal having good heat conduction characteristics may be copper or aluminum.

[0075]

Further disposed on the first laminate layer 37 is a second laminate layer 38 covering all of the conductive structures and extension portions thereof, and an outer surface of the first laminate layer 37 and the heat dissipation layer 131. on. The second laminate layer 38 has the same structural dimensions as the first laminate layer 37, and the second laminate layer 38 has a smaller thickness than the first laminate layer 37. The second laminate layer 38 is also formed of a PP layer, and the second laminate layer 38 hermetically encapsulates the outer surface of the first laminate layer 37, the conductive structure, and the heat dissipation layer 131 to complete the package structure.

[0076]

The packaging method of the second embodiment is substantially the same as the packaging method of the first embodiment, and is not described herein.

[0077]

Example 3:

[0078]

Referring to the top view (Fig. 3), the cross-sectional view in the A-A direction (Fig. 15), and the cross-sectional view in the B-B direction (Fig. 16), this embodiment 3 discloses another embodiment of an embedded package. It comprises a pre-mold leadframe (pre-mold LDF) 31, the lead frame 31 is made of copper, and the surface can be nickel-plated, silver-plated or gold-plated, and the lead frame 31 is The first stage 311 and the second stage 312 having the same thickness are disposed on the same plane. A plurality of pins 32 are surrounded around the first stage 311 and the second stage 312, and some of the pins are separated from the first stage 311 or the second stage 312 and are electrically connected. They are connected to the first stage 311 or the second stage 312, respectively. The molding material on the lead frame fills the lead frame hollow structure, so that the lead frame forms a flat surface without hollowing out.

[0079]

A first wafer 33 and a second wafer 34 are disposed on the first stage 311, and a third wafer 35 is disposed on the second stage 312. The first wafer 33 is a logic IC chip, the second wafer 34 is a MOSFET power chip, and the third wafer 35 is a MOSFET power flip chip. As shown in the figure, the first wafer 33 and the second wafer 34 are electrically connected, and the first wafer 33 and the second wafer 34 are electrically connected to respective ones of the plurality of pins 32, respectively.

[0080]

A clip 36 is disposed on the second wafer 34 and the third wafer 35, and the metal sheet 36 is in contact with and electrically connected to the top surfaces of the second wafer 34 and the third wafer 35, respectively, and the metal sheet 36 is not fully covered. The top surface of the second wafer 34 and the third wafer 35 cover only the portion of the top surface of the second wafer 34 and the third wafer 35 that needs to be connected to the lead, for example, the metal piece 36 is electrically connected to the top surface of the second wafer 34, The source of the top surface of the third wafer 35. The other end of the metal piece 36 is bonded to a pin 32' to effect electrical connection between the top surface of the second wafer 34 and the third wafer 35 and the pin 32. Preferably, the metal piece 36 is made of a copper piece, a nickel piece or other metal piece having a conductive property.

[0081]

As shown in FIG. 15 and in conjunction with FIG. 16, the first laminate 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36 and the leads 32 are coated with a first laminate layer 37. The first laminate layer 37 employs a PP layer that fills the gap between the first wafer 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36, and the leads 32, and will be first The wafer 33, the second wafer 34, the third wafer 35, the lead frame 31, the metal piece 36, and the lead 32 are hermetically sealed, and the structural dimensions of the first laminate layer 37 and the dimensions of the lead frame 31 and the leads 32 are enclosed. It is flush with the structure.

[0082]

As shown in FIG. 15 and in conjunction with FIG. 3, the first wafer 33 is bonded to the first stage 311 of the lead frame 31 by epoxy bonding. A hole is etched at a region on the top surface of the first wafer 33 corresponding to the connection pin 32 to form a via 41 from the surface of the first wafer 33 to the outer surface of the first laminate layer 37, while at the corresponding pin 32, A laminate layer also etches the vias to form vias 42 from the surface of the leads 32 to the outer surface of the first laminate layer 37. Metal is plated in the vias 41, 42, respectively, to form conductive structures 43, 44, respectively, which may be copper. On the outer surface of the first laminate layer 37, the conductive structure 43 connected to a certain area of the first wafer 33 and the conductive structure 44 of the corresponding pin 32 of the area are plated and electrically connected to each other, thereby making the first wafer 33 The specific area is electrically connected to its corresponding pin 32.

[0083]

As shown in FIG. 16 and in conjunction with FIG. 3, the bottom of the second wafer 34 is electrically connected to the first stage 311 of the lead frame 31 by soldering. A gate or source region at the top of the second wafer 34 is etched into the first laminate layer 37 to form vias from the surface of the second wafer 34 to the outer surface of the first laminate layer 37, while correspondingly At the foot 32, the first laminate layer also etches the vias to form vias from the surface of the leads 32 to the outer surface of the first laminate layer 37. Metal is plated in each via to form a conductive structure. On the outer surface of the first laminate layer 37, the conductive structure connected to the gate or source region of the second wafer 34 and the conductive structure of the corresponding pin of the region are plated and electrically connected to each other, thereby making the second wafer 34 The specific area is electrically connected to its corresponding pin 32.

[0084]

At the same time, the first wafer 33 is further electrically connected to the second wafer 34 by the above-mentioned conductive structure.

[0085]

Preferably, the via hole drilled by the first laminate layer 37 is tapered, and the diameter of one end of the surface of the connecting wafer or the lead is smaller than the diameter of one end of the outer surface of the first laminate.

[0086]

As shown in FIG. 15 and in conjunction with FIG. 16, the third wafer 35 is disposed on the second stage 312 of the lead frame 31. The third wafer 35 is a MOSFET power flip chip, and the bottom portion is provided with a regulation. The third wafer 35 is electrically connected to the lead frame 31 by the solder balls. The bottom gate and the source of the third wafer 35 are respectively provided with solder balls, and are electrically connected by solder balls. Lead frame

[0087]

A gate pin 45 (a groove shown in the figure) is disposed at a gate of the lead frame 31 correspondingly connected to the third wafer 33, and a solder ball at a gate of the third wafer 33 is disposed in the gate pin 45 to ensure The solder balls do not roll freely on the plane of the second stage 312.

[0088]

As shown in FIGS. 15 and 16, a heat dissipation layer 151 is further disposed on the outer surface of the first laminate layer 37. The heat dissipation layer 151 has a shape corresponding to the metal sheet 36 or the wafer for rewinding the metal sheet 36 or The heat of the wafer improves the thermal performance of the package. The heat dissipation layer 151 is a heat dissipation metal foil, and the heat dissipation metal foil is made of a metal having good heat conduction characteristics, and the metal having good heat conduction characteristics may be copper or aluminum.

[0089]

Further disposed on the first laminate layer 37 is a second laminate layer 38 overlying all of the conductive structures and their extensions, as well as the outer surface of the first laminate layer 37 and the heat dissipation layer 151. on. The second laminate layer 38 has the same structural dimensions as the first laminate layer 37, and the second laminate layer 38 has a smaller thickness than the first laminate layer 37. The second laminate layer 38 is also formed of a PP layer, and the second laminate layer 38 hermetically encapsulates the outer surface of the first laminate layer 37, the conductive structure, and the heat dissipation layer 151 to complete the package structure.

[0090]

The packaging method of the third embodiment is substantially the same as the packaging methods of the first and second embodiments, and is not described herein.

[0091]

Example 4:

[0092]

Referring to the top view (Fig. 17) and the A-A cross-sectional view (Fig. 18), the fourth embodiment discloses a three-dimensional stack power and logic chip (SIP). It comprises a pre-mold leadframe (pre-mold LDF) 31, the lead frame 31 is made of copper, and the surface can be nickel-plated, silver-plated or gold-plated, and the lead frame 31 is The first stage 311 and the second stage 312 having the same thickness are disposed on the same plane. A plurality of pins 32 are surrounded around the first stage 311 and the second stage 312, and some of the pins are separated from the first stage 311 or the second stage 312 and are electrically connected. They are connected to the first stage 311 or the second stage 312, respectively. The molding material on the lead frame fills the lead frame hollow structure, so that the lead frame forms a flat surface without hollowing out.

[0093]

A first power chip 171 is disposed on the first stage 311, and a second power chip 172 is disposed on the second stage 312, wherein the second power chip 172 is a flip chip. The first power die 171 and the second power die 172 may be MOSFETs.

[0094]

A chip 36 is disposed on the first power chip 171 and the second power chip 172, and the metal chip 36 is in contact with and electrically connected to the top surfaces of the first power chip 171 and the second power chip 172, respectively. 36 does not cover the top surface of the first power chip 171 and the second power chip 172, and covers only the portion of the top surface of the first power chip 171 and the second power chip 172 that needs to be connected to the lead, for example, the metal piece 36 is electrically connected first. The drain of the top surface of the power chip 171 and the source of the top surface of the second power chip 172. The other end of the metal piece 36 is bonded to a pin 32' to electrically connect the top surface of the first power chip 171 and the second power chip 172 to the pin 32. Preferably, the metal piece 36 is made of a copper piece, a nickel piece or other metal piece having a conductive property.

[0095]

As shown in FIG. 18, the first power layer 171, the second power wafer 172, the lead frame 31, the metal piece 36, and the leads 32 are coated with a first laminate layer 37, the first laminate layer 37. A PP layer is used, which fills the gap between the first power chip 171, the second power chip 172, the lead frame 31, the metal piece 36 and the lead 32, and the first power chip 171, the second power chip 172, and the lead The frame 31, the metal piece 36 and the lead 32 are hermetically sealed, and the first laminate layer 37 has a structural size that is flush with the size and structure of the lead frame 31 and the lead 32.

[0096]

As shown in FIGS. 17 and 18, a passive device 174 and a logic chip 173 are disposed on the first laminate layer 37, and are laid on the passive device 174, the first laminate layer 37, and the logic wafer 173. An intermediate laminate layer 175 encasing the passive device 174 and the logic wafer 173 and having the same structural dimensions as the first laminate layer 37, the thickness being slightly smaller than the first laminate layer 37 . The intermediate laminate layer 175 is a PP layer. Wherein the first laminate layer 37 is provided with a copper foil island 176 at a position corresponding to the passive device 174 and the logic wafer 173, and the logic chip 173 and the passive device 174 are soldered on the copper foil island by soldering Copper foil traces are interconnected with the remaining functional devices.

[0097]

Located at the logic wafer 173, the intermediate laminate layer 175 etches the vias to form vias from the surface of the logic wafer 173 to the outer surface of the intermediate laminate layer 175, while at the corresponding pins 32, the first laminate layer and The logic die 173 also etches the vias to form vias from the surface of the leads 32 to the outer surface of the logic die 173. Metal is plated in each of the via holes to form a conductive structure, and the metal may be copper. On the outer surface of the first laminate layer 37, the conductive structure connected to the logic chip 173 and the conductive structures of the respective pins corresponding to the logic chip 173 are plated and electrically connected to each other, thereby realizing the logic chip 173 and its corresponding pin 32. Electrical connection.

[0098]

At the same time, the logic chip 173 is further electrically connected to the metal piece 36 by the above-mentioned conductive structure.

[0099]

Preferably, the via holes drilled by the first laminate layer 37 and the intermediate laminate layer 175 are tapered, and the diameter of one end of the connecting wafer or the lead surface is smaller than the outer surface of the first laminate layer 37 or the intermediate laminate layer 175. The caliber of one end.

【0100】

As shown in FIG. 18, the second power chip 172 is placed on the second stage 312 of the lead frame 31, and the second power chip 172 is a MOSFET power flip chip having a prescribed density of solder at the bottom. The second power chip 172 is electrically connected to the lead frame 31 by using the solder balls. The bottom gate and the source of the second power chip 172 are respectively provided with solder balls, and the solder balls are electrically connected to the leads. frame.

【0101】

Preferably, a heat dissipation layer 181 is further disposed on the outer surface of the intermediate layer 175, and the heat dissipation layer 181 has a shape structure corresponding to the metal piece 36, the logic chip 173 and the passive device 174 for heat dissipation and improvement of the package. Thermal performance. The heat dissipation layer 181 is a heat dissipation metal foil, and the heat dissipation metal foil is made of a metal having good heat conduction characteristics, and the metal having good heat conduction characteristics may be copper or aluminum.

【0102】

Further disposed on the intermediate laminate layer 175 is a second laminate layer 38 overlying all of the conductive structures and their extensions, as well as the outer surface of the intermediate laminate layer 175 and the heat dissipation layer 181. The second laminate layer 38 has the same structural dimensions as the first laminate layer 37 and the intermediate laminate layer 175, and the second laminate layer 38 has a smaller thickness than the first laminate layer 37. The second laminate layer 38 is also formed of a PP layer. After the second laminate layer 38 is hermetically sealed to the outer surface of the intermediate laminate layer 175, the conductive structure and the heat dissipation layer 151, the complete package structure is completed.

【0103】

The packaging process of the fourth embodiment is as follows:

[0104]

First, the lead frame 31 is prefabricated, and the lead frame 31 includes a first stage 311 and a second stage 312 which are disposed apart from each other, and pins are disposed around the first stage 311 and the second stage 312. 32, a part of the pin 32 is electrically connected to the first stage 311 or the second stage 312, and is partially separated from the first stage 311 or the second stage 312. The lead frame 31 is pre-filled with a molding material, and the molding material on the lead frame fills the hollow structure of the lead frame 31 so that the lead frame 31 forms a flat surface without voiding.

【0105】

The bottom of the first power chip 171 is electrically connected to the first stage 311 of the lead frame 31 by soldering; the second power chip 172 is soldered to the second stage of the lead frame 31 by a solder ball dot of the bottom surface thereof. On the platform 312.

【0106】

A metal piece 36 is disposed on the first power chip 171 and the second power chip 172. The metal piece 36 is electrically connected to the drain of the first power chip 171 and the source of the second power chip 172, respectively. Bonded to the corresponding pin 32'. The first power chip 171 is electrically connected to the second power chip 172, and the first power chip 171 and the second power chip 172 are electrically connected to the pin 32'.

【0107】

A first laminate layer 37 is laid over the disposed first power wafer 171, the second power wafer 172, the lead frame 31, and the leads 32. The first laminate layer 37 hermetically encapsulates the first power wafer 171, the second power wafer 172, and the leads 32, and the length and width of the first laminate layer 37 are the same as the length and width of the lead frame 31, and The upper surface of the lead frame 31 is completely covered. The first laminate layer 37 is a PP layer.

【0108】

After the first laminate layer 37 is completed, a conductive layer is electroplated on the first laminate layer 37.

【0109】

Alternatively, the first laminate layer 37 is a PP plate of a predetermined copper foil, wherein the copper foil serves as the above-mentioned conductive layer.

[0110]

Corresponding to the area of the first power chip 171, the second power chip 172 to which the pins are to be connected, and the corresponding pins 32, the first laminate layer 37 is drilled through the holes.

[0111]

Electroplating the metal in each of the vias forms a conductive structure that extends from the wafer or pin surface to the surface of the first laminate layer 37. Preferably, the plating metal used to form the electrically conductive structure is copper.

[0112]

After the conductive structure is formed in the via hole, the conductive layer or the copper foil is etched to form an electrical connection line 111 between the first power chip 171, the second power chip 172, and the conductive structure of the corresponding lead 32, and copper. Foil based island 176. The conductive structure on the area of each of the wafers to which the pins are to be connected is electrically connected to the conductive structures on the corresponding pins of the respective areas. At the same time, a copper foil island 176 is provided for setting the passive device 174.

[0113]

Logic wafer 173 and passive device 174 are soldered on copper foil island 176 by soldering.

【0114】

After the electrical connection between the conductive structures is completed, an intermediate laminate layer 175 is coated on the first laminate layer 37, the intermediate laminate layer 175 covering the conductive structure and its electrical connection lines, and the logic wafer 173 and passive components 174. Meanwhile, the intermediate laminate layer 175 has the same structural size as the first laminate layer 37, and the intermediate laminate layer 175 has a smaller thickness than the first laminate layer 37. The intermediate laminate layer 175 is also a PP layer of a predetermined copper foil.

[0115]

Corresponding logic chip 173, passive device 174, first power chip 171, and second power chip 172 are connected to pins or interconnected regions and respective corresponding pins 32, and the intermediate laminate layer 175 is drilled through the holes, respectively.

[0116]

After the conductive structure is formed in the via, the conductive layer or copper foil is etched on the intermediate laminate layer 175 to form a conductive structure between the first power die 171, the second power die 172, and its corresponding pin 32. Electrical connection line 111. The conductive structure on the area of each of the wafers to which the pins are to be connected is electrically connected to the conductive structures on the corresponding pins of the respective areas.

【0117】

After the electrical connection between the various devices on the intermediate laminate layer 175 is completed, a second laminate layer 38 is deposited over the intermediate laminate layer 175 to encapsulate the conductive structures and their electrical connections.

【0118】

After the second laminate layer 38 is laid, the complete packaging process is completed.

【0119】

It can be seen from the flow chart and the package structure of the embodiment that the package can add or reduce the corresponding laminate according to specific needs, and the three-dimensional (3D) stack lamination technology of the package can be realized by lamination, when the size allows In the following, how many package layers are needed, the corresponding laminate layer can be disposed to implement packaging for devices distributed in different layers, and at the same time, by the feature of the present invention, the characteristics of the conductive structure can be realized without affecting the structure setting. Devices in different layers are electrically connected to achieve system-level packaging.

[0120]

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

Domestic registration information [please note according to the registration authority, date, number order]
No foreign deposit information [please note according to the country, organization, date, number order]
no

no

311‧‧‧First stage

312‧‧‧Second stage

32‧‧‧ pin

33‧‧‧First chip

35‧‧‧ Third chip

37‧‧‧First laminate

38‧‧‧Second laminate

41, 42‧‧‧ Via

43,44‧‧‧Electrical structure

45‧‧‧gate pin

Claims (24)

[Item 1] An embedded package that includes:
a lead frame of pre-filled sealing material, and a plurality of wafers disposed thereon;
a plurality of pins arranged around the lead frame;
a molding material on the lead frame fills the lead frame hollow structure, so that the lead frame forms a plane without hollowing out;
a metal sheet disposed on a portion of the plurality of wafers, the wafers being electrically connected by the metal sheet, the metal sheet being electrically connected to the lead at one end;
a first laminate layer overlying the wafer, the lead frame, the metal sheet, and the pin;
Corresponding to the pin and the area of each of the wafers for connecting the pins, the first laminate layer is provided with a via from the surface of the wafer or the lead to the outer surface of the first laminate;
Each of the via holes is plated with a metal to form a conductive structure;
The conductive structure on the area of the chip to be connected to the pin is electrically connected to the conductive structure on the pin corresponding to the respective regions; or the electrical conductivity of the corresponding conductive structure between the wafer and the other of the wafers connection. [Item 2] The embedded package of claim 1, wherein the plurality of wafers comprise a first wafer, a second wafer, and a third wafer. [Item 3] The embedded package of claim 2, wherein the first wafer is a logic wafer. [Item 4] The embedded package of claim 3, wherein the first wafer is bonded to the lead frame by epoxy, and the top is respectively connected to the corresponding pin by a plurality of conductive structures. [Item 5] The embedded package of claim 2, wherein the second wafer is a MOSFET power chip. [Item 6] The embedded package of claim 5, wherein the bottom of the second wafer is electrically connected to the lead frame, and the top gate and the top source are respectively connected to the corresponding pins by conductive structures. [Item 7] The embedded package of claim 2, wherein the third wafer is a MOSFET power flip chip. [Item 8] The embedded package of claim 7, wherein the bottom gate and the source of the third wafer are respectively provided with solder balls, and the lead frame is electrically connected by solder balls. [Item 9] The embedded package of claim 8, wherein the lead frame is connected to the third wafer gate and is provided with a gate pin, and the solder ball at the third wafer gate is connected to the gate. On the feet. [Item 10] The embedded package according to any one of claims 2 to 9, wherein the lead frame comprises a first stage and a second stage which are separately disposed, the first wafer and the second The wafer is disposed on the first stage; the third wafer is disposed on the second stage. [Item 11] The embedded package of any one of claims 2 to 9, wherein the metal piece is disposed on a drain of the second wafer and a source of the third wafer, and the drain of the second wafer And a source of the third wafer is electrically connected by the metal piece. [Item 12] The embedded package of claim 11, wherein the metal piece is a copper piece or a nickel piece. [Item 13] The embedded package of claim 1, wherein the first laminate layer is a PP layer. [Item 14] The embedded package of claim 1 or claim 13 wherein the first laminate layer further comprises a second laminate layer overlying the conductive structure and its extension. [Item 15] The embedded package of claim 14, wherein the second laminate layer is a PP layer. [Item 16] The embedded package of claim 1, wherein the via is tapered, and the diameter of one end of the surface of the wafer or the surface of the lead is smaller than the diameter of one end of the outer surface of the first laminate. [Item 17] The embedded package of claim 1, wherein the surface of the first laminate layer is further provided with a heat dissipating metal foil disposed at a position corresponding to the metal sheet or the wafer. [Item 18] The embedded package of claim 15, wherein a plurality of intermediate laminate layers are further stacked between the first laminate layer and the second laminate layer. [Item 19] The embedded package of claim 18, wherein the intermediate laminate layer is provided with an electronic device. [Item 20] An encapsulation method for an embedded package, the method comprising the following steps:
The wafer patch is disposed on the lead frame of the pre-filled sealing material, and the first laminate layer is laid on the disposed wafer, the lead frame and the lead;
Corresponding to the area where the chip needs to be connected to the pin and the corresponding pin, the first laminate layer is drilled through the hole, and a conductive structure is formed in each via hole, and the conductive structure extends from the surface of the wafer or the lead to the first layer. a surface of the laminate; and a conductive structure on a region of each of the wafers to which the leads are to be connected is electrically connected to a conductive structure on a corresponding pin of each of the regions; or a conductive structure between the respective wafers and other wafers Connected lines. [Item 21] The encapsulation method according to claim 20, wherein before the first laminate layer is drilled through the hole, a conductive layer is pre-laminated in the first laminate layer, and after the conductive structure is formed in the via hole, the conductive layer is performed. Etching to form electrical connections between the wafer and its corresponding pins or conductive structures of other wafers. [Item 22] The encapsulation method according to claim 20, wherein when the first laminate layer is laid, the first laminate layer has a metal foil on one side, and after the conductive structure is formed in the via hole, the metal foil is etched to Forming electrical connections between the wafer and its corresponding pins or conductive structures of other wafers. [Item 23] The encapsulation method according to any one of claims 20 to 22, wherein after the electrical connection between the electrically conductive structures is completed, a second laminate layer is laid on the first laminate layer, the second laminate layer The conductive structure is covered and its electrical connection. [Item 24] The encapsulation method of claim 20, wherein a metal piece is disposed on the plurality of power chips before the first laminate layer is laid to realize electrical connection between the power chips, and the metal piece is electrically connected. To the corresponding pin.