WO2020125073A1 - Fan-out packaging structure for stacking flash chips and manufacturing method thereof - Google Patents

Fan-out packaging structure for stacking flash chips and manufacturing method thereof Download PDF

Info

Publication number
WO2020125073A1
WO2020125073A1 PCT/CN2019/104927 CN2019104927W WO2020125073A1 WO 2020125073 A1 WO2020125073 A1 WO 2020125073A1 CN 2019104927 W CN2019104927 W CN 2019104927W WO 2020125073 A1 WO2020125073 A1 WO 2020125073A1
Authority
WO
WIPO (PCT)
Prior art keywords
flash chip
flash
layer
chip
chips
Prior art date
Application number
PCT/CN2019/104927
Other languages
French (fr)
Chinese (zh)
Inventor
倪寿杰
孙鹏
曹立强
Original Assignee
华进半导体封装先导技术研发中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华进半导体封装先导技术研发中心有限公司 filed Critical 华进半导体封装先导技术研发中心有限公司
Publication of WO2020125073A1 publication Critical patent/WO2020125073A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73227—Wire and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
    • H01L2224/92164—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Definitions

  • a second Flash chip, the second Flash chip is disposed on the uppermost first Flash chip through a misaligned formal mounting, wherein the pads of each first Flash chip and the second Flash chip are not covered by adjacent chips;
  • a first chip 310 and a second chip 320 are provided.
  • the first chip is a conventional Flash chip, which is composed of a chip body 311 and a lead pad 312, wherein the lead pad is used to form an electrical interconnection with other chips and/or external circuits; the second chip 320 passes on the surface of the conventional Flash chip
  • the rearrangement wiring layer 321 is formed to form external conductive copper pillars 323 and interconnection pads 322.
  • multiple sets of first chips 310 and a set of second chips 320 need to be provided, and the interconnection pads 322 of the second chips 320 are nickel-palladium gold pads.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A fan-out packaging structure (200) for stacking flash chips comprises: multiple first flash chips (210) attached face-up to the bottom of the packaging structure (200) in a staggered manner; a second flash chip (220) attached face-up to the uppermost first flash chip (210) in a staggered manner; electrically-conductive wires (240) electrically interconnecting the multiple first flash chips (210) and the second flash chip (220); a plastic encapsulation layer (250) enclosing the first flash chips (210) and the second flash chip (220); and a redistribution layer (260) electrically connected to the the second flash chip (220) and realizing a fan-out function of the packaging structure (200).

Description

一种Flash芯片堆叠的扇出封装结构及其制造方法Fan-out packaging structure of Flash chip stacking and manufacturing method thereof 技术领域Technical field
本发明涉及半导体封装技术领域，尤其涉及一种Flash芯片堆叠的扇出封装结构及其制造方法。The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging structure for a stack of Flash chips and a manufacturing method thereof.
背景技术Background technique
随着电子产品轻、小型化的要求，IC芯片封装趋于薄型、小型化。芯片封装的小型化、薄型化就显得尤其重要。在目前电子产品中，存储芯片占据非常重要的地位，而Flash(闪存)芯片又是其中一类核心产品。With the demand for light and miniaturized electronic products, IC chip packaging tends to be thin and miniaturized. The miniaturization and thinning of chip packages are particularly important. In current electronic products, memory chips occupy a very important position, and Flash (flash memory) chips are one of the core products.
传统的Flash存储芯片的封装结构通过堆叠封装实现器件密度的进一步提升。图1示出现有的Flash存储芯片的堆叠封装结构100。现有的封装结构通过再封装衬底/基板101上采用DAF(Die Attach Film，芯片粘接膜)错位层贴多个Flash存储芯片102，然后采用引线键合实现芯片间的互连最后进行整体塑封保护。这种Flash存储芯片的封装结构由于采用了封装基板工艺，极大的增加了堆叠封装结构的厚度。The packaging structure of the traditional Flash memory chip achieves a further increase in device density through stacked packaging. FIG. 1 shows a conventional stacked packaging structure 100 of Flash memory chips. The existing packaging structure uses a DAF (Die Attach Film, chip adhesive film) dislocation layer on the re-encapsulation substrate/substrate 101 to stick multiple flash memory chips 102, and then uses wire bonding to realize the interconnection between the chips and finally the whole Plastic protection. The packaging structure of this Flash memory chip greatly increases the thickness of the stacked packaging structure due to the packaging substrate technology.
针对现有Flash存储芯片的堆叠封装结构需要采用封装基板，存在的封装结构厚度较大等问题，本发明提出了一种新型的Flash芯片堆叠的Fan-Out(扇出)封装结构及其制造方法，省略了封装基板，实现了更小尺寸和更低厚度的堆叠封装结构。In view of the problem that the existing flash memory chip stack packaging structure needs to use a packaging substrate, the existing packaging structure has a large thickness, and the like, the present invention proposes a new type of Flash chip stacked Fan-Out (fan-out) packaging structure and manufacturing method thereof , The package substrate is omitted, and a smaller size and lower thickness stacked package structure is realized.
发明内容Summary of the invention
针对现有Flash存储芯片的堆叠封装结构需要采用封装基板，存在的封装结构厚度较大等问题，根据本发明的一个方面，提供一种Flash芯片堆叠的Fan-Out封装结构，包括：In view of the problem that the existing flash memory chip stack packaging structure needs to use a packaging substrate, and the existing packaging structure has a large thickness, etc., according to one aspect of the present invention, a Flash chip stacked Fan-Out packaging structure is provided, including:
多个第一Flash芯片，所述多个第一Flash芯片通过错位正装层贴设置在封装结构的底部；A plurality of first Flash chips, the plurality of first Flash chips are arranged on the bottom of the packaging structure through a misaligned formal mounting layer sticker;
第二Flash芯片，所述第二Flash芯片通过错位正装层贴设置在最上层第 一Flash芯片之上，其中每个第一Flash芯片和第二Flash芯片的焊盘不会被相邻芯片覆盖；A second Flash chip, the second Flash chip is disposed on the uppermost first Flash chip through a misaligned formal mounting, wherein the pads of each first Flash chip and the second Flash chip are not covered by adjacent chips;
导电引线，所述导电引线电互连所述多个第一Flash芯片和第二Flash芯片；Conductive leads that electrically interconnect the plurality of first Flash chips and second Flash chips;
塑封层，所述塑封层包覆所述多个第一Flash芯片和第二Flash芯片；A plastic encapsulation layer, the plastic encapsulation layer covering the plurality of first Flash chips and second Flash chips;
重新布局布线层，所述重新布局布线层与所述第二Flash芯片电连接，并实现对封装结构的扇出功能。Re-laying the wiring layer, the re-laying wiring layer is electrically connected to the second Flash chip, and realizes a fan-out function to the packaging structure.
在本发明的一个实施例中，Flash芯片堆叠的Fan-Out封装结构还包括设置在所述多个第一Flash芯片和所述第二Flash芯片的相邻两者之间的DAF薄膜，所述DAF薄膜用于实现所述错位正装层贴。In an embodiment of the present invention, the Fan-Out package structure of the stacked Flash chips further includes a DAF film disposed between adjacent ones of the plurality of first Flash chips and the second Flash chips, the The DAF film is used to realize the misplaced formal dressing.
在本发明的一个实施例中，所述第二Flash芯片还包括：In an embodiment of the present invention, the second Flash chip further includes:
RDL层，所述RDL层设置在所述第二Flash芯片表面，且与所述第二Flash芯片的IO互连；An RDL layer, the RDL layer is provided on the surface of the second Flash chip and is interconnected with the IO of the second Flash chip;
互连焊盘，所述互连焊盘电连接至所述RDL层，用于实现所述第二Flash芯片和所述第一Flash芯片的互连；以及An interconnection pad, the interconnection pad is electrically connected to the RDL layer, for interconnecting the second Flash chip and the first Flash chip; and
导电铜柱。Conductive copper pillars.
在本发明的一个实施例中，所述互连焊盘为镍钯金焊盘。In one embodiment of the present invention, the interconnection pad is a nickel-palladium gold pad.
在本发明的一个实施例中，所述重新布局布线层通过所述导电铜柱、所述RDL层实现和所述第二Flash芯片电连接。In an embodiment of the present invention, the redistribution wiring layer is electrically connected to the second Flash chip through the conductive copper pillar and the RDL layer.
在本发明的一个实施例中，所述塑封层漏出最下层第一Flash芯片的背面。In an embodiment of the present invention, the plastic encapsulation layer leaks out of the back surface of the lowermost first Flash chip.
在本发明的一个实施例中，所述重新布局布线层具有N层重布线金属层，其中N≥2。In one embodiment of the present invention, the redistribution wiring layer has N rewiring metal layers, where N≧2.
根据本发明的另一个实施例中，提供一种Flash芯片堆叠的Fan-Out封装结构的制造方法，包括：According to another embodiment of the present invention, a method for manufacturing a stacked Flash chip Fan-Out package structure is provided, including:
提供第一Flash芯片和第二Flash芯片，其中第二Flash芯片具有RDL层、引线焊盘和导电铜柱；Provide a first Flash chip and a second Flash chip, where the second Flash chip has an RDL layer, a lead pad and a conductive copper pillar;
采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上，并漏出各芯片的引线焊盘；Use the DAF process to attach and bond multiple first Flash chips and one second Flash chip dislocation layer to the carrier board, and leak the lead pads of each chip;
通过引线键合工艺电连接已完成错位层贴的第一Flash芯片和第二Flash 芯片；Electrically connecting the first Flash chip and the second Flash chip that have completed the dislocation layer bonding through a wire bonding process;
对完成引线键合的第一Flash芯片和第二Flash芯片进行整体塑封；Integrally mold the first Flash chip and the second Flash chip that have completed wire bonding;
减薄塑封层并去除载板；Thin the plastic seal layer and remove the carrier board;
在裸露出第二Flash芯片的导电铜柱的塑封层上面形成重新布局布线层。A redistribution wiring layer is formed on the plastic encapsulation layer that exposes the conductive copper pillar of the second Flash chip.
在本发明的另一个实施例中，所述采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上进一步包括：In another embodiment of the present invention, the use of the DAF process to paste and bond a plurality of first Flash chips and a second Flash chip to the carrier board and further comprising:
将一个第一Flash芯片通过键合材料键合到载板上，形成最下层第一Flash芯片；Bond a first Flash chip to the carrier board with a bonding material to form the lowermost first Flash chip;
利用DAF薄膜将多个第一Flash芯片依次错位层贴至最下层第一Flash芯片上；以及Using a DAF film to sequentially paste a plurality of first Flash chips to the lowermost first Flash chip; and
将一个第二Flash芯片错位层贴至最上层第一Flash芯片上。A second flash chip dislocation layer is attached to the uppermost first flash chip.
在本发明的另一个实施例中，所述载板为透光材料；所述键合材料为激光可拆键合材料。In another embodiment of the present invention, the carrier board is a light-transmitting material; the bonding material is a laser detachable bonding material.
本发明提供一种Flash芯片堆叠的Fan-Out封装结构及其制造方法，基于扇出结构设计的封装，封装体中各层芯片通过引线键合互连，顶层芯片预设有重新布局布线层(RDL，Re-Distribution Layer)建立互连的镍钯金焊盘和导电铜柱，镍钯金焊盘与相邻层芯片通过引线键合互连，导电铜柱通过塑封减薄露头，然后再采用RDL和Bumping工艺互连实现最终堆叠封装结构。基于本发明的该种Flash芯片堆叠的Fan-Out封装结构具有相比现有flash产品更低的厚度，从而满足更多便携式、微型电子设备的要求。The present invention provides a Fan-Out package structure for flash chip stacking and a manufacturing method thereof. The package is designed based on a fan-out structure. Each layer of chips in the package body is interconnected by wire bonding. The top chip is preset with a re-layout wiring layer ( RDL, Re-Distribution (Layer) establishes interconnected nickel-palladium gold pads and conductive copper pillars. The nickel-palladium gold pads and the adjacent layer chips are interconnected by wire bonding. The conductive copper pillars are thinned by plastic encapsulation and then used. RDL and Bumping process interconnection to achieve the final stacked package structure. The Fan-Out package structure based on the flash chip stack of the present invention has a lower thickness than existing flash products, thereby meeting the requirements of more portable and miniature electronic devices.
附图说明BRIEF DESCRIPTION
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。In order to further clarify the above and other advantages and features of the embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the drawings. It can be understood that these drawings depict only typical embodiments of the present invention and therefore will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar symbols.
图1示出现有技术的Flash存储芯片的堆叠封装结构100的剖面示意图。FIG. 1 shows a schematic cross-sectional view of a stack package structure 100 of a prior art Flash memory chip.
图2示出根据本发明的一个实施例形成的一种Flash芯片堆叠的Fan-Out封装结构200的剖面示意图。FIG. 2 shows a schematic cross-sectional view of a stacked Fan-Out package structure 200 of Flash chips formed according to an embodiment of the present invention.
图3A至图3H示出根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的过程剖面示意图。3A to 3H show schematic cross-sectional views of a process of forming the Fan-Out package structure 200 of the Flash chip stack according to an embodiment of the present invention.
图4示出的是根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的流程图400。FIG. 4 shows a flowchart 400 of forming the Fan-Out package structure 200 of the Flash chip stack according to an embodiment of the present invention.
具体实施方式detailed description
在以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免使本发明的各实施例的诸方面晦涩。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明可在没有特定细节的情况下实施。此外，应理解附图中示出的各实施例是说明性表示且不一定按比例绘制。In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that embodiments may be implemented without one or more specific details or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations have not been shown or described in detail so as not to obscure aspects of the embodiments of the present invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a comprehensive understanding of embodiments of the invention. However, the present invention can be implemented without specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。In this specification, reference to "one embodiment" or "this embodiment" means that a particular feature, structure, or characteristic described in connection with this embodiment is included in at least one embodiment of the present invention. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily all refer to the same embodiment.
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the process Adjustment to adjust the sequence of steps.
本发明提供一种Flash芯片堆叠的Fan-Out封装结构及其制造方法，基于扇出结构设计的封装，封装体中各层芯片通过引线键合互连，顶层芯片预设有重新布局布线层(RDL，Re-Distribution Layer)建立互连的镍钯金焊盘和导电铜柱，镍钯金焊盘与相邻层芯片通过引线键合互连，导电铜柱通过塑封减薄露头，然后再采用RDL和Bumping工艺互连实现最终堆叠封装结构。基于本发明的该种Flash芯片堆叠的Fan-Out封装结构具有相比现有flash产品更低的厚度，从而满足更多便携式、微型电子设备的要求。The present invention provides a Fan-Out package structure for Flash chip stacking and a manufacturing method thereof. The package is based on a fan-out structure design. The chips in the package body are interconnected by wire bonding. The top chip is preset with a redistribution wiring layer ( RDL, Re-Distribution Layer) to establish interconnected nickel-palladium gold pads and conductive copper pillars. The nickel-palladium gold pads and the adjacent layer chips are interconnected by wire bonding. The conductive copper pillars are thinned by plastic encapsulation and then used. RDL and Bumping process interconnection to achieve the final stacked package structure. The Fan-Out package structure based on the flash chip stack of the present invention has a lower thickness than existing flash products, thereby meeting the requirements of more portable and miniature electronic devices.
下面结合图2来详细介绍根据本发明的一个实施例的一种Flash芯片堆叠的Fan-Out封装结构。图2示出根据本发明的一个实施例形成的一种Flash芯片堆叠的Fan-Out封装结构200的剖面示意图。如图2所示，该Flash芯片 堆叠的Fan-Out封装结构200进一步包括第一Flash芯片210、第二Flash芯片220、芯片粘接膜230、导电引线240、塑封层250、重新布局布线层260以及外接焊球270。The following describes a Fan-Out package structure of a stacked Flash chip according to an embodiment of the present invention in conjunction with FIG. 2. FIG. 2 shows a schematic cross-sectional view of a stacked Fan-Out package structure 200 of Flash chips formed according to an embodiment of the present invention. As shown in FIG. 2, the stacked Fan-Out package structure 200 of Flash chips further includes a first Flash chip 210, a second Flash chip 220, a chip adhesive film 230, a conductive lead 240, a plastic encapsulation layer 250, and a rearrangement wiring layer 260 As well as external solder balls 270.
第一Flash芯片210设置在封装结构的上部，为常规Flash芯片，由芯片主体和引线焊盘构成，其中引线焊盘用于和其他芯片和/或外部电路形成电互连。在本发明的一个实施例中，第一Flash芯片210包括3个相同或类似结构的类似芯片构成，从上到下依次为210-1、210-2、210-3，对应的具有3组引线焊盘211-1、211-2、211-3。The first Flash chip 210 is arranged at the upper part of the package structure and is a conventional Flash chip, which is composed of a chip body and a lead pad, where the lead pad is used to form an electrical interconnection with other chips and/or external circuits. In an embodiment of the present invention, the first Flash chip 210 includes three similar chips of the same or similar structure, from top to bottom are 210-1, 210-2, 210-3, corresponding to three sets of leads Pads 211-1, 211-2, 211-3.
第二Flash芯片220通过在常规Flash芯片的表面通过重新布局布线层221形成外接导电铜柱223和互连焊盘222形成，设置在第一Flash芯片210的下面。在本发明的一个实施例中，互连焊盘为镍钯金焊盘。The second Flash chip 220 is formed by forming external conductive copper pillars 223 and interconnection pads 222 on the surface of the conventional Flash chip by rearranging the wiring layer 221, and is disposed under the first Flash chip 210. In one embodiment of the invention, the interconnect pad is a nickel-palladium gold pad.
芯片粘接膜230用于芯片堆叠时的贴片，通过标准的DAF工艺将多个第一Flash芯片210和一个第二Flash芯片220错位正贴，其中第二Flash芯片220位于最下层。如图所示，每个Flash芯片的焊盘区域不会被相邻层叠的Flash芯片覆盖。The chip adhesive film 230 is used for the patch when the chips are stacked, and the first flash chips 210 and one second flash chip 220 are staggered and pasted by a standard DAF process, wherein the second flash chip 220 is located at the bottom layer. As shown in the figure, the pad area of each Flash chip will not be covered by adjacent stacked Flash chips.
导电引线240互连相邻的第一Flash芯片210和/或第二Flash芯片220。导电引线240通过引线键合工艺形成，可以为金线、铜线或者其他金属线或合金线。The conductive lead 240 interconnects the adjacent first Flash chip 210 and/or the second Flash chip 220. The conductive lead 240 is formed by a wire bonding process, and may be a gold wire, a copper wire, or other metal wires or alloy wires.
塑封层250包覆第一Flash芯片210、第二Flash芯片220以及导电引线240，起到绝缘保护和结构支撑作用。在本发明的一个实施例中，最外侧的第一Flash芯片210的背面从塑封层250中裸露出来，以获得良好的散热效果。The plastic encapsulation layer 250 covers the first Flash chip 210, the second Flash chip 220 and the conductive lead 240 to play an insulation protection and structural support role. In one embodiment of the present invention, the back side of the outermost first Flash chip 210 is exposed from the plastic encapsulation layer 250 to obtain a good heat dissipation effect.
重新布局布线层260设置在与第二Flash芯片220的导电铜柱223电互连，并实现对堆叠Flash芯片引脚的扇出功能。在本发明的一个实施例中，重新布局布线层260可以包括一层或多层重新布线层构成。The re-layout wiring layer 260 is disposed to be electrically interconnected with the conductive copper pillar 223 of the second Flash chip 220, and realizes the fan-out function for the pins of the stacked Flash chip. In one embodiment of the present invention, the redistribution wiring layer 260 may include one or more redistribution layers.
外接焊球270设置在重新布局布线层260的外接焊盘上，实现与外部电路的电和/或信号互连。The external solder balls 270 are disposed on the external pads of the redistribution wiring layer 260 to realize electrical and/or signal interconnection with external circuits.
下面结合图3A至图3H以及图4来详细描述形成该种芯片Flash芯片堆叠的Fan-Out封装结构200的过程。图3A至图3H示出根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的过程剖面示意图；图 4示出的是根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的流程图400。The process of forming the Fan-Out package structure 200 of this kind of chip Flash chip stack will be described in detail below with reference to FIGS. 3A to 3H and FIG. 4. 3A to 3H show a schematic cross-sectional view of the process of forming the Fan-Out package structure 200 of the Flash chip stack according to an embodiment of the invention; FIG. 4 shows the formation of the Flash chip according to an embodiment of the invention Flow chart 400 of the stacked Fan-Out package structure 200.
首先，在步骤410，如图3A、图3B所示，提供第一芯片310和第二芯片320。其中第一芯片为常规Flash芯片，由芯片主体311和引线焊盘312构成，其中引线焊盘用于和其他芯片和/或外部电路形成电互连；第二芯片320在常规Flash芯片的表面通过重新布局布线层321形成外接导电铜柱323和互连焊盘322形成。在本发明的一个实施例中，需要提供多组第一芯片310和一组第二芯片320，第二芯片320的互连焊盘322为镍钯金焊盘。First, in step 410, as shown in FIGS. 3A and 3B, a first chip 310 and a second chip 320 are provided. The first chip is a conventional Flash chip, which is composed of a chip body 311 and a lead pad 312, wherein the lead pad is used to form an electrical interconnection with other chips and/or external circuits; the second chip 320 passes on the surface of the conventional Flash chip The rearrangement wiring layer 321 is formed to form external conductive copper pillars 323 and interconnection pads 322. In one embodiment of the present invention, multiple sets of first chips 310 and a set of second chips 320 need to be provided, and the interconnection pads 322 of the second chips 320 are nickel-palladium gold pads.
接下来，在步骤420，如图3C所示，采用DAF工艺将多个第一芯片310及一个第二芯片320错位层贴并键合到载板340上，错位层贴漏出各芯片的引线焊盘。在本发明的一个实施中，第一步将一个第一芯片310-1通过键合材料330键合到载板340上，第二步采用DAF薄膜350将多个第一芯片310-2、310-3及一个第二芯片320错位层贴至第一芯片310-1上。在本发明的又一实施例中，键合材料330为激光可拆键合材料，载板340为透光材料，以获得更安全、经济和高效的工艺效果。Next, in step 420, as shown in FIG. 3C, a plurality of first chips 310 and one second chip 320 are bonded and bonded to the carrier board 340 using a DAF process. plate. In one implementation of the present invention, in the first step, a first chip 310-1 is bonded to the carrier board 340 through a bonding material 330, and in the second step, the DAF film 350 is used to bond the plurality of first chips 310-2, 310. -3 and a dislocation layer of the second chip 320 are attached to the first chip 310-1. In yet another embodiment of the present invention, the bonding material 330 is a laser detachable bonding material, and the carrier plate 340 is a light-transmitting material to obtain a safer, economical, and efficient process effect.
然后，在步骤430，如图3D所示，通过导电引线360引线键合电连接已完成错位层贴的第一芯片310和第二芯片320。导电引线360可以为金线、铜线或其他金属线以及合金线。Then, in step 430, as shown in FIG. 3D, the first chip 310 and the second chip 320 that have completed the dislocation layer bonding are electrically connected by wire bonding through conductive wires 360. The conductive lead 360 may be a gold wire, a copper wire or other metal wire, and an alloy wire.
接下来，在步骤440，如图3E所示，对完成引线键合的第一芯片310和第二芯片320进行整体塑封，塑封后的塑封层370完全包覆第一芯片310和第二芯片320。Next, in step 440, as shown in FIG. 3E, the first chip 310 and the second chip 320 that have completed the wire bonding are integrally encapsulated, and the plastic encapsulation layer 370 after the encapsulation completely covers the first chip 310 and the second chip 320 .
然后，在步骤450，如图3F所示，减薄塑封层370，并去除载板340。其中减薄塑封层370可通过研磨、抛光等工艺实现，逐渐减薄塑封层370，直到漏出第二芯片320的导电铜柱323，在导电铜柱323上方形成晶圆重构面。其中，去除载板340工艺可通过加热、光照等方式完成，具体去除方式需要依据键合材料330的特性进行。Then, in step 450, as shown in FIG. 3F, the plastic encapsulation layer 370 is thinned, and the carrier board 340 is removed. The thinning of the plastic encapsulation layer 370 can be achieved through grinding, polishing and other processes. The plastic encapsulation layer 370 is gradually thinned until the conductive copper pillar 323 of the second chip 320 leaks, and a wafer reconstruction surface is formed above the conductive copper pillar 323. The process of removing the carrier board 340 can be completed by heating, lighting, etc. The specific removal method needs to be performed according to the characteristics of the bonding material 330.
接下来，在步骤460，如图3G所示，在裸露出第二芯片320的导电铜柱323的塑封层上面形成重新布局布线层380。重新布局布线层380与导电铜柱323电互连。在本发明的一个实施例中，重新布局布线层380可以具有一层或 多层，同时在相邻两层间或同层的导线间还设置有介质层以起到绝缘和保护作用。Next, in step 460, as shown in FIG. 3G, a redistribution wiring layer 380 is formed on the plastic encapsulation layer that exposes the conductive copper pillar 323 of the second chip 320. The rearrangement wiring layer 380 is electrically interconnected with the conductive copper pillar 323. In one embodiment of the present invention, the redistribution wiring layer 380 may have one or more layers, and a dielectric layer is also provided between adjacent two layers or between wires of the same layer for insulation and protection.
最后，在步骤470，如图3H所示，形成外接焊球390。外接焊球390设置在重新布局布线层380的最外层布线的外接焊盘位置。Finally, in step 470, as shown in FIG. 3H, circumscribed solder balls 390 are formed. The circumscribed solder balls 390 are provided at the circumscribed pad positions of the outermost wiring of the redistribution wiring layer 380.
基于本发明提供的该种Flash芯片堆叠的Fan-Out封装结构及其制造方法，基于扇出结构设计的封装，封装体中各层芯片通过引线键合互连，顶层芯片预设有重新布局布线层(RDL，Re-Distribution Layer)建立互连的镍钯金焊盘和导电铜柱，镍钯金焊盘与相邻层芯片通过引线键合互连，导电铜柱通过塑封减薄露头，然后再采用RDL和Bumping工艺互连实现最终堆叠封装结构。基于本发明的该种Flash芯片堆叠的Fan-Out封装结构具有相比现有flash产品更低的厚度，从而满足更多便携式、微型电子设备的要求。Based on the Fan-Out package structure of the Flash chip stack provided by the present invention and its manufacturing method, the package is designed based on the fan-out structure, the various layers of chips in the package body are interconnected by wire bonding, and the top chip is preset with re-layout wiring Layer (RDL, Re-Distribution Layer) establishes interconnected nickel-palladium gold pads and conductive copper pillars, the nickel-palladium gold pads and the adjacent layer chips are interconnected by wire bonding, the conductive copper pillars are thinned by plastic encapsulation, and then Then use RDL and Bumping process interconnection to achieve the final stacked package structure. The Fan-Out package structure based on the flash chip stack of the present invention has a lower thickness than existing flash products, thereby meeting the requirements of more portable and miniature electronic devices.
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined only in accordance with the appended claims and their equivalents.

Claims (10)

  1. 一种Flash芯片堆叠的Fan-Out封装结构，包括：A Fan-Out package structure of Flash chip stacking, including:
    多个第一Flash芯片，所述多个第一Flash芯片通过错位正装层贴设置在封装结构的底部；A plurality of first Flash chips, the plurality of first Flash chips are arranged on the bottom of the packaging structure through a misaligned formal mounting layer sticker;
    第二Flash芯片，所述第二Flash芯片通过错位正装层贴设置在最上层第一Flash芯片之上，其中每个第一Flash芯片和第二Flash芯片的焊盘不会被相邻芯片覆盖；A second Flash chip, the second Flash chip is disposed on the uppermost first Flash chip through a dislocation front-mounted layer paste, wherein the pads of each first Flash chip and the second Flash chip are not covered by adjacent chips;
    导电引线，所述导电引线电互连所述多个第一Flash芯片和第二Flash芯片；Conductive leads that electrically interconnect the plurality of first Flash chips and second Flash chips;
    塑封层，所述塑封层包覆所述多个第一Flash芯片和第二Flash芯片；A plastic encapsulation layer, the plastic encapsulation layer covering the plurality of first Flash chips and second Flash chips;
    重新布局布线层，所述重新布局布线层与所述第二Flash芯片电连接，并实现对封装结构的扇出功能。Re-laying the wiring layer, the re-laying wiring layer is electrically connected to the second Flash chip, and realizes a fan-out function to the packaging structure.
  2. 如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，还包括设置在所述多个第一Flash芯片和所述第二Flash芯片的相邻两者之间的DAF薄膜，所述DAF薄膜用于实现所述错位正装层贴。The Fan-Out package structure of the Flash chip stack according to claim 1, further comprising a DAF film disposed between adjacent ones of the plurality of first Flash chips and the second Flash chip , The DAF film is used to realize the misaligned formal dressing.
  3. 如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述第二Flash芯片还包括：The Fan-Out package structure of the Flash chip stack according to claim 1, wherein the second Flash chip further comprises:
    RDL层，所述RDL层设置在所述第二Flash芯片表面，且与所述第二Flash芯片的IO互连；An RDL layer, the RDL layer is provided on the surface of the second Flash chip and is interconnected with the IO of the second Flash chip;
    互连焊盘，所述互连焊盘电连接至所述RDL层，用于实现所述第二Flash芯片和所述第一Flash芯片的互连；以及An interconnection pad, the interconnection pad is electrically connected to the RDL layer, for interconnecting the second Flash chip and the first Flash chip; and
    导电铜柱。Conductive copper pillars.
  4. 如权利要求3所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述互连焊盘为镍钯金焊盘。The Fan-Out package structure of a stacked Flash chip according to claim 3, wherein the interconnection pad is a nickel-palladium gold pad.
  5. 如权利要求1或3所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述重新布局布线层通过所述导电铜柱、所述RDL层实现和所述第二Flash芯片电连接。The Fan-Out package structure of the Flash chip stack according to claim 1 or 3, wherein the redistribution wiring layer is electrically connected to the second Flash chip through the conductive copper pillar and the RDL layer .
  6. 如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于， 所述塑封层漏出最下层第一Flash芯片的背面。The Fan-Out package structure of the stacked Flash chips according to claim 1, wherein the plastic encapsulation layer leaks out the back surface of the first Flash chip at the lowermost layer.
  7. 如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述重新布局布线层具有N层重布线金属层，其中N≥2。The Fan-Out package structure of the Flash chip stack according to claim 1, wherein the redistribution wiring layer has an N-layer rewiring metal layer, where N≥2.
  8. 一种Flash芯片堆叠的Fan-Out封装结构的制造方法，包括：A method for manufacturing a Fan-Out package structure with stacked Flash chips includes:
    提供第一Flash芯片和第二Flash芯片，其中第二Flash芯片具有RDL层、引线焊盘和导电铜柱；Provide a first Flash chip and a second Flash chip, where the second Flash chip has an RDL layer, a lead pad and a conductive copper pillar;
    采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上，并漏出各芯片的引线焊盘；Use the DAF process to attach and bond multiple first Flash chips and one second Flash chip dislocation layer to the carrier board, and leak the lead pads of each chip;
    通过引线键合工艺电连接已完成错位层贴的第一Flash芯片和第二Flash芯片；Electrically connecting the first Flash chip and the second Flash chip that have completed the dislocation layer bonding through a wire bonding process;
    对完成引线键合的第一Flash芯片和第二Flash芯片进行整体塑封；Integrally mold the first Flash chip and the second Flash chip that have completed wire bonding;
    减薄塑封层并去除载板；Thin the plastic seal layer and remove the carrier board;
    在裸露出第二Flash芯片的导电铜柱的塑封层上面形成重新布局布线层。A redistribution wiring layer is formed on the plastic encapsulation layer that exposes the conductive copper pillar of the second Flash chip.
  9. 如权利要求8所述的方法，其特征在于，所述采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上进一步包括：The method according to claim 8, wherein the bonding and bonding the dislocation layers of the plurality of first Flash chips and one second Flash chip to the carrier board by the DAF process further comprises:
    将一个第一Flash芯片通过键合材料键合到载板上，形成最下层第一Flash芯片；Bond a first Flash chip to the carrier board with a bonding material to form the lowermost first Flash chip;
    利用DAF薄膜将多个第一Flash芯片依次错位层贴至最下层第一Flash芯片上；以及Use a DAF film to attach a plurality of first Flash chips to the first flash chip in the lowermost layer in sequence; and
    将一个第二Flash芯片错位层贴至最上层第一Flash芯片上。A second flash chip misalignment layer is pasted on the uppermost first flash chip.
  10. 如权利要求9所述的方法，其特征在于，所述载板为透光材料；所述键合材料为激光可拆键合材料。The method according to claim 9, wherein the carrier plate is a light-transmitting material; and the bonding material is a laser detachable bonding material.
PCT/CN2019/104927 2018-12-17 2019-09-09 Fan-out packaging structure for stacking flash chips and manufacturing method thereof WO2020125073A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811540270.6 2018-12-17
CN201811540270.6A CN109585431A (en) 2018-12-17 2018-12-17 A kind of fan-out packaging structure and its manufacturing method of Flash chip stacking

Publications (1)

Publication Number Publication Date
WO2020125073A1 true WO2020125073A1 (en) 2020-06-25

Family

ID=65930430

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/104927 WO2020125073A1 (en) 2018-12-17 2019-09-09 Fan-out packaging structure for stacking flash chips and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN109585431A (en)
WO (1) WO2020125073A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113078070A (en) * 2021-03-30 2021-07-06 无锡闻泰信息技术有限公司 Device plastic packaging method
CN116682743A (en) * 2023-05-15 2023-09-01 珠海妙存科技有限公司 Memory chip packaging method, memory chip and integrated circuit system

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109585431A (en) * 2018-12-17 2019-04-05 华进半导体封装先导技术研发中心有限公司 A kind of fan-out packaging structure and its manufacturing method of Flash chip stacking
CN111066144B (en) * 2019-11-29 2021-10-15 长江存储科技有限责任公司 Chip packaging structure and manufacturing method thereof
CN111883521B (en) * 2020-07-13 2022-03-01 矽磐微电子(重庆)有限公司 Multi-chip 3D packaging structure and manufacturing method thereof
CN112614830A (en) * 2020-11-30 2021-04-06 华为技术有限公司 Encapsulation module and electronic equipment
CN114975415A (en) * 2022-04-29 2022-08-30 盛合晶微半导体(江阴)有限公司 Fan-out stacked semiconductor packaging structure and packaging method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110068481A1 (en) * 2009-09-23 2011-03-24 Sung-Kyu Park Package-on-package type semiconductor package and method for fabricating the same
US20170033084A1 (en) * 2015-07-29 2017-02-02 Powertech Technology Inc. Multi-chip package having encapsulation body to replace substrate core
CN107579061A (en) * 2016-07-04 2018-01-12 晟碟信息科技（上海）有限公司 The semiconductor device of superposition packaging body comprising interconnection
CN108695284A (en) * 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 Include the semiconductor equipment of Top-down design semiconductor package body group
CN109585431A (en) * 2018-12-17 2019-04-05 华进半导体封装先导技术研发中心有限公司 A kind of fan-out packaging structure and its manufacturing method of Flash chip stacking

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101605600B1 (en) * 2014-02-04 2016-03-22 앰코 테크놀로지 코리아 주식회사 Manufacturing method of semiconductor device and semiconductor device thereof
TWI567897B (en) * 2016-06-02 2017-01-21 力成科技股份有限公司 Thin fan-out stacked chip package and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110068481A1 (en) * 2009-09-23 2011-03-24 Sung-Kyu Park Package-on-package type semiconductor package and method for fabricating the same
US20170033084A1 (en) * 2015-07-29 2017-02-02 Powertech Technology Inc. Multi-chip package having encapsulation body to replace substrate core
CN107579061A (en) * 2016-07-04 2018-01-12 晟碟信息科技（上海）有限公司 The semiconductor device of superposition packaging body comprising interconnection
CN108695284A (en) * 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 Include the semiconductor equipment of Top-down design semiconductor package body group
CN109585431A (en) * 2018-12-17 2019-04-05 华进半导体封装先导技术研发中心有限公司 A kind of fan-out packaging structure and its manufacturing method of Flash chip stacking

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113078070A (en) * 2021-03-30 2021-07-06 无锡闻泰信息技术有限公司 Device plastic packaging method
CN116682743A (en) * 2023-05-15 2023-09-01 珠海妙存科技有限公司 Memory chip packaging method, memory chip and integrated circuit system
CN116682743B (en) * 2023-05-15 2024-01-23 珠海妙存科技有限公司 Memory chip packaging method, memory chip and integrated circuit system

Also Published As

Publication number Publication date
CN109585431A (en) 2019-04-05

Similar Documents

Publication Publication Date Title
WO2020125073A1 (en) Fan-out packaging structure for stacking flash chips and manufacturing method thereof
US11239157B2 (en) Package structure and package-on-package structure
US10056350B2 (en) Fan-out package structure, and manufacturing method thereof
US10170458B2 (en) Manufacturing method of package-on-package structure
US10276545B1 (en) Semiconductor package and manufacturing method thereof
EP2033220B1 (en) Stack die packages
TWI225670B (en) Packaging method of multi-chip module
WO2017049928A1 (en) Chip packaging structure and packaging method therefor
CN107403733A (en) Three layer laminate encapsulating structures and forming method thereof
CN111052371A (en) Semiconductor device with laterally offset stacked semiconductor die
CN107851615A (en) Independent 3D is stacked
TW201721771A (en) Integrated fan-out package and the methods of manufacturing
TW201041106A (en) Substrate having single patterned metal foil, and package applied with the same, and methods of manufacturing the substrate and package
CN107706521A (en) Fan-out-type antenna packages structure and preparation method thereof
CN107039287A (en) Bilateral is integrated to be fanned out to packaging part
CN107742778A (en) Fan-out-type antenna packages structure and preparation method thereof
CN107706520A (en) Fan-out-type antenna packages structure and preparation method thereof
CN107622996B (en) Three-dimensional high-density fan-out type packaging structure and manufacturing method thereof
TW200805620A (en) Method of packaging a plurality of integrated circuit devices and semiconductor package so formed
CN115547961A (en) High-density integrated three-dimensional chip packaging structure and manufacturing method thereof
CN110854093A (en) Three-dimensional laminated packaging structure and manufacturing method thereof
CN112349608A (en) Manufacturing method of chip packaging structure
US20220148975A1 (en) Electronic package and manufacturing method thereof
WO2024051124A1 (en) Multi-layer high bandwidth memory and manufacturing method therefor
CN207852897U (en) Fan-out-type antenna packages structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19899703

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19899703

Country of ref document: EP

Kind code of ref document: A1