TWI700786B - Chip-on-film package structure - Google Patents

Chip-on-film package structure Download PDF

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TWI700786B
TWI700786B TW107110823A TW107110823A TWI700786B TW I700786 B TWI700786 B TW I700786B TW 107110823 A TW107110823 A TW 107110823A TW 107110823 A TW107110823 A TW 107110823A TW I700786 B TWI700786 B TW I700786B
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chip
chips
side surfaces
buffer
glue
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TW107110823A
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TW201943031A (en
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陳崇龍
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南茂科技股份有限公司
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Priority to CN201810480052.1A priority patent/CN110323184B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A chip-on-film package structure includes a flexible substrate, a plurality of leads, two chips, a buffer component, and an encapsulant. The leads are disposed on the flexible substrate and extend outwardly from a chip bonding area. The two chips are arranged side by side in the chip bonding area, and are respectively electrically connected with the leads. Each chip has an active surface, a back surface opposite to the active surface, and a plurality of side surfaces connecting the active surface and the back surface. These side surfaces include a short side surface connecting a short side of the active surface. The two chips are arranged side by side with their short side surfaces facing each other. The buffer component is disposed on the flexible substrate and between the two chips. The encapsulant at least fills in the space between each chip and the flexible substrate and covers the side surfaces of each chip. The buffer component is coupled to the two chips through the encapsulant.

Description

薄膜覆晶封裝結構Thin film flip chip package structure

本發明是有關於一種封裝結構，且特別是有關於一種薄膜覆晶封裝結構。The present invention relates to a packaging structure, and more particularly to a thin-film-on-chip packaging structure.

由於液晶顯示器具有低消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點，因而廣泛地應用在行動電話、筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。為配合液晶顯示裝置中超高數量的電性訊號傳輸，目前普遍採用捲帶自動接合(tape automatic bonding, TAB)技術進行驅動晶片的封裝，而薄膜覆晶(chip on film, COF)封裝結構便是其中一種應用捲帶自動接合技術的封裝結構。Because LCD displays have the advantages of low power consumption, thin and light weight, high resolution, high color saturation, and long life span, they are widely used in mobile phones, laptops or desktop computers, LCD screens and LCD TVs, etc. Electronic products closely related to life. In order to cooperate with the ultra-high number of electrical signal transmissions in liquid crystal display devices, tape automatic bonding (TAB) technology is generally used to drive the chip packaging, and the chip on film (COF) packaging structure is One of them is a packaging structure using tape and reel automatic bonding technology.

隨著科技不斷的進步，電子產品的功能需求也越來越多，晶片的體積電路密度因此必須不斷地提高，液晶顯示裝置的驅動晶片亦然。液晶顯示裝置的驅動晶片上的高I/O端點數使得I/O端點的配置集中於晶片主動面上的相對兩側，驅動晶片的外型因此設計成長寬差異頗大的細長型。為能容置更多的I/O端點，驅動晶片的長度也須增長。然而，增長晶片雖然可以增加端點數量，但長度過長的細長型晶片極容易斷裂且較難操作，因此，改以兩顆並排的晶片來取代一顆加長晶片。但兩顆並排的晶片之間未有阻隔物時，可撓性基板彎曲即可能導致兩顆並排的晶片互相碰撞擠壓。當填充封裝膠體於兩顆晶片之間作阻隔保護時，又因為兩顆晶片之間的位置缺乏支撐，填充於其中的封裝膠體固化時產生收縮而導致整個薄膜覆晶封裝結構產生於兩晶片之間向下而兩側向上的翹曲現象，同樣可能導致兩顆晶片互相碰撞擠壓，進而影響了電子產品的可靠度。With the continuous advancement of technology, there are more and more functional requirements for electronic products. Therefore, the volume circuit density of the chip must be continuously increased, as is the driving chip of the liquid crystal display device. The high number of I/O terminals on the driving chip of the liquid crystal display device makes the configuration of the I/O terminals concentrated on the opposite sides of the active surface of the chip, and the appearance of the driving chip is therefore designed to be a slender type with a large difference in growth and width. In order to accommodate more I/O endpoints, the length of the driver chip must also be increased. However, although an extended chip can increase the number of endpoints, an elongated chip with a long length is extremely easy to break and is difficult to handle. Therefore, two side-by-side chips are used instead of one extended chip. However, when there is no barrier between the two side-by-side chips, the bending of the flexible substrate may cause the two side-by-side chips to collide and squeeze each other. When the encapsulant is filled for barrier protection between the two chips, and because the position between the two chips lacks support, the encapsulant filled therein shrinks when it solidifies, resulting in the entire thin-film flip-chip packaging structure being generated between the two chips. The warping phenomenon of downwards and upwards on both sides may also cause the two chips to collide and squeeze each other, thereby affecting the reliability of electronic products.

本發明提供一種薄膜覆晶封裝結構，可避免產生翹曲導致並排兩晶片互相碰撞擠壓，且可具有較佳的可靠度。The present invention provides a film-on-chip packaging structure, which can avoid warping and cause two side-by-side chips to collide and squeeze each other, and has better reliability.

本發明的薄膜覆晶封裝結構包括可撓性基材、多個引腳、二個晶片、緩衝件及封裝膠體。可撓性基材具有晶片接合區。多個引腳設置於可撓性基材上，並自晶片接合區內向外延伸。二個晶片並列設置於可撓性基材的晶片接合區內，且分別電性連接這些引腳。各晶片具有主動表面、相對於主動表面的背表面以及連接主動表面與背表面的多個側表面。這些側表面包括連接主動表面的短邊的短邊側表面。二個晶片以短邊側表面互相面對而並排設置。緩衝件設置於可撓性基材上且位於二個晶片之間。封裝膠體至少填充於各晶片與可撓性基材之間且覆蓋各晶片的這些側表面。緩衝件透過封裝膠體與二個晶片耦接。The film-on-chip packaging structure of the present invention includes a flexible substrate, a plurality of pins, two chips, a buffer, and a packaging gel. The flexible substrate has a wafer bonding area. A plurality of pins are arranged on the flexible substrate and extend outward from the chip bonding area. The two chips are arranged side by side in the chip bonding area of the flexible substrate, and are electrically connected to these pins respectively. Each wafer has an active surface, a back surface opposite to the active surface, and a plurality of side surfaces connecting the active surface and the back surface. These side surfaces include short side side surfaces connecting the short sides of the active surface. The two wafers are arranged side by side with the short side surfaces facing each other. The buffer is arranged on the flexible substrate and located between the two chips. The encapsulant is filled at least between each chip and the flexible substrate and covers the side surfaces of each chip. The buffer is coupled to the two chips through the packaging glue.

基於上述，本發明的薄膜覆晶封裝結構，利用在二個並排設置的晶片的短邊側表面之間配置緩衝件，以在二個晶片之間的位置提供阻隔與支撐，再以封裝膠體填充於各晶片的短邊側表面與緩衝件之間的區域，以加強固定緩衝件與各晶片之間的相對位置並強化二個晶片之間的區域的硬度。緩衝件在二個晶片之間提供了阻隔與支撐，可避免薄膜覆晶封裝結構因封裝膠體固化收縮產生翹曲而造成二個晶片互相碰撞擠壓。此外，由於緩衝件的設置，減少了二個晶片之間所填充的封裝膠體的量，使得封裝膠體的收縮程度隨之降低。如此一來，可避免薄膜覆晶封裝結構產生翹曲而造成二個晶片互相碰撞擠壓，進而可提高薄膜覆晶封裝結構的可靠度。Based on the above, the thin-film-on-chip package structure of the present invention utilizes a buffer between the short side surfaces of two chips arranged side by side to provide barrier and support at the position between the two chips, and then is filled with packaging gel The area between the short side surface of each wafer and the buffer member is used to strengthen the relative position between the fixed buffer member and each wafer and to strengthen the hardness of the area between the two wafers. The buffer member provides barrier and support between the two chips, which can prevent the film-on-chip packaging structure from warping due to the curing shrinkage of the packaging colloid and causing the two chips to collide and squeeze each other. In addition, due to the arrangement of the buffer, the amount of packaging glue filled between the two chips is reduced, so that the shrinkage of the packaging glue is reduced accordingly. In this way, it is possible to prevent the two chips from colliding and squeezing due to warpage of the thin film on chip package structure, thereby improving the reliability of the thin film on chip package structure.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1A是依照本發明一實施例的一種薄膜覆晶封裝結構的示意圖。圖1B是圖1A的薄膜覆晶封裝結構沿A-A’的剖面示意圖。請參照圖1A與圖1B，在本實施例中，薄膜覆晶封裝結構100包括可撓性基材110、多個引腳120、二個晶片130、緩衝件150及封裝膠體160。可撓性基材110的材質例如是聚醯亞胺(PI)、聚酯樹脂(PET)或其他可撓曲的絕緣材質，其中可撓性基材110具有晶片接合區112。這些引腳120設置於可撓性基材110上，並自晶片接合區112內向外延伸。接著，二個晶片130並列設置於可撓性基材110的晶片接合區112內，且透過凸塊138分別電性連接這些引腳120。在本實施例中，二個晶片130之間的距離D例如是不大於10毫米。FIG. 1A is a schematic diagram of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 1A along A-A'. 1A and 1B, in this embodiment, the film-on-chip package structure 100 includes a flexible substrate 110, a plurality of pins 120, two chips 130, a buffer 150, and a packaging gel 160. The material of the flexible substrate 110 is, for example, polyimide (PI), polyester resin (PET) or other flexible insulating materials, wherein the flexible substrate 110 has a chip bonding area 112. The pins 120 are disposed on the flexible substrate 110 and extend outward from the chip bonding area 112. Then, the two chips 130 are arranged side by side in the chip bonding area 112 of the flexible substrate 110, and are electrically connected to the pins 120 through the bumps 138, respectively. In this embodiment, the distance D between the two wafers 130 is, for example, not more than 10 mm.

詳細來說，各晶片130具有主動表面132、相對於主動表面132的背表面134以及連接主動表面132與背表面134的多個側表面136。其中，各晶片130的主動表面132分別具有二個短邊1322以及二個長邊1324。在本實施例中，短邊1322的長度H例如是不大於4毫米。在本實施例中，這些側表面136包括分別連接主動表面132的二個短邊1322的二個短邊側表面1362，以及分別連接主動表面132的二個長邊1324的二個長邊側表面1364。二個晶片130以短邊側表面1362互相面對而並排設置。緩衝件150設置於可撓性基材110上且位於二個晶片130之間。封裝膠體160至少填充於各晶片130與可撓性基材110之間且覆蓋各晶片130的這些側表面136。換言之，封裝膠體160覆蓋各晶片130的主動表面132，且封裝膠體160更覆蓋各晶片130的二個短邊側表面1362以及二個長邊側表面1364。In detail, each chip 130 has an active surface 132, a back surface 134 opposite to the active surface 132, and a plurality of side surfaces 136 connecting the active surface 132 and the back surface 134. The active surface 132 of each chip 130 has two short sides 1322 and two long sides 1324 respectively. In this embodiment, the length H of the short side 1322 is, for example, not more than 4 mm. In this embodiment, the side surfaces 136 include two short side surfaces 1362 respectively connected to the two short sides 1322 of the active surface 132, and two long side side surfaces respectively connected to the two long sides 1324 of the active surface 132 1364. The two wafers 130 are arranged side by side with the short side surfaces 1362 facing each other. The buffer 150 is disposed on the flexible substrate 110 and located between the two chips 130. The encapsulant 160 is filled at least between each chip 130 and the flexible substrate 110 and covers the side surfaces 136 of each chip 130. In other words, the encapsulant 160 covers the active surface 132 of each chip 130, and the encapsulant 160 further covers the two short side surfaces 1362 and the two long side surfaces 1364 of each chip 130.

緩衝件150透過封裝膠體160與二個晶片130耦接。更進一步而言，在本實施例中，緩衝件150的配置方式如下所述。待二個晶片130分別設置於可撓性基材110的晶片接合區112內且電性連接引腳120之後，先將緩衝件150設置於可撓性基材110上，使緩衝件150位於二個晶片130之間，即位於二個晶片130的短邊側表面1362之間。此時，緩衝件150可例如是以黏貼或熱壓接合的方式固定於可撓性基材110上，但不以此為限。接著，再以封裝膠體160填充於各晶片130與可撓性基材110之間，以覆蓋二個晶片130的主動表面132、短邊側表面1362以及長邊側表面1364。其中，封裝膠體160更填充於各晶片130的短邊側表面1362與緩衝件150之間的區域，使緩衝件150與二個晶片130耦接，以固定緩衝件150、確保緩衝件150與二個晶片130之間的相對位置並加強此區域的硬度。在本實施例中，緩衝件150例如是包括耐熱材料，可耐受溫度例如是不低於150℃，舉例來說，例如是酚醛樹脂(電木)、聚醚醚酮(polyetheretherketone，PEEK)、鐵氟龍、聚醯亞胺(polyimide)、石墨烯或其他適合的耐熱材料。The buffer 150 is coupled to the two chips 130 through the packaging compound 160. Furthermore, in this embodiment, the configuration of the buffer 150 is as follows. After the two chips 130 are respectively disposed in the chip bonding area 112 of the flexible substrate 110 and are electrically connected to the pins 120, the buffer 150 is first disposed on the flexible substrate 110 so that the buffer 150 is located on the two Between the two wafers 130, that is, between the short side surfaces 1362 of the two wafers 130. At this time, the buffer member 150 may be fixed on the flexible substrate 110 in a manner of, for example, pasting or thermocompression bonding, but it is not limited thereto. Then, an encapsulant 160 is filled between each chip 130 and the flexible substrate 110 to cover the active surface 132, the short side surface 1362 and the long side surface 1364 of the two chips 130. Wherein, the packaging glue 160 is further filled in the area between the short side surface 1362 of each chip 130 and the buffer 150, so that the buffer 150 is coupled to the two chips 130 to fix the buffer 150 and ensure that the buffer 150 and the two The relative position between the two wafers 130 enhances the hardness of this area. In this embodiment, the buffer member 150 includes, for example, a heat-resistant material, and the tolerable temperature is, for example, not less than 150°C. For example, such as phenolic resin (bakelite), polyetheretherketone (PEEK), Teflon, polyimide, graphene or other suitable heat-resistant materials.

在本實施例中，薄膜覆晶封裝結構100還包括防焊層170。其中，防焊層170配置於可撓性基材110上，且局部覆蓋引腳120但暴露出晶片接合區112。In this embodiment, the film-on-chip package structure 100 further includes a solder mask 170. Wherein, the solder mask 170 is disposed on the flexible substrate 110 and partially covers the pins 120 but exposes the die bonding area 112.

在本實施例中，可撓性基材110還具有相對的兩傳輸區116、117以及多個傳輸孔118，其中這些傳輸孔118分別位於傳輸區116與117內，且貫穿可撓性基材110。這些傳輸孔118沿著垂直於主動表面132的長邊1324的方向排列，且這些傳輸孔118的配置用以與傳輸機構配合而帶動可撓性基材110移動。實務上，在完成捲帶式薄膜覆晶封裝後，可撓性基材110中相對的兩傳輸區116、117會被移除，也就是說，最後製作所得到的薄膜覆晶封裝結構100並不具有傳輸區116、117，圖式中繪示出兩傳輸區116、117是用以說明薄膜覆晶封裝結構100係透過捲帶式薄膜覆晶封裝技術製作而得。In this embodiment, the flexible substrate 110 further has two opposite transmission areas 116 and 117 and a plurality of transmission holes 118, wherein the transmission holes 118 are respectively located in the transmission areas 116 and 117 and penetrate the flexible substrate 110. The transmission holes 118 are arranged along a direction perpendicular to the long side 1324 of the active surface 132, and the transmission holes 118 are configured to cooperate with the transmission mechanism to drive the flexible substrate 110 to move. In practice, after the tape-to-reel TFT-on-film packaging is completed, the two opposite transmission regions 116 and 117 in the flexible substrate 110 will be removed. That is to say, the resulting TFT-on-film packaging structure 100 is not There are transmission areas 116 and 117. The two transmission areas 116 and 117 are shown in the figure to illustrate that the film-on-chip packaging structure 100 is manufactured by the tape-to-reel thin-film-on-chip packaging technology.

基於上述的設計，利用在二個並排設置的晶片130的短邊側表面1362之間配置緩衝件150，以在二個晶片130之間的位置提供阻隔與支撐，再以封裝膠體160填充於各晶片130的短邊側表面1362與緩衝件150之間的區域，以加強固定緩衝件150與各晶片130之間的相對位置並強化二個晶片130之間的區域的硬度。緩衝件150在二個晶片130之間提供了阻隔與支撐，可避免薄膜覆晶封裝結構100因封裝膠體160固化收縮產生翹曲而造成二個晶片130互相碰撞擠壓。此外，由於緩衝件150的設置，減少了二個晶片130之間所填充的封裝膠體160的量，封裝膠體160的收縮程度隨之降低，進而避免薄膜覆晶封裝結構100產生翹曲而造成二個晶片130互相碰撞擠壓。Based on the above design, a buffer 150 is arranged between the short side surfaces 1362 of the two wafers 130 arranged side by side to provide barrier and support at the position between the two wafers 130, and then the encapsulant 160 is used to fill each The area between the short side surface 1362 of the wafer 130 and the buffer 150 is used to strengthen the relative position between the buffer 150 and each wafer 130 and strengthen the hardness of the area between the two wafers 130. The buffer 150 provides barrier and support between the two chips 130, which can prevent the film-on-chip packaging structure 100 from warping due to the curing shrinkage of the packaging compound 160 and causing the two chips 130 to collide and squeeze. In addition, due to the arrangement of the buffer 150, the amount of the packaging compound 160 filled between the two chips 130 is reduced, and the shrinkage of the packaging compound 160 is reduced accordingly, thereby avoiding the warpage of the thin-film-on-chip packaging structure 100 and causing two The two wafers 130 collide and squeeze each other.

以下將列舉其他實施例以作為說明。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。Other embodiments will be listed below for description. It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

圖2A是依照本發明另一實施例的一種薄膜覆晶封裝結構的示意圖。圖2B是圖2A的薄膜覆晶封裝結構沿B-B’的剖面示意圖。請參照圖2A與圖2B，圖2A(圖2B)的薄膜覆晶封裝結構100a與圖1A(圖1B)的薄膜覆晶封裝結構100的主要差異在於：封裝膠體160更包括二個第一膠體162、163以及第二膠體164。其中，各晶片130的主動表面132與其側表面136被對應的第一膠體162、163所覆蓋，且第二膠體164耦接二個第一膠體162、163與緩衝件150。在本實施例中，第二膠體164可以包括散熱/導熱膠、紫外線硬化膠或其他適合的材質。2A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 2B is a schematic cross-sectional view along B-B' of the chip-on-film package structure of FIG. 2A. Please refer to FIGS. 2A and 2B. The main difference between the thin film on chip package structure 100a of FIG. 2A (FIG. 2B) and the thin film on chip package structure 100 of FIG. 1A (FIG. 1B) is that the packaging glue 160 further includes two first glues 162, 163 and the second colloid 164. Wherein, the active surface 132 and the side surface 136 of each chip 130 are covered by the corresponding first glues 162 and 163, and the second glue 164 is coupled to the two first glues 162, 163 and the buffer 150. In this embodiment, the second glue 164 may include heat dissipation/thermal conductivity glue, ultraviolet curing glue or other suitable materials.

詳細來說，請繼續參照圖2A與圖2B，各第一膠體162、163具有覆蓋對應的晶片130的短邊側表面1362的內側部分1622、1632。二個晶片130所對應的這些內側部分1622、1632之間具有間隔區114，且緩衝件150位於間隔區114中。此外，第二膠體164包覆二個第一膠體162、163及緩衝件150的周圍，並填充於間隔區114內。第二膠體164更覆蓋二個晶片130的這些背表面134與緩衝件150的頂面152。In detail, please continue to refer to FIGS. 2A and 2B, each of the first glue bodies 162 and 163 has inner parts 1622 and 1632 covering the short side surface 1362 of the corresponding chip 130. The inner portions 1622 and 1632 corresponding to the two chips 130 have a spacer 114 between them, and the buffer 150 is located in the spacer 114. In addition, the second gel 164 covers the surroundings of the two first gels 162 and 163 and the buffer 150 and fills the space 114. The second glue 164 further covers the back surfaces 134 of the two chips 130 and the top surface 152 of the buffer 150.

圖3A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖3B是圖3A的薄膜覆晶封裝結構沿C-C’的截面示意圖。請參照圖3A與圖3B，圖3A(圖3B)的薄膜覆晶封裝結構100b與圖2A(圖2B)的薄膜覆晶封裝結構100a的主要差異在於：第二膠體164未覆蓋二個晶片130的這些背表面134與緩衝件150的頂面152。FIG. 3A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 3B is a schematic cross-sectional view along C-C' of the chip-on-film package structure of FIG. 3A. Please refer to FIGS. 3A and 3B. The main difference between the thin film on chip package structure 100b of FIG. 3A (FIG. 3B) and the thin film on chip package structure 100a of FIG. 2A (FIG. 2B) is that the second glue 164 does not cover the two chips 130 The back surface 134 and the top surface 152 of the buffer 150.

詳細來說，請繼續參照圖3A與圖3B，各晶片130的主動表面132、短邊側表面1362以及長邊側表面1364被對應的第一膠體162、163所覆蓋。此外，第二膠體164包覆二個第一膠體162、163及緩衝件150的周圍，並填充於間隔區114內。第二膠體164暴露出二個晶片130的背表面134與緩衝件150的頂面152。第二膠體164耦接二個第一膠體162、163與緩衝件150。在本實施例中，二個晶片130的這些背表面134不被第二膠體164所覆蓋而為裸露，晶片130於運作中所產生的熱可透過背表面134進行消散，因此可增加散熱效率。In detail, please continue to refer to FIGS. 3A and 3B. The active surface 132, the short side surface 1362, and the long side surface 1364 of each chip 130 are covered by the corresponding first gels 162 and 163. In addition, the second gel 164 covers the surroundings of the two first gels 162 and 163 and the buffer 150 and fills the space 114. The second glue 164 exposes the back surface 134 of the two chips 130 and the top surface 152 of the buffer 150. The second glue 164 is coupled to the two first glues 162 and 163 and the buffer 150. In this embodiment, the back surfaces 134 of the two chips 130 are not covered by the second glue 164 and are exposed. The heat generated by the chip 130 during operation can be dissipated through the back surface 134, thus increasing the heat dissipation efficiency.

圖4A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖4B是圖4A的薄膜覆晶封裝結構沿D-D’的截面示意圖。請參照圖4A與圖4B，圖4A(圖4B)的薄膜覆晶封裝結構100c與圖3A(圖3B)的薄膜覆晶封裝結構100b的主要差異在於：緩衝件150具有分別相鄰於二個第一膠體162、163的內側部分1622、1632的二個相對的第二側面156。其中，第二膠體164並未填充於內側部分1622、1632與第二側面156之間。4A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 4B is a schematic cross-sectional view along D-D' of the chip-on-film package structure of FIG. 4A. Please refer to FIGS. 4A and 4B. The main difference between the chip-on-film package structure 100c in FIG. 4A (FIG. 4B) and the chip-on-chip package structure 100b in FIG. 3A (FIG. 3B) is that the buffer 150 has two adjacent The inner side portions 1622, 1632 of the first glue body 162, 163 have two opposite second side surfaces 156. The second gel 164 is not filled between the inner portion 1622, 1632 and the second side surface 156.

詳細來說，在本實施例中，各第一膠體162、163具有覆蓋對應的晶片130的二個長邊側表面1364的二個外側部分1626、1636以及覆蓋鄰近晶片接合區112邊緣的短邊側表面1362的外側部分1628、1638，緩衝件150具有分別鄰近各晶片130的二個長邊側表面1364的二個相對的第一側面154。第二膠體164包覆二個第一膠體162、163的這些外側部分1626、1628、1636、1638與緩衝件150的這些第一側面154。換言之，在本實施例中，緩衝件150是透過第二膠體164連接第一側面154與第一膠體162、163的外側部分1626、1636而與二個晶片130耦接。In detail, in this embodiment, each of the first gels 162, 163 has two outer portions 1626, 1636 covering the two long side surfaces 1364 of the corresponding chip 130, and a short side covering the edge of the adjacent chip bonding area 112. On the outer portions 1628 and 1638 of the side surface 1362, the buffer 150 has two opposite first side surfaces 154 adjacent to the two long side surfaces 1364 of each wafer 130, respectively. The second gel 164 covers the outer portions 1626, 1628, 1636, 1638 of the two first gels 162 and 163 and the first side surfaces 154 of the buffer 150. In other words, in this embodiment, the buffer 150 is coupled to the two chips 130 by connecting the first side surface 154 and the outer portions 1626 and 1636 of the first plastic bodies 162 and 163 through the second glue body 164.

圖5A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖5B是圖5A的薄膜覆晶封裝結構沿E-E’的剖面示意圖。請參照圖5A與圖5B，圖5A(圖5B)的薄膜覆晶封裝結構100d與圖4A(圖4B)的薄膜覆晶封裝結構100c的主要差異在於：第二膠體164僅包覆二個第一膠體162、163的內側部分1622、1632與緩衝件150的第二側面156。5A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 5B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 5A along E-E'. Referring to FIGS. 5A and 5B, the main difference between the thin film on chip package structure 100d in FIG. 5A (FIG. 5B) and the thin film on chip package structure 100c in FIG. 4A (FIG. 4B) is that the second glue 164 only covers two The inner part 1622, 1632 of a glue body 162, 163 and the second side 156 of the buffer 150.

詳細來說，第二膠體164覆蓋二個第一膠體162、163的內側部分1622、1632、緩衝件150的第一側面154、緩衝件150的第二側面156以及緩衝件150的頂面152。換言之，在本實施例中，緩衝件150是透過第二膠體164連接第二側面156與第一膠體162、163的內側部分1622、1632而與二個晶片130耦接。In detail, the second glue 164 covers the inner portions 1622, 1632 of the two first glues 162 and 163, the first side surface 154 of the buffer 150, the second side 156 of the buffer 150, and the top surface 152 of the buffer 150. In other words, in this embodiment, the buffer 150 is coupled to the two chips 130 by connecting the second side surface 156 and the inner portions 1622, 1632 of the first glue 162, 163 through the second glue 164.

綜上所述，本發明的薄膜覆晶封裝結構，利用在二個並排設置的晶片的短邊側表面之間配置緩衝件，以在二個晶片之間的位置提供阻隔與支撐，再以封裝膠體填充於各晶片的短邊側表面與緩衝件之間的區域，以加強固定緩衝件與各晶片之間的相對位置並強化二個晶片之間的區域的硬度。緩衝件在二個晶片之間提供了阻隔與支撐，可避免薄膜覆晶封裝結構因封裝膠體固化收縮產生翹曲而造成二個晶片互相碰撞擠壓。此外，由於緩衝件的設置，減少了二個晶片之間所填充的封裝膠體的量，使得封裝膠體的收縮程度隨之降低。如此一來，可避免薄膜覆晶封裝結構產生翹曲而造成二個晶片互相碰撞擠壓，進而可提高薄膜覆晶封裝結構的可靠度。In summary, the thin-film-on-chip package structure of the present invention utilizes a buffer between the short side surfaces of two chips arranged side by side to provide barrier and support between the two chips, and then package The gel is filled in the area between the short side surface of each chip and the buffer to strengthen the relative position between the fixed buffer and each chip and to strengthen the hardness of the area between the two chips. The buffer member provides barrier and support between the two chips, which can prevent the film-on-chip packaging structure from warping due to the curing shrinkage of the packaging colloid and causing the two chips to collide and squeeze each other. In addition, due to the arrangement of the buffer, the amount of packaging glue filled between the two chips is reduced, so that the shrinkage of the packaging glue is reduced accordingly. In this way, it is possible to prevent the two chips from colliding and squeezing due to warpage of the thin film on chip package structure, thereby improving the reliability of the thin film on chip package structure.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100、100a、100b、100c、100d‧‧‧薄膜覆晶封裝結構110‧‧‧可撓性基材112‧‧‧晶片接合區114‧‧‧間隔區120‧‧‧引腳130‧‧‧晶片132‧‧‧主動表面1322‧‧‧短邊1324‧‧‧長邊134‧‧‧背表面136‧‧‧側表面1362‧‧‧短邊側表面1364‧‧‧長邊側表面138‧‧‧凸塊150‧‧‧緩衝件152‧‧‧頂面154‧‧‧第一側面156‧‧‧第二側面160‧‧‧封裝膠體162‧‧‧第一膠體1622‧‧‧內側部分1626、1628‧‧‧外側部分163‧‧‧第一膠體1632‧‧‧內側部分1636、1638‧‧‧外側部分164‧‧‧第二膠體170‧‧‧防焊層D‧‧‧距離H‧‧‧長度100, 100a, 100b, 100c, 100d‧‧‧Thin film flip chip package structure 110‧‧‧Flexible substrate 112‧‧‧Chip bonding area 114‧‧‧Spacer area 120‧‧‧Pin 130‧‧‧Chip 132‧‧‧Active surface 1322‧‧‧Short side 1324‧‧‧Long side 134‧‧Back surface 136‧‧‧Side surface 1362‧‧‧Short side side surface 1364‧‧‧Long side side surface 138‧‧‧ Bump 150‧‧‧Buffer 152‧‧‧Top surface 154‧‧‧First side 156‧‧‧Second side 160‧‧‧Packaging glue 162‧‧‧First glue 1622‧‧‧Inner part 1626, 1628 ‧‧‧Outer part 163‧‧‧First gel 1632‧‧‧Inner part 1636, 1638‧‧‧Outer part 164‧‧‧Second gel 170‧‧‧Soldering layer D‧‧‧Distance H‧‧‧Length

圖1A是依照本發明一實施例的一種薄膜覆晶封裝結構的示意圖。 圖1B是圖1A的薄膜覆晶封裝結構沿A-A’的剖面示意圖。 圖2A是依照本發明另一實施例的一種薄膜覆晶封裝結構的示意圖。 圖2B是圖2A的薄膜覆晶封裝結構沿B-B’的剖面示意圖。 圖3A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖3B是圖3A的薄膜覆晶封裝結構沿C-C’的截面示意圖。 圖4A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖4B是圖4A的薄膜覆晶封裝結構沿D-D’的截面示意圖。 圖5A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖5B是圖5A的薄膜覆晶封裝結構沿E-E’的剖面示意圖。FIG. 1A is a schematic diagram of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 1A along A-A'. 2A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 2B is a schematic cross-sectional view along B-B' of the chip-on-film package structure of FIG. 2A. FIG. 3A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 3B is a schematic cross-sectional view along C-C' of the chip-on-film package structure of FIG. 3A. 4A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 4B is a schematic cross-sectional view along D-D' of the chip-on-film package structure of FIG. 4A. 5A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 5B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 5A along E-E'.

100‧‧‧薄膜覆晶封裝結構 100‧‧‧Thin Film Flip Chip Package Structure

110‧‧‧可撓性基材 110‧‧‧Flexible substrate

120‧‧‧引腳 120‧‧‧pin

130‧‧‧晶片 130‧‧‧chip

132‧‧‧主動表面 132‧‧‧Active surface

134‧‧‧背表面 134‧‧‧Back surface

136‧‧‧側表面 136‧‧‧Side surface

1362‧‧‧短邊側表面 1362‧‧‧Short side surface

1364‧‧‧長邊側表面 1364‧‧‧Long side surface

138‧‧‧凸塊 138‧‧‧ bump

150‧‧‧緩衝件 150‧‧‧Buffer

160‧‧‧封裝膠體 160‧‧‧Packaging gel

170‧‧‧防焊層 170‧‧‧Solder Protection Layer

D‧‧‧距離 D‧‧‧Distance

Claims (8)

一種薄膜覆晶封裝結構，包括：一可撓性基材，具有一晶片接合區；多個引腳，設置於該可撓性基材上，並自該晶片接合區內向外延伸；二個晶片，並列設置於該可撓性基材的該晶片接合區內，且分別電性連接該些引腳，其中各該晶片具有一主動表面、相對於該主動表面的一背表面以及連接該主動表面與該背表面的多個側表面，該些側表面包括連接該主動表面的一短邊的一短邊側表面，其中該二個晶片以該短邊側表面互相面對而並排設置；一緩衝件，設置於該可撓性基材上，且位於該二個晶片之間；以及一封裝膠體，至少填充於各該晶片與該可撓性基材之間且覆蓋各該晶片的該些側表面，且該緩衝件透過該封裝膠體與該二個晶片耦接，其中該封裝膠體包括二個第一膠體，各該第一膠體具有覆蓋對應的該晶片的該短邊側表面的一內側部分，該二個晶片所對應的該些內側部分之間具有一間隔區，該緩衝件位於該間隔區中，其中該二個晶片之間的距離不大於10毫米。 A chip-on-film packaging structure includes: a flexible substrate with a chip bonding area; a plurality of pins arranged on the flexible substrate and extending outward from the chip bonding area; two chips , Arranged side by side in the chip bonding area of the flexible substrate and electrically connected to the pins, wherein each chip has an active surface, a back surface opposite to the active surface, and connected to the active surface And a plurality of side surfaces of the back surface, the side surfaces include a short side surface connected to a short side of the active surface, wherein the two chips are arranged side by side with the short side surface facing each other; a buffer Piece, arranged on the flexible substrate and located between the two chips; and an encapsulating glue filled at least between each chip and the flexible substrate and covering the sides of each chip Surface, and the buffer is coupled to the two chips through the packaging glue, wherein the packaging glue includes two first glues, each of the first glues has an inner portion covering the short side surface of the corresponding chip There is a space between the inner parts corresponding to the two wafers, the buffer is located in the space, and the distance between the two wafers is not more than 10 mm. 如申請專利範圍第1項所述的薄膜覆晶封裝結構，其中該封裝膠體更包括一第二膠體，各該晶片的該主動表面與該些側表面被對應的該第一膠體所覆蓋，且該第二膠體耦接該二個第一膠體與該緩衝件。 In the thin film on chip package structure described in claim 1, wherein the package glue further includes a second glue, the active surface and the side surfaces of each chip are covered by the corresponding first glue, and The second glue is coupled to the two first glues and the buffer. 如申請專利範圍第2項所述的薄膜覆晶封裝結構，其中該第二膠體包覆該二個第一膠體及該緩衝件的周圍，並填充於該間隔區內。 In the thin-film-on-chip package structure described in item 2 of the scope of patent application, the second glue covers the two first glues and the surroundings of the buffer member, and fills the spacer area. 如申請專利範圍第3項所述的薄膜覆晶封裝結構，其中該第二膠體更覆蓋該二個晶片的該些背表面與該緩衝件的頂面。 In the thin film chip-on-chip package structure described in claim 3, the second glue further covers the back surfaces of the two chips and the top surface of the buffer member. 如申請專利範圍第2項所述的薄膜覆晶封裝結構，其中各該晶片的該些側表面包括分別連接該主動表面的二個長邊的二個長邊側表面，各該第一膠體具有覆蓋該二個長邊側表面的二個外側部分，該緩衝件具有分別鄰近各該晶片的該二個長邊側表面的二個相對的第一側面，該第二膠體包覆該二個第一膠體的該些外側部分與該緩衝件的該些第一側面。 As for the thin-film-on-chip package structure described in claim 2, wherein the side surfaces of each of the chips include two long side side surfaces respectively connected to the two long sides of the active surface, and each first glue has Covering the two outer parts of the two long side surfaces, the buffer member has two opposite first side surfaces respectively adjacent to the two long side surfaces of each of the chips, and the second gel covers the two second side surfaces. The outer parts of a colloid and the first side surfaces of the buffer. 如申請專利範圍第2項所述的薄膜覆晶封裝結構，其中該緩衝件具有分別相鄰於該二個第一膠體的該些內側部分的二個相對的第二側面，該第二膠體填充於該間隔區內，且包覆該些內側部分與該些第二側面。 The thin film chip-on-chip package structure described in claim 2, wherein the buffer member has two opposite second side surfaces respectively adjacent to the inner portions of the two first colloids, and the second colloid is filled with In the compartment area, and cover the inner parts and the second side surfaces. 如申請專利範圍第1項所述的薄膜覆晶封裝結構，其中各該晶片的該短邊的長度不大於4毫米。 In the thin-film-on-chip package structure described in item 1 of the scope of patent application, the length of the short side of each chip is not greater than 4 mm. 如申請專利範圍第1項所述的薄膜覆晶封裝結構，其中該緩衝件為耐熱材料。 In the thin-film-on-chip package structure described in item 1 of the scope of patent application, the buffer is made of heat-resistant material.
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