TWI700786B - Chip-on-film package structure - Google Patents
Chip-on-film package structure Download PDFInfo
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
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Abstract
Description
本發明是有關於一種封裝結構,且特別是有關於一種薄膜覆晶封裝結構。The present invention relates to a packaging structure, and more particularly to a thin-film-on-chip packaging structure.
由於液晶顯示器具有低消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點,因而廣泛地應用在行動電話、筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。為配合液晶顯示裝置中超高數量的電性訊號傳輸,目前普遍採用捲帶自動接合(tape automatic bonding, TAB)技術進行驅動晶片的封裝,而薄膜覆晶(chip on film, COF)封裝結構便是其中一種應用捲帶自動接合技術的封裝結構。Because LCD displays have the advantages of low power consumption, thin and light weight, high resolution, high color saturation, and long life span, they are widely used in mobile phones, laptops or desktop computers, LCD screens and LCD TVs, etc. Electronic products closely related to life. In order to cooperate with the ultra-high number of electrical signal transmissions in liquid crystal display devices, tape automatic bonding (TAB) technology is generally used to drive the chip packaging, and the chip on film (COF) packaging structure is One of them is a packaging structure using tape and reel automatic bonding technology.
隨著科技不斷的進步,電子產品的功能需求也越來越多,晶片的體積電路密度因此必須不斷地提高,液晶顯示裝置的驅動晶片亦然。液晶顯示裝置的驅動晶片上的高I/O端點數使得I/O端點的配置集中於晶片主動面上的相對兩側,驅動晶片的外型因此設計成長寬差異頗大的細長型。為能容置更多的I/O端點,驅動晶片的長度也須增長。然而,增長晶片雖然可以增加端點數量,但長度過長的細長型晶片極容易斷裂且較難操作,因此,改以兩顆並排的晶片來取代一顆加長晶片。但兩顆並排的晶片之間未有阻隔物時,可撓性基板彎曲即可能導致兩顆並排的晶片互相碰撞擠壓。當填充封裝膠體於兩顆晶片之間作阻隔保護時,又因為兩顆晶片之間的位置缺乏支撐,填充於其中的封裝膠體固化時產生收縮而導致整個薄膜覆晶封裝結構產生於兩晶片之間向下而兩側向上的翹曲現象,同樣可能導致兩顆晶片互相碰撞擠壓,進而影響了電子產品的可靠度。With the continuous advancement of technology, there are more and more functional requirements for electronic products. Therefore, the volume circuit density of the chip must be continuously increased, as is the driving chip of the liquid crystal display device. The high number of I/O terminals on the driving chip of the liquid crystal display device makes the configuration of the I/O terminals concentrated on the opposite sides of the active surface of the chip, and the appearance of the driving chip is therefore designed to be a slender type with a large difference in growth and width. In order to accommodate more I/O endpoints, the length of the driver chip must also be increased. However, although an extended chip can increase the number of endpoints, an elongated chip with a long length is extremely easy to break and is difficult to handle. Therefore, two side-by-side chips are used instead of one extended chip. However, when there is no barrier between the two side-by-side chips, the bending of the flexible substrate may cause the two side-by-side chips to collide and squeeze each other. When the encapsulant is filled for barrier protection between the two chips, and because the position between the two chips lacks support, the encapsulant filled therein shrinks when it solidifies, resulting in the entire thin-film flip-chip packaging structure being generated between the two chips. The warping phenomenon of downwards and upwards on both sides may also cause the two chips to collide and squeeze each other, thereby affecting the reliability of electronic products.
本發明提供一種薄膜覆晶封裝結構,可避免產生翹曲導致並排兩晶片互相碰撞擠壓,且可具有較佳的可靠度。The present invention provides a film-on-chip packaging structure, which can avoid warping and cause two side-by-side chips to collide and squeeze each other, and has better reliability.
本發明的薄膜覆晶封裝結構包括可撓性基材、多個引腳、二個晶片、緩衝件及封裝膠體。可撓性基材具有晶片接合區。多個引腳設置於可撓性基材上,並自晶片接合區內向外延伸。二個晶片並列設置於可撓性基材的晶片接合區內,且分別電性連接這些引腳。各晶片具有主動表面、相對於主動表面的背表面以及連接主動表面與背表面的多個側表面。這些側表面包括連接主動表面的短邊的短邊側表面。二個晶片以短邊側表面互相面對而並排設置。緩衝件設置於可撓性基材上且位於二個晶片之間。封裝膠體至少填充於各晶片與可撓性基材之間且覆蓋各晶片的這些側表面。緩衝件透過封裝膠體與二個晶片耦接。The film-on-chip packaging structure of the present invention includes a flexible substrate, a plurality of pins, two chips, a buffer, and a packaging gel. The flexible substrate has a wafer bonding area. A plurality of pins are arranged on the flexible substrate and extend outward from the chip bonding area. The two chips are arranged side by side in the chip bonding area of the flexible substrate, and are electrically connected to these pins respectively. Each wafer has an active surface, a back surface opposite to the active surface, and a plurality of side surfaces connecting the active surface and the back surface. These side surfaces include short side side surfaces connecting the short sides of the active surface. The two wafers are arranged side by side with the short side surfaces facing each other. The buffer is arranged on the flexible substrate and located between the two chips. The encapsulant is filled at least between each chip and the flexible substrate and covers the side surfaces of each chip. The buffer is coupled to the two chips through the packaging glue.
基於上述,本發明的薄膜覆晶封裝結構,利用在二個並排設置的晶片的短邊側表面之間配置緩衝件,以在二個晶片之間的位置提供阻隔與支撐,再以封裝膠體填充於各晶片的短邊側表面與緩衝件之間的區域,以加強固定緩衝件與各晶片之間的相對位置並強化二個晶片之間的區域的硬度。緩衝件在二個晶片之間提供了阻隔與支撐,可避免薄膜覆晶封裝結構因封裝膠體固化收縮產生翹曲而造成二個晶片互相碰撞擠壓。此外,由於緩衝件的設置,減少了二個晶片之間所填充的封裝膠體的量,使得封裝膠體的收縮程度隨之降低。如此一來,可避免薄膜覆晶封裝結構產生翹曲而造成二個晶片互相碰撞擠壓,進而可提高薄膜覆晶封裝結構的可靠度。Based on the above, the thin-film-on-chip package structure of the present invention utilizes a buffer between the short side surfaces of two chips arranged side by side to provide barrier and support at the position between the two chips, and then is filled with packaging gel The area between the short side surface of each wafer and the buffer member is used to strengthen the relative position between the fixed buffer member and each wafer and to strengthen the hardness of the area between the two wafers. The buffer member provides barrier and support between the two chips, which can prevent the film-on-chip packaging structure from warping due to the curing shrinkage of the packaging colloid and causing the two chips to collide and squeeze each other. In addition, due to the arrangement of the buffer, the amount of packaging glue filled between the two chips is reduced, so that the shrinkage of the packaging glue is reduced accordingly. In this way, it is possible to prevent the two chips from colliding and squeezing due to warpage of the thin film on chip package structure, thereby improving the reliability of the thin film on chip package structure.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
圖1A是依照本發明一實施例的一種薄膜覆晶封裝結構的示意圖。圖1B是圖1A的薄膜覆晶封裝結構沿A-A’的剖面示意圖。請參照圖1A與圖1B,在本實施例中,薄膜覆晶封裝結構100包括可撓性基材110、多個引腳120、二個晶片130、緩衝件150及封裝膠體160。可撓性基材110的材質例如是聚醯亞胺(PI)、聚酯樹脂(PET)或其他可撓曲的絕緣材質,其中可撓性基材110具有晶片接合區112。這些引腳120設置於可撓性基材110上,並自晶片接合區112內向外延伸。接著,二個晶片130並列設置於可撓性基材110的晶片接合區112內,且透過凸塊138分別電性連接這些引腳120。在本實施例中,二個晶片130之間的距離D例如是不大於10毫米。FIG. 1A is a schematic diagram of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 1A along A-A'. 1A and 1B, in this embodiment, the film-on-
詳細來說,各晶片130具有主動表面132、相對於主動表面132的背表面134以及連接主動表面132與背表面134的多個側表面136。其中,各晶片130的主動表面132分別具有二個短邊1322以及二個長邊1324。在本實施例中,短邊1322的長度H例如是不大於4毫米。在本實施例中,這些側表面136包括分別連接主動表面132的二個短邊1322的二個短邊側表面1362,以及分別連接主動表面132的二個長邊1324的二個長邊側表面1364。二個晶片130以短邊側表面1362互相面對而並排設置。緩衝件150設置於可撓性基材110上且位於二個晶片130之間。封裝膠體160至少填充於各晶片130與可撓性基材110之間且覆蓋各晶片130的這些側表面136。換言之,封裝膠體160覆蓋各晶片130的主動表面132,且封裝膠體160更覆蓋各晶片130的二個短邊側表面1362以及二個長邊側表面1364。In detail, each
緩衝件150透過封裝膠體160與二個晶片130耦接。更進一步而言,在本實施例中,緩衝件150的配置方式如下所述。待二個晶片130分別設置於可撓性基材110的晶片接合區112內且電性連接引腳120之後,先將緩衝件150設置於可撓性基材110上,使緩衝件150位於二個晶片130之間,即位於二個晶片130的短邊側表面1362之間。此時,緩衝件150可例如是以黏貼或熱壓接合的方式固定於可撓性基材110上,但不以此為限。接著,再以封裝膠體160填充於各晶片130與可撓性基材110之間,以覆蓋二個晶片130的主動表面132、短邊側表面1362以及長邊側表面1364。其中,封裝膠體160更填充於各晶片130的短邊側表面1362與緩衝件150之間的區域,使緩衝件150與二個晶片130耦接,以固定緩衝件150、確保緩衝件150與二個晶片130之間的相對位置並加強此區域的硬度。在本實施例中,緩衝件150例如是包括耐熱材料,可耐受溫度例如是不低於150℃,舉例來說,例如是酚醛樹脂(電木)、聚醚醚酮(polyetheretherketone,PEEK)、鐵氟龍、聚醯亞胺(polyimide)、石墨烯或其他適合的耐熱材料。The
在本實施例中,薄膜覆晶封裝結構100還包括防焊層170。其中,防焊層170配置於可撓性基材110上,且局部覆蓋引腳120但暴露出晶片接合區112。In this embodiment, the film-on-
在本實施例中,可撓性基材110還具有相對的兩傳輸區116、117以及多個傳輸孔118,其中這些傳輸孔118分別位於傳輸區116與117內,且貫穿可撓性基材110。這些傳輸孔118沿著垂直於主動表面132的長邊1324的方向排列,且這些傳輸孔118的配置用以與傳輸機構配合而帶動可撓性基材110移動。實務上,在完成捲帶式薄膜覆晶封裝後,可撓性基材110中相對的兩傳輸區116、117會被移除,也就是說,最後製作所得到的薄膜覆晶封裝結構100並不具有傳輸區116、117,圖式中繪示出兩傳輸區116、117是用以說明薄膜覆晶封裝結構100係透過捲帶式薄膜覆晶封裝技術製作而得。In this embodiment, the
基於上述的設計,利用在二個並排設置的晶片130的短邊側表面1362之間配置緩衝件150,以在二個晶片130之間的位置提供阻隔與支撐,再以封裝膠體160填充於各晶片130的短邊側表面1362與緩衝件150之間的區域,以加強固定緩衝件150與各晶片130之間的相對位置並強化二個晶片130之間的區域的硬度。緩衝件150在二個晶片130之間提供了阻隔與支撐,可避免薄膜覆晶封裝結構100因封裝膠體160固化收縮產生翹曲而造成二個晶片130互相碰撞擠壓。此外,由於緩衝件150的設置,減少了二個晶片130之間所填充的封裝膠體160的量,封裝膠體160的收縮程度隨之降低,進而避免薄膜覆晶封裝結構100產生翹曲而造成二個晶片130互相碰撞擠壓。Based on the above design, a
以下將列舉其他實施例以作為說明。在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。Other embodiments will be listed below for description. It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
圖2A是依照本發明另一實施例的一種薄膜覆晶封裝結構的示意圖。圖2B是圖2A的薄膜覆晶封裝結構沿B-B’的剖面示意圖。請參照圖2A與圖2B,圖2A(圖2B)的薄膜覆晶封裝結構100a與圖1A(圖1B)的薄膜覆晶封裝結構100的主要差異在於:封裝膠體160更包括二個第一膠體162、163以及第二膠體164。其中,各晶片130的主動表面132與其側表面136被對應的第一膠體162、163所覆蓋,且第二膠體164耦接二個第一膠體162、163與緩衝件150。在本實施例中,第二膠體164可以包括散熱/導熱膠、紫外線硬化膠或其他適合的材質。2A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 2B is a schematic cross-sectional view along B-B' of the chip-on-film package structure of FIG. 2A. Please refer to FIGS. 2A and 2B. The main difference between the thin film on
詳細來說,請繼續參照圖2A與圖2B,各第一膠體162、163具有覆蓋對應的晶片130的短邊側表面1362的內側部分1622、1632。二個晶片130所對應的這些內側部分1622、1632之間具有間隔區114,且緩衝件150位於間隔區114中。此外,第二膠體164包覆二個第一膠體162、163及緩衝件150的周圍,並填充於間隔區114內。第二膠體164更覆蓋二個晶片130的這些背表面134與緩衝件150的頂面152。In detail, please continue to refer to FIGS. 2A and 2B, each of the
圖3A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖3B是圖3A的薄膜覆晶封裝結構沿C-C’的截面示意圖。請參照圖3A與圖3B,圖3A(圖3B)的薄膜覆晶封裝結構100b與圖2A(圖2B)的薄膜覆晶封裝結構100a的主要差異在於:第二膠體164未覆蓋二個晶片130的這些背表面134與緩衝件150的頂面152。FIG. 3A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 3B is a schematic cross-sectional view along C-C' of the chip-on-film package structure of FIG. 3A. Please refer to FIGS. 3A and 3B. The main difference between the thin film on
詳細來說,請繼續參照圖3A與圖3B,各晶片130的主動表面132、短邊側表面1362以及長邊側表面1364被對應的第一膠體162、163所覆蓋。此外,第二膠體164包覆二個第一膠體162、163及緩衝件150的周圍,並填充於間隔區114內。第二膠體164暴露出二個晶片130的背表面134與緩衝件150的頂面152。第二膠體164耦接二個第一膠體162、163與緩衝件150。在本實施例中,二個晶片130的這些背表面134不被第二膠體164所覆蓋而為裸露,晶片130於運作中所產生的熱可透過背表面134進行消散,因此可增加散熱效率。In detail, please continue to refer to FIGS. 3A and 3B. The
圖4A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖4B是圖4A的薄膜覆晶封裝結構沿D-D’的截面示意圖。請參照圖4A與圖4B,圖4A(圖4B)的薄膜覆晶封裝結構100c與圖3A(圖3B)的薄膜覆晶封裝結構100b的主要差異在於:緩衝件150具有分別相鄰於二個第一膠體162、163的內側部分1622、1632的二個相對的第二側面156。其中,第二膠體164並未填充於內側部分1622、1632與第二側面156之間。4A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 4B is a schematic cross-sectional view along D-D' of the chip-on-film package structure of FIG. 4A. Please refer to FIGS. 4A and 4B. The main difference between the chip-on-
詳細來說,在本實施例中,各第一膠體162、163具有覆蓋對應的晶片130的二個長邊側表面1364的二個外側部分1626、1636以及覆蓋鄰近晶片接合區112邊緣的短邊側表面1362的外側部分1628、1638,緩衝件150具有分別鄰近各晶片130的二個長邊側表面1364的二個相對的第一側面154。第二膠體164包覆二個第一膠體162、163的這些外側部分1626、1628、1636、1638與緩衝件150的這些第一側面154。換言之,在本實施例中,緩衝件150是透過第二膠體164連接第一側面154與第一膠體162、163的外側部分1626、1636而與二個晶片130耦接。In detail, in this embodiment, each of the
圖5A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖5B是圖5A的薄膜覆晶封裝結構沿E-E’的剖面示意圖。請參照圖5A與圖5B,圖5A(圖5B)的薄膜覆晶封裝結構100d與圖4A(圖4B)的薄膜覆晶封裝結構100c的主要差異在於:第二膠體164僅包覆二個第一膠體162、163的內側部分1622、1632與緩衝件150的第二側面156。5A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 5B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 5A along E-E'. Referring to FIGS. 5A and 5B, the main difference between the thin film on
詳細來說,第二膠體164覆蓋二個第一膠體162、163的內側部分1622、1632、緩衝件150的第一側面154、緩衝件150的第二側面156以及緩衝件150的頂面152。換言之,在本實施例中,緩衝件150是透過第二膠體164連接第二側面156與第一膠體162、163的內側部分1622、1632而與二個晶片130耦接。In detail, the
綜上所述,本發明的薄膜覆晶封裝結構,利用在二個並排設置的晶片的短邊側表面之間配置緩衝件,以在二個晶片之間的位置提供阻隔與支撐,再以封裝膠體填充於各晶片的短邊側表面與緩衝件之間的區域,以加強固定緩衝件與各晶片之間的相對位置並強化二個晶片之間的區域的硬度。緩衝件在二個晶片之間提供了阻隔與支撐,可避免薄膜覆晶封裝結構因封裝膠體固化收縮產生翹曲而造成二個晶片互相碰撞擠壓。此外,由於緩衝件的設置,減少了二個晶片之間所填充的封裝膠體的量,使得封裝膠體的收縮程度隨之降低。如此一來,可避免薄膜覆晶封裝結構產生翹曲而造成二個晶片互相碰撞擠壓,進而可提高薄膜覆晶封裝結構的可靠度。In summary, the thin-film-on-chip package structure of the present invention utilizes a buffer between the short side surfaces of two chips arranged side by side to provide barrier and support between the two chips, and then package The gel is filled in the area between the short side surface of each chip and the buffer to strengthen the relative position between the fixed buffer and each chip and to strengthen the hardness of the area between the two chips. The buffer member provides barrier and support between the two chips, which can prevent the film-on-chip packaging structure from warping due to the curing shrinkage of the packaging colloid and causing the two chips to collide and squeeze each other. In addition, due to the arrangement of the buffer, the amount of packaging glue filled between the two chips is reduced, so that the shrinkage of the packaging glue is reduced accordingly. In this way, it is possible to prevent the two chips from colliding and squeezing due to warpage of the thin film on chip package structure, thereby improving the reliability of the thin film on chip package structure.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
100、100a、100b、100c、100d‧‧‧薄膜覆晶封裝結構110‧‧‧可撓性基材112‧‧‧晶片接合區114‧‧‧間隔區120‧‧‧引腳130‧‧‧晶片132‧‧‧主動表面1322‧‧‧短邊1324‧‧‧長邊134‧‧‧背表面136‧‧‧側表面1362‧‧‧短邊側表面1364‧‧‧長邊側表面138‧‧‧凸塊150‧‧‧緩衝件152‧‧‧頂面154‧‧‧第一側面156‧‧‧第二側面160‧‧‧封裝膠體162‧‧‧第一膠體1622‧‧‧內側部分1626、1628‧‧‧外側部分163‧‧‧第一膠體1632‧‧‧內側部分1636、1638‧‧‧外側部分164‧‧‧第二膠體170‧‧‧防焊層D‧‧‧距離H‧‧‧長度100, 100a, 100b, 100c, 100d‧‧‧Thin film flip
圖1A是依照本發明一實施例的一種薄膜覆晶封裝結構的示意圖。 圖1B是圖1A的薄膜覆晶封裝結構沿A-A’的剖面示意圖。 圖2A是依照本發明另一實施例的一種薄膜覆晶封裝結構的示意圖。 圖2B是圖2A的薄膜覆晶封裝結構沿B-B’的剖面示意圖。 圖3A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖3B是圖3A的薄膜覆晶封裝結構沿C-C’的截面示意圖。 圖4A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖4B是圖4A的薄膜覆晶封裝結構沿D-D’的截面示意圖。 圖5A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖5B是圖5A的薄膜覆晶封裝結構沿E-E’的剖面示意圖。FIG. 1A is a schematic diagram of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 1A along A-A'. 2A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 2B is a schematic cross-sectional view along B-B' of the chip-on-film package structure of FIG. 2A. FIG. 3A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 3B is a schematic cross-sectional view along C-C' of the chip-on-film package structure of FIG. 3A. 4A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 4B is a schematic cross-sectional view along D-D' of the chip-on-film package structure of FIG. 4A. 5A is a schematic diagram of a chip-on-film package structure according to another embodiment of the invention. 5B is a schematic cross-sectional view of the chip-on-film package structure of FIG. 5A along E-E'.
100‧‧‧薄膜覆晶封裝結構 100‧‧‧Thin Film Flip Chip Package Structure
110‧‧‧可撓性基材 110‧‧‧Flexible substrate
120‧‧‧引腳 120‧‧‧pin
130‧‧‧晶片 130‧‧‧chip
132‧‧‧主動表面 132‧‧‧Active surface
134‧‧‧背表面 134‧‧‧Back surface
136‧‧‧側表面 136‧‧‧Side surface
1362‧‧‧短邊側表面 1362‧‧‧Short side surface
1364‧‧‧長邊側表面 1364‧‧‧Long side surface
138‧‧‧凸塊 138‧‧‧ bump
150‧‧‧緩衝件 150‧‧‧Buffer
160‧‧‧封裝膠體 160‧‧‧Packaging gel
170‧‧‧防焊層 170‧‧‧Solder Protection Layer
D‧‧‧距離 D‧‧‧Distance
Claims (8)
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WO2017135801A1 (en) * | 2016-02-05 | 2017-08-10 | 엘지이노텍 주식회사 | Light source unit and light unit having same |
WO2017217672A1 (en) * | 2016-06-13 | 2017-12-21 | 주식회사 세미콘라이트 | Semiconductor light emitting device and manufacturing method therefor |
WO2018008901A1 (en) * | 2016-07-07 | 2018-01-11 | 주식회사 세미콘라이트 | Semiconductor light emitting element and manufacturing method therefor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI724825B (en) * | 2020-03-19 | 2021-04-11 | 友達光電股份有限公司 | Flexible printed circuit film and display module |
Also Published As
Publication number | Publication date |
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TW201943031A (en) | 2019-11-01 |
CN110323184A (en) | 2019-10-11 |
CN110323184B (en) | 2021-05-18 |
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