TW201943031A - Chip-on-film package structure - Google Patents

Chip-on-film package structure Download PDF

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TW201943031A
TW201943031A TW107110823A TW107110823A TW201943031A TW 201943031 A TW201943031 A TW 201943031A TW 107110823 A TW107110823 A TW 107110823A TW 107110823 A TW107110823 A TW 107110823A TW 201943031 A TW201943031 A TW 201943031A
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wafers
thin
packaging structure
chip packaging
film flip
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TW107110823A
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TWI700786B (en
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陳崇龍
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南茂科技股份有限公司
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Priority to CN201810480052.1A priority patent/CN110323184B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant

Abstract

A chip-on-film package structure includes a flexible substrate, a plurality of leads, two chips, a buffer component, and an encapsulant. The leads are disposed on the flexible substrate and extend outwardly from a chip bonding area. The two chips are arranged side by side in the chip bonding area, and are respectively electrically connected with the leads. Each chip has an active surface, a back surface opposite to the active surface, and a plurality of side surfaces connecting the active surface and the back surface. These side surfaces include a short side surface connecting a short side of the active surface. The two chips are arranged side by side with their short side surfaces facing each other. The buffer component is disposed on the flexible substrate and between the two chips. The encapsulant at least fills in the space between each chip and the flexible substrate and covers the side surfaces of each chip. The buffer component is coupled to the two chips through the encapsulant.

Description

薄膜覆晶封裝結構Thin-film flip-chip packaging structure

本發明是有關於一種封裝結構,且特別是有關於一種薄膜覆晶封裝結構。The present invention relates to a packaging structure, and more particularly, to a thin-film flip-chip packaging structure.

由於液晶顯示器具有低消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點,因而廣泛地應用在行動電話、筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。為配合液晶顯示裝置中超高數量的電性訊號傳輸,目前普遍採用捲帶自動接合(tape automatic bonding, TAB)技術進行驅動晶片的封裝,而薄膜覆晶(chip on film, COF)封裝結構便是其中一種應用捲帶自動接合技術的封裝結構。Because liquid crystal displays have the advantages of low power consumption, light weight, high resolution, high color saturation, and long life, they are widely used in mobile phones, notebook computers or desktop computers, LCD screens, and LCD TVs. Electronics related to life. In order to cope with the ultra-high amount of electrical signal transmission in liquid crystal display devices, tape automatic bonding (TAB) technology is currently commonly used to drive chip packaging, and the chip on film (COF) packaging structure is One of them is a package structure using a tape and reel automatic bonding technology.

隨著科技不斷的進步,電子產品的功能需求也越來越多,晶片的體積電路密度因此必須不斷地提高,液晶顯示裝置的驅動晶片亦然。液晶顯示裝置的驅動晶片上的高I/O端點數使得I/O端點的配置集中於晶片主動面上的相對兩側,驅動晶片的外型因此設計成長寬差異頗大的細長型。為能容置更多的I/O端點,驅動晶片的長度也須增長。然而,增長晶片雖然可以增加端點數量,但長度過長的細長型晶片極容易斷裂且較難操作,因此,改以兩顆並排的晶片來取代一顆加長晶片。但兩顆並排的晶片之間未有阻隔物時,可撓性基板彎曲即可能導致兩顆並排的晶片互相碰撞擠壓。當填充封裝膠體於兩顆晶片之間作阻隔保護時,又因為兩顆晶片之間的位置缺乏支撐,填充於其中的封裝膠體固化時產生收縮而導致整個薄膜覆晶封裝結構產生於兩晶片之間向下而兩側向上的翹曲現象,同樣可能導致兩顆晶片互相碰撞擠壓,進而影響了電子產品的可靠度。With the continuous advancement of technology, the functional requirements of electronic products are also increasing, so the volume and circuit density of the chip must be continuously improved, as is the driving chip of the liquid crystal display device. The high number of I / O endpoints on the driver chip of the liquid crystal display device makes the configuration of the I / O endpoints concentrated on the opposite sides of the active surface of the chip. Therefore, the shape of the driver chip is designed to be a slender type with a large difference in width. To accommodate more I / O endpoints, the length of the driver chip must also be increased. However, although a growing wafer can increase the number of endpoints, an elongated wafer that is too long is very easy to break and difficult to handle. Therefore, two side-by-side wafers are used instead of one extension wafer. However, when there are no barriers between the two side-by-side wafers, bending of the flexible substrate may cause the two side-by-side wafers to collide and squeeze each other. When the filling and encapsulating gel is used as a barrier between two wafers, and because the position between the two wafers lacks support, the encapsulating colloid filled in it shrinks when curing, resulting in the entire thin-film flip-chip packaging structure being generated between the two wafers. The phenomenon of warping downwards and upwards on both sides may also cause the two chips to collide and squeeze each other, which in turn affects the reliability of electronic products.

本發明提供一種薄膜覆晶封裝結構,可避免產生翹曲導致並排兩晶片互相碰撞擠壓,且可具有較佳的可靠度。The invention provides a thin-film flip-chip packaging structure, which can avoid warping and cause two chips side by side to collide with each other and squeeze, and can have better reliability.

本發明的薄膜覆晶封裝結構包括可撓性基材、多個引腳、二個晶片、緩衝件及封裝膠體。可撓性基材具有晶片接合區。多個引腳設置於可撓性基材上,並自晶片接合區內向外延伸。二個晶片並列設置於可撓性基材的晶片接合區內,且分別電性連接這些引腳。各晶片具有主動表面、相對於主動表面的背表面以及連接主動表面與背表面的多個側表面。這些側表面包括連接主動表面的短邊的短邊側表面。二個晶片以短邊側表面互相面對而並排設置。緩衝件設置於可撓性基材上且位於二個晶片之間。封裝膠體至少填充於各晶片與可撓性基材之間且覆蓋各晶片的這些側表面。緩衝件透過封裝膠體與二個晶片耦接。The thin-film flip-chip packaging structure of the present invention includes a flexible substrate, a plurality of pins, two chips, a buffer, and a packaging gel. The flexible substrate has a wafer bonding area. A plurality of pins are disposed on the flexible substrate and extend outward from the wafer bonding area. The two chips are arranged side by side in a wafer bonding area of a flexible substrate, and these pins are electrically connected respectively. Each wafer has an active surface, a back surface opposite the active surface, and a plurality of side surfaces connecting the active surface and the back surface. These side surfaces include short side side surfaces that connect the short sides of the active surface. The two wafers are arranged side by side with the short side surfaces facing each other. The buffer is disposed on the flexible substrate and is located between the two wafers. The encapsulant is filled at least between each wafer and the flexible substrate and covers these side surfaces of each wafer. The buffer member is coupled to the two chips through the packaging gel.

基於上述,本發明的薄膜覆晶封裝結構,利用在二個並排設置的晶片的短邊側表面之間配置緩衝件,以在二個晶片之間的位置提供阻隔與支撐,再以封裝膠體填充於各晶片的短邊側表面與緩衝件之間的區域,以加強固定緩衝件與各晶片之間的相對位置並強化二個晶片之間的區域的硬度。緩衝件在二個晶片之間提供了阻隔與支撐,可避免薄膜覆晶封裝結構因封裝膠體固化收縮產生翹曲而造成二個晶片互相碰撞擠壓。此外,由於緩衝件的設置,減少了二個晶片之間所填充的封裝膠體的量,使得封裝膠體的收縮程度隨之降低。如此一來,可避免薄膜覆晶封裝結構產生翹曲而造成二個晶片互相碰撞擠壓,進而可提高薄膜覆晶封裝結構的可靠度。Based on the above, the thin-film flip-chip packaging structure of the present invention utilizes a buffer member disposed between the short side surfaces of two wafers arranged side by side, so as to provide a barrier and support at a position between the two wafers, and then filled with a packaging gel. The region between the short side surface of each wafer and the buffer member is used to strengthen the relative position between the buffer member and each wafer and to strengthen the hardness of the region between the two wafers. The buffer member provides a barrier and support between the two wafers, which can prevent the two wafers from colliding and squeezing due to the warpage of the thin-film flip-chip packaging structure due to the curing and shrinkage of the packaging colloid. In addition, due to the arrangement of the buffer, the amount of the encapsulating gel filled between the two wafers is reduced, so that the shrinkage of the encapsulating gel is reduced accordingly. In this way, warpage of the thin-film flip-chip packaging structure can be avoided, which can cause two wafers to collide and squeeze with each other, thereby improving the reliability of the thin-film flip-chip packaging structure.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

圖1A是依照本發明一實施例的一種薄膜覆晶封裝結構的示意圖。圖1B是圖1A的薄膜覆晶封裝結構沿A-A’的剖面示意圖。請參照圖1A與圖1B,在本實施例中,薄膜覆晶封裝結構100包括可撓性基材110、多個引腳120、二個晶片130、緩衝件150及封裝膠體160。可撓性基材110的材質例如是聚醯亞胺(PI)、聚酯樹脂(PET)或其他可撓曲的絕緣材質,其中可撓性基材110具有晶片接合區112。這些引腳120設置於可撓性基材110上,並自晶片接合區112內向外延伸。接著,二個晶片130並列設置於可撓性基材110的晶片接合區112內,且透過凸塊138分別電性連接這些引腳120。在本實施例中,二個晶片130之間的距離D例如是不大於10毫米。FIG. 1A is a schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 1A along A-A '. Please refer to FIGS. 1A and 1B. In this embodiment, the thin-film flip-chip packaging structure 100 includes a flexible substrate 110, a plurality of pins 120, two chips 130, a buffer 150, and a packaging gel 160. The material of the flexible substrate 110 is, for example, polyimide (PI), polyester resin (PET), or other flexible insulating materials. The flexible substrate 110 has a wafer bonding region 112. These pins 120 are disposed on the flexible substrate 110 and extend outward from the wafer bonding area 112. Next, the two wafers 130 are arranged side by side in the wafer bonding region 112 of the flexible substrate 110, and the pins 120 are electrically connected through the bumps 138 respectively. In this embodiment, the distance D between the two wafers 130 is, for example, not more than 10 mm.

詳細來說,各晶片130具有主動表面132、相對於主動表面132的背表面134以及連接主動表面132與背表面134的多個側表面136。其中,各晶片130的主動表面132分別具有二個短邊1322以及二個長邊1324。在本實施例中,短邊1322的長度H例如是不大於4毫米。在本實施例中,這些側表面136包括分別連接主動表面132的二個短邊1322的二個短邊側表面1362,以及分別連接主動表面132的二個長邊1324的二個長邊側表面1364。二個晶片130以短邊側表面1362互相面對而並排設置。緩衝件150設置於可撓性基材110上且位於二個晶片130之間。封裝膠體160至少填充於各晶片130與可撓性基材110之間且覆蓋各晶片130的這些側表面136。換言之,封裝膠體160覆蓋各晶片130的主動表面132,且封裝膠體160更覆蓋各晶片130的二個短邊側表面1362以及二個長邊側表面1364。In detail, each wafer 130 has an active surface 132, a back surface 134 opposite to the active surface 132, and a plurality of side surfaces 136 connecting the active surface 132 and the back surface 134. The active surface 132 of each wafer 130 has two short sides 1322 and two long sides 1324, respectively. In this embodiment, the length H of the short side 1322 is, for example, not more than 4 mm. In this embodiment, these side surfaces 136 include two short side surface 1362 which respectively connect the two short sides 1322 of the active surface 132, and two long side side surfaces which respectively connect the two long sides 1324 of the active surface 132. 1364. The two wafers 130 are arranged side by side with the short side surfaces 1362 facing each other. The buffer member 150 is disposed on the flexible substrate 110 and is located between the two wafers 130. The encapsulant 160 is filled at least between the wafers 130 and the flexible substrate 110 and covers the side surfaces 136 of the wafers 130. In other words, the encapsulant 160 covers the active surface 132 of each chip 130, and the encapsulant 160 covers two short side surfaces 1362 and two long side surfaces 1364 of each chip 130.

緩衝件150透過封裝膠體160與二個晶片130耦接。更進一步而言,在本實施例中,緩衝件150的配置方式如下所述。待二個晶片130分別設置於可撓性基材110的晶片接合區112內且電性連接引腳120之後,先將緩衝件150設置於可撓性基材110上,使緩衝件150位於二個晶片130之間,即位於二個晶片130的短邊側表面1362之間。此時,緩衝件150可例如是以黏貼或熱壓接合的方式固定於可撓性基材110上,但不以此為限。接著,再以封裝膠體160填充於各晶片130與可撓性基材110之間,以覆蓋二個晶片130的主動表面132、短邊側表面1362以及長邊側表面1364。其中,封裝膠體160更填充於各晶片130的短邊側表面1362與緩衝件150之間的區域,使緩衝件150與二個晶片130耦接,以固定緩衝件150、確保緩衝件150與二個晶片130之間的相對位置並加強此區域的硬度。在本實施例中,緩衝件150例如是包括耐熱材料,可耐受溫度例如是不低於150℃,舉例來說,例如是酚醛樹脂(電木)、聚醚醚酮(polyetheretherketone,PEEK)、鐵氟龍、聚醯亞胺(polyimide)、石墨烯或其他適合的耐熱材料。The buffer member 150 is coupled to the two chips 130 through the packaging gel 160. Furthermore, in this embodiment, the arrangement of the buffer 150 is as follows. After the two wafers 130 are respectively disposed in the wafer bonding area 112 of the flexible substrate 110 and the lead pins 120 are electrically connected, the buffer member 150 is first disposed on the flexible substrate 110 so that the buffer member 150 is located on the second substrate 130. The two wafers 130 are located between the short side surfaces 1362 of the two wafers 130. At this time, the buffer member 150 may be fixed on the flexible base material 110 by, for example, adhesive or thermocompression bonding, but is not limited thereto. Next, the encapsulant 160 is filled between each chip 130 and the flexible substrate 110 to cover the active surface 132, the short side surface 1362 and the long side surface 1364 of the two chips 130. The encapsulant 160 fills the area between the short side surface 1362 of each chip 130 and the buffer member 150, so that the buffer member 150 is coupled to the two wafers 130 to fix the buffer member 150 and ensure that the buffer member 150 and two The relative position between the wafers 130 and strengthens the hardness of this area. In this embodiment, the buffer member 150 includes, for example, a heat-resistant material, and can withstand a temperature of not less than 150 ° C., for example, phenol resin (bakelite), polyetheretherketone (PEEK), Teflon, polyimide, graphene or other suitable heat-resistant materials.

在本實施例中,薄膜覆晶封裝結構100還包括防焊層170。其中,防焊層170配置於可撓性基材110上,且局部覆蓋引腳120但暴露出晶片接合區112。In this embodiment, the thin-film flip-chip packaging structure 100 further includes a solder resist layer 170. The solder mask 170 is disposed on the flexible substrate 110 and partially covers the leads 120 but exposes the wafer bonding area 112.

在本實施例中,可撓性基材110還具有相對的兩傳輸區116、117以及多個傳輸孔118,其中這些傳輸孔118分別位於傳輸區116與117內,且貫穿可撓性基材110。這些傳輸孔118沿著垂直於主動表面132的長邊1324的方向排列,且這些傳輸孔118的配置用以與傳輸機構配合而帶動可撓性基材110移動。實務上,在完成捲帶式薄膜覆晶封裝後,可撓性基材110中相對的兩傳輸區116、117會被移除,也就是說,最後製作所得到的薄膜覆晶封裝結構100並不具有傳輸區116、117,圖式中繪示出兩傳輸區116、117是用以說明薄膜覆晶封裝結構100係透過捲帶式薄膜覆晶封裝技術製作而得。In this embodiment, the flexible substrate 110 also has two transmission regions 116 and 117 and a plurality of transmission holes 118 opposite to each other. The transmission holes 118 are respectively located in the transmission regions 116 and 117 and penetrate the flexible substrate. 110. The transmission holes 118 are arranged along a direction perpendicular to the long side 1324 of the active surface 132, and the transmission holes 118 are configured to cooperate with the transmission mechanism to drive the flexible substrate 110 to move. In practice, after the tape-and-reel film-on-chip packaging is completed, the two opposite transmission regions 116 and 117 in the flexible substrate 110 are removed, that is, the film-on-chip packaging structure 100 obtained at the end is not The transmission region 116 and 117 are provided. The two transmission regions 116 and 117 are illustrated in the drawing to explain that the thin film flip chip packaging structure 100 is made by a tape and reel thin film flip chip packaging technology.

基於上述的設計,利用在二個並排設置的晶片130的短邊側表面1362之間配置緩衝件150,以在二個晶片130之間的位置提供阻隔與支撐,再以封裝膠體160填充於各晶片130的短邊側表面1362與緩衝件150之間的區域,以加強固定緩衝件150與各晶片130之間的相對位置並強化二個晶片130之間的區域的硬度。緩衝件150在二個晶片130之間提供了阻隔與支撐,可避免薄膜覆晶封裝結構100因封裝膠體160固化收縮產生翹曲而造成二個晶片130互相碰撞擠壓。此外,由於緩衝件150的設置,減少了二個晶片130之間所填充的封裝膠體160的量,封裝膠體160的收縮程度隨之降低,進而避免薄膜覆晶封裝結構100產生翹曲而造成二個晶片130互相碰撞擠壓。Based on the above design, the buffer 150 is arranged between the short side surfaces 1362 of the two side-by-side wafers 130 to provide the barrier and support at the position between the two wafers 130. The region between the short side surface 1362 of the wafer 130 and the buffer 150 strengthens the relative position between the buffer 150 and each wafer 130 and strengthens the hardness of the region between the two wafers 130. The buffer member 150 provides a barrier and support between the two wafers 130, which can prevent the thin-film flip-chip packaging structure 100 from warping due to the curing shrinkage of the encapsulant 160 and causing the two wafers 130 to collide with each other. In addition, due to the provision of the buffer 150, the amount of the encapsulating gel 160 filled between the two wafers 130 is reduced, and the degree of shrinkage of the encapsulating gel 160 is reduced accordingly, thereby avoiding warping of the thin-film flip-chip packaging structure 100 and causing The wafers 130 collide with each other and are squeezed.

以下將列舉其他實施例以作為說明。在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。Other embodiments will be listed below for illustration. It must be noted here that the following embodiments use the component numbers and parts of the foregoing embodiments, in which the same reference numerals are used to indicate the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

圖2A是依照本發明另一實施例的一種薄膜覆晶封裝結構的示意圖。圖2B是圖2A的薄膜覆晶封裝結構沿B-B’的剖面示意圖。請參照圖2A與圖2B,圖2A(圖2B)的薄膜覆晶封裝結構100a與圖1A(圖1B)的薄膜覆晶封裝結構100的主要差異在於:封裝膠體160更包括二個第一膠體162、163以及第二膠體164。其中,各晶片130的主動表面132與其側表面136被對應的第一膠體162、163所覆蓋,且第二膠體164耦接二個第一膠體162、163與緩衝件150。在本實施例中,第二膠體164可以包括散熱/導熱膠、紫外線硬化膠或其他適合的材質。FIG. 2A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 2A along B-B '. Please refer to FIGS. 2A and 2B. The main difference between the thin-film flip-chip packaging structure 100a of FIG. 2A (FIG. 2B) and the thin-film flip-chip packaging structure 100 of FIG. 1A (FIG. 1B) is that the packaging colloid 160 further includes two first colloids. 162, 163 and the second colloid 164. The active surface 132 and the side surface 136 of each wafer 130 are covered by corresponding first colloids 162 and 163, and the second colloid 164 is coupled to the two first colloids 162 and 163 and the buffer 150. In this embodiment, the second gel 164 may include a heat-dissipating / thermal-conductive glue, a UV-curing glue, or other suitable materials.

詳細來說,請繼續參照圖2A與圖2B,各第一膠體162、163具有覆蓋對應的晶片130的短邊側表面1362的內側部分1622、1632。二個晶片130所對應的這些內側部分1622、1632之間具有間隔區114,且緩衝件150位於間隔區114中。此外,第二膠體164包覆二個第一膠體162、163及緩衝件150的周圍,並填充於間隔區114內。第二膠體164更覆蓋二個晶片130的這些背表面134與緩衝件150的頂面152。In detail, please continue to refer to FIGS. 2A and 2B. Each of the first colloids 162 and 163 has an inner portion 1622 and 1632 covering the short side surface 1362 of the corresponding wafer 130. A space 114 is provided between the inner portions 1622 and 1632 corresponding to the two wafers 130, and the buffer 150 is located in the space 114. In addition, the second colloid 164 covers the periphery of the two first colloids 162 and 163 and the buffer 150 and fills the space 114. The second colloid 164 further covers the back surfaces 134 of the two wafers 130 and the top surface 152 of the buffer member 150.

圖3A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖3B是圖3A的薄膜覆晶封裝結構沿C-C’的截面示意圖。請參照圖3A與圖3B,圖3A(圖3B)的薄膜覆晶封裝結構100b與圖2A(圖2B)的薄膜覆晶封裝結構100a的主要差異在於:第二膠體164未覆蓋二個晶片130的這些背表面134與緩衝件150的頂面152。FIG. 3A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. 3B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 3A along C-C '. Please refer to FIGS. 3A and 3B. The main difference between the thin-film flip-chip packaging structure 100 b of FIG. 3A (FIG. 3B) and the thin-film flip-chip packaging structure 100 a of FIG. 2A (FIG. 2B) is that the second gel 164 does not cover the two chips 130 These back surfaces 134 and the top surface 152 of the buffer member 150.

詳細來說,請繼續參照圖3A與圖3B,各晶片130的主動表面132、短邊側表面1362以及長邊側表面1364被對應的第一膠體162、163所覆蓋。此外,第二膠體164包覆二個第一膠體162、163及緩衝件150的周圍,並填充於間隔區114內。第二膠體164暴露出二個晶片130的背表面134與緩衝件150的頂面152。第二膠體164耦接二個第一膠體162、163與緩衝件150。在本實施例中,二個晶片130的這些背表面134不被第二膠體164所覆蓋而為裸露,晶片130於運作中所產生的熱可透過背表面134進行消散,因此可增加散熱效率。In detail, please continue to refer to FIGS. 3A and 3B. The active surface 132, the short side surface 1362 and the long side surface 1364 of each chip 130 are covered by the corresponding first colloids 162 and 163. In addition, the second colloid 164 covers the periphery of the two first colloids 162 and 163 and the buffer 150 and fills the space 114. The second gel 164 exposes the back surface 134 of the two wafers 130 and the top surface 152 of the buffer member 150. The second colloid 164 is coupled to the two first colloids 162 and 163 and the buffer member 150. In this embodiment, the back surfaces 134 of the two wafers 130 are not covered by the second colloid 164 and are exposed. The heat generated by the chip 130 during operation can be dissipated through the back surface 134, so the heat dissipation efficiency can be increased.

圖4A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖4B是圖4A的薄膜覆晶封裝結構沿D-D’的截面示意圖。請參照圖4A與圖4B,圖4A(圖4B)的薄膜覆晶封裝結構100c與圖3A(圖3B)的薄膜覆晶封裝結構100b的主要差異在於:緩衝件150具有分別相鄰於二個第一膠體162、163的內側部分1622、1632的二個相對的第二側面156。其中,第二膠體164並未填充於內側部分1622、1632與第二側面156之間。FIG. 4A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. 4B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 4A along D-D '. Please refer to FIG. 4A and FIG. 4B. The main difference between the thin-film flip-chip packaging structure 100c of FIG. 4A (FIG. 4B) and the thin-film flip-chip packaging structure 100b of FIG. 3A (FIG. 3B) is that the buffer 150 has two adjacent two Two opposite second side surfaces 156 of the inner portions 1622 and 1632 of the first colloids 162 and 163. The second colloid 164 is not filled between the inner portions 1622 and 1632 and the second side surface 156.

詳細來說,在本實施例中,各第一膠體162、163具有覆蓋對應的晶片130的二個長邊側表面1364的二個外側部分1626、1636以及覆蓋鄰近晶片接合區112邊緣的短邊側表面1362的外側部分1628、1638,緩衝件150具有分別鄰近各晶片130的二個長邊側表面1364的二個相對的第一側面154。第二膠體164包覆二個第一膠體162、163的這些外側部分1626、1628、1636、1638與緩衝件150的這些第一側面154。換言之,在本實施例中,緩衝件150是透過第二膠體164連接第一側面154與第一膠體162、163的外側部分1626、1636而與二個晶片130耦接。In detail, in this embodiment, each of the first colloids 162 and 163 has two outer portions 1626 and 1636 covering two long side surfaces 1364 of the corresponding wafer 130 and a short side covering an edge of the adjacent wafer bonding region 112. On the outer portions 1628 and 1638 of the side surface 1362, the buffer member 150 has two opposite first side surfaces 154 adjacent to the two long side surface 1364 of each wafer 130, respectively. The second colloid 164 covers the outer portions 1626, 1628, 1636, 1638 of the two first colloids 162, 163 and the first side surfaces 154 of the buffer member 150. In other words, in this embodiment, the buffer member 150 is coupled to the two chips 130 by connecting the first side surface 154 and the outer portions 1626 and 1636 of the first gels 162 and 163 through the second gel 164.

圖5A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。圖5B是圖5A的薄膜覆晶封裝結構沿E-E’的剖面示意圖。請參照圖5A與圖5B,圖5A(圖5B)的薄膜覆晶封裝結構100d與圖4A(圖4B)的薄膜覆晶封裝結構100c的主要差異在於:第二膠體164僅包覆二個第一膠體162、163的內側部分1622、1632與緩衝件150的第二側面156。FIG. 5A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. 5B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 5A along the line E-E '. Please refer to FIG. 5A and FIG. 5B. The main difference between the thin-film flip-chip packaging structure 100 d of FIG. 5A (FIG. 5B) and the thin-film flip-chip packaging structure 100 c of FIG. The inner portions 1622 and 1632 of the colloids 162 and 163 and the second side surface 156 of the buffer member 150.

詳細來說,第二膠體164覆蓋二個第一膠體162、163的內側部分1622、1632、緩衝件150的第一側面154、緩衝件150的第二側面156以及緩衝件150的頂面152。換言之,在本實施例中,緩衝件150是透過第二膠體164連接第二側面156與第一膠體162、163的內側部分1622、1632而與二個晶片130耦接。In detail, the second colloid 164 covers the inner portions 1622, 1632 of the two first colloids 162, 163, the first side surface 154 of the buffer member 150, the second side surface 156 of the buffer member 150, and the top surface 152 of the buffer member 150. In other words, in the present embodiment, the buffer member 150 is coupled to the two wafers 130 by connecting the second side surface 156 and the inner portions 1622 and 1632 of the first gels 162 and 163 through the second gel 164.

綜上所述,本發明的薄膜覆晶封裝結構,利用在二個並排設置的晶片的短邊側表面之間配置緩衝件,以在二個晶片之間的位置提供阻隔與支撐,再以封裝膠體填充於各晶片的短邊側表面與緩衝件之間的區域,以加強固定緩衝件與各晶片之間的相對位置並強化二個晶片之間的區域的硬度。緩衝件在二個晶片之間提供了阻隔與支撐,可避免薄膜覆晶封裝結構因封裝膠體固化收縮產生翹曲而造成二個晶片互相碰撞擠壓。此外,由於緩衝件的設置,減少了二個晶片之間所填充的封裝膠體的量,使得封裝膠體的收縮程度隨之降低。如此一來,可避免薄膜覆晶封裝結構產生翹曲而造成二個晶片互相碰撞擠壓,進而可提高薄膜覆晶封裝結構的可靠度。In summary, in the thin-film flip-chip packaging structure of the present invention, a buffer is arranged between the short side surfaces of two wafers arranged side by side to provide blocking and support at the position between the two wafers, and then the package is packaged. The colloid is filled in the region between the short side surface of each wafer and the buffer member to strengthen the relative position between the buffer member and each wafer and to strengthen the hardness of the region between the two wafers. The buffer member provides a barrier and support between the two wafers, which can prevent the two wafers from colliding and squeezing due to the warpage of the thin-film flip-chip packaging structure due to the curing and shrinkage of the packaging colloid. In addition, due to the arrangement of the buffer, the amount of the encapsulating gel filled between the two wafers is reduced, so that the shrinkage of the encapsulating gel is reduced accordingly. In this way, warpage of the thin-film flip-chip packaging structure can be avoided, which can cause two wafers to collide and squeeze with each other, thereby improving the reliability of the thin-film flip-chip packaging structure.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100、100a、100b、100c、100d‧‧‧薄膜覆晶封裝結構100, 100a, 100b, 100c, 100d

110‧‧‧可撓性基材110‧‧‧ flexible substrate

112‧‧‧晶片接合區112‧‧‧ Wafer Land

114‧‧‧間隔區114‧‧‧ spacer

120‧‧‧引腳120‧‧‧pin

130‧‧‧晶片130‧‧‧Chip

132‧‧‧主動表面132‧‧‧active surface

1322‧‧‧短邊1322‧‧‧Short side

1324‧‧‧長邊1324‧‧‧long side

134‧‧‧背表面134‧‧‧back surface

136‧‧‧側表面136‧‧‧side surface

1362‧‧‧短邊側表面1362‧‧‧Side side surface

1364‧‧‧長邊側表面1364‧‧‧Long side surface

138‧‧‧凸塊138‧‧‧ bump

150‧‧‧緩衝件150‧‧‧ buffer

152‧‧‧頂面152‧‧‧Top

154‧‧‧第一側面154‧‧‧first side

156‧‧‧第二側面156‧‧‧second side

160‧‧‧封裝膠體160‧‧‧ encapsulated colloid

162‧‧‧第一膠體162‧‧‧The first colloid

1622‧‧‧內側部分1622‧‧‧Inner part

1626、1628‧‧‧外側部分1626, 1628‧‧‧ Outer part

163‧‧‧第一膠體163‧‧‧The first colloid

1632‧‧‧內側部分1632‧‧‧Inner part

1636、1638‧‧‧外側部分1636, 1638‧‧‧outside

164‧‧‧第二膠體164‧‧‧Second Colloid

170‧‧‧防焊層170‧‧‧solder mask

D‧‧‧距離D‧‧‧distance

H‧‧‧長度H‧‧‧ length

圖1A是依照本發明一實施例的一種薄膜覆晶封裝結構的示意圖。 圖1B是圖1A的薄膜覆晶封裝結構沿A-A’的剖面示意圖。 圖2A是依照本發明另一實施例的一種薄膜覆晶封裝結構的示意圖。 圖2B是圖2A的薄膜覆晶封裝結構沿B-B’的剖面示意圖。 圖3A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖3B是圖3A的薄膜覆晶封裝結構沿C-C’的截面示意圖。 圖4A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖4B是圖4A的薄膜覆晶封裝結構沿D-D’的截面示意圖。 圖5A是依照本發明又一實施例的一種薄膜覆晶封裝結構的示意圖。 圖5B是圖5A的薄膜覆晶封裝結構沿E-E’的剖面示意圖。FIG. 1A is a schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 1A along A-A '. FIG. 2A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 2A along B-B '. FIG. 3A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. 3B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 3A along C-C '. FIG. 4A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. 4B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 4A along D-D '. FIG. 5A is a schematic diagram of a thin-film flip-chip packaging structure according to another embodiment of the present invention. 5B is a schematic cross-sectional view of the thin-film flip-chip packaging structure of FIG. 5A along the line E-E '.

Claims (10)

一種薄膜覆晶封裝結構,包括: 一可撓性基材,具有一晶片接合區; 多個引腳,設置於該可撓性基材上,並自該晶片接合區內向外延伸; 二個晶片,並列設置於該可撓性基材的該晶片接合區內,且分別電性連接該些引腳,其中各該晶片具有一主動表面、相對於該主動表面的一背表面以及連接該主動表面與該背表面的多個側表面,該些側表面包括連接該主動表面的一短邊的一短邊側表面,其中該二個晶片以該短邊側表面互相面對而並排設置; 一緩衝件,設置於該可撓性基材上,且位於該二個晶片之間;以及 一封裝膠體,至少填充於各該晶片與該可撓性基材之間且覆蓋各該晶片的該些側表面,且該緩衝件透過該封裝膠體與該二個晶片耦接。A thin-film flip-chip packaging structure includes: a flexible substrate having a wafer bonding area; a plurality of pins disposed on the flexible substrate and extending outward from the wafer bonding area; two wafers And are arranged side by side in the wafer bonding area of the flexible substrate and are electrically connected to the pins, respectively, wherein each of the wafers has an active surface, a back surface opposite to the active surface, and the active surface is connected to the chip. And a plurality of side surfaces of the back surface, the side surfaces including a short side surface connected to a short side of the active surface, wherein the two chips are arranged side by side with the short side surface facing each other; a buffer Components are disposed on the flexible substrate and are located between the two wafers; and an encapsulant is filled at least between each of the wafers and the flexible substrate and covers the sides of each of the wafers Surface, and the buffer member is coupled to the two chips through the packaging gel. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該封裝膠體包括二個第一膠體及一第二膠體,各該晶片的該主動表面與該些側表面被對應的該第一膠體所覆蓋,且該第二膠體耦接該二個第一膠體與該緩衝件。The thin-film flip-chip packaging structure according to item 1 of the scope of the patent application, wherein the packaging colloid includes two first colloids and a second colloid, and the active surface of each wafer and the first surfaces corresponding to the side surfaces are corresponding. The colloid is covered, and the second colloid is coupled to the two first colloids and the buffer member. 如申請專利範圍第2項所述的薄膜覆晶封裝結構,其中各該第一膠體具有覆蓋對應的該晶片的該短邊側表面的一內側部分,該二個晶片所對應的該些內側部分之間具有一間隔區,該緩衝件位於該間隔區中。The thin-film flip-chip packaging structure according to item 2 of the scope of patent application, wherein each of the first colloids has an inner portion covering the corresponding short side surface of the wafer, and the inner portions corresponding to the two wafers. There is a gap between them, and the buffer is located in the gap. 如申請專利範圍第3項所述的薄膜覆晶封裝結構,其中該第二膠體包覆該二個第一膠體及該緩衝件的周圍,並填充於該間隔區內。According to the thin-film flip-chip packaging structure described in item 3 of the patent application scope, wherein the second colloid covers the two first colloids and the periphery of the buffer member, and fills the gap region. 如申請專利範圍第4項所述的薄膜覆晶封裝結構,其中該第二膠體更覆蓋該二個晶片的該些背表面與該緩衝件的頂面。According to the thin-film flip-chip packaging structure described in item 4 of the patent application scope, wherein the second colloid further covers the back surfaces of the two wafers and the top surface of the buffer member. 如申請專利範圍第3項所述的薄膜覆晶封裝結構,其中各該晶片的該些側表面包括分別連接該主動表面的二個長邊的二個長邊側表面,各該第一膠體具有覆蓋該二個長邊側表面的二個外側部分,該緩衝件具有分別鄰近各該晶片的該二個長邊側表面的二個相對的第一側面,該第二膠體包覆該二個第一膠體的該些外側部分與該緩衝件的該些第一側面。The thin-film flip-chip packaging structure according to item 3 of the scope of patent application, wherein the side surfaces of each of the wafers include two long-side side surfaces that are respectively connected to two long sides of the active surface, and each of the first colloids has Two outer side portions covering the two long side side surfaces, the buffer member having two opposite first side surfaces adjacent to the two long side side surfaces of each of the wafers respectively, and the second colloid covering the two second side surfaces The outer portions of a colloid and the first sides of the buffer member. 如申請專利範圍第3項所述的薄膜覆晶封裝結構,其中該緩衝件具有分別相鄰於該二個第一膠體的該些內側部分的二個相對的第二側面,該第二膠體填充於該間隔區內,且包覆該些內側部分與該些第二側面。The thin-film flip-chip packaging structure according to item 3 of the patent application scope, wherein the buffer member has two opposite second sides respectively adjacent to the inner portions of the two first colloids, and the second colloid is filled Within the gap area, the inner portions and the second side surfaces are covered. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中各該晶片的該短邊的長度不大於4毫米。According to the thin-film flip-chip packaging structure described in item 1 of the scope of patent application, wherein the length of the short side of each of the wafers is not greater than 4 mm. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該二個晶片之間的距離不大於10毫米。The thin-film flip-chip packaging structure according to item 1 of the scope of patent application, wherein the distance between the two wafers is not greater than 10 mm. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該緩衝件為耐熱材料。The thin-film flip-chip packaging structure according to item 1 of the patent application scope, wherein the buffer member is a heat-resistant material.
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