TWI697079B - Chip on film package structure - Google Patents

Chip on film package structure Download PDF

Info

Publication number
TWI697079B
TWI697079B TW108107506A TW108107506A TWI697079B TW I697079 B TWI697079 B TW I697079B TW 108107506 A TW108107506 A TW 108107506A TW 108107506 A TW108107506 A TW 108107506A TW I697079 B TWI697079 B TW I697079B
Authority
TW
Taiwan
Prior art keywords
chip
flexible substrate
heat dissipation
wafer
encapsulant
Prior art date
Application number
TW108107506A
Other languages
Chinese (zh)
Other versions
TW202034467A (en
Inventor
陳崇龍
Original Assignee
南茂科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW108107506A priority Critical patent/TWI697079B/en
Priority to CN201910374014.2A priority patent/CN111668172B/en
Application granted granted Critical
Publication of TWI697079B publication Critical patent/TWI697079B/en
Publication of TW202034467A publication Critical patent/TW202034467A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

A chip on film package structure including a flexible substrate, a circuit layer, a chip, an encapsulant, and a heat dissipating tape is provided. The circuit layer and the chip are disposed on the flexible substrate. The chip is electrically connected to the circuit layer. The circuit layer is located between the flexible substrate and the chip. The chip has a first side surface and a second side surface opposite to each other. The encapsulant is at least filled between the flexible substrate and the chip. The encapsulant includes a first portion covering the first side surface of the chip and a second portion covering the second side surface of the chip. The heat dissipating tape is located on the flexible substrate and covers the chip and the encapsulant. The heat dissipating tape has at least two openings, and the two openings are respectively located on opposite sides of the chip. One of the two openings partially exposes the first portion of the encapsulant and another one of the two openings partially exposes the second portion of the encapsulant.

Description

薄膜覆晶封裝結構Thin film flip chip packaging structure

本發明是有關於一種封裝結構，且特別是有關於一種薄膜覆晶封裝結構。The invention relates to a packaging structure, and in particular to a thin film flip chip packaging structure.

現行的薄膜覆晶封裝(Chip on Film, COF)為增進散熱效果，會貼附散熱貼片於封裝結構的表面上，特別是具有晶片的表面上。一般而言，散熱貼片是以滾壓的方式貼附於晶片封裝結構上，由於晶片具有一定的高度，且覆蓋晶片四周的底部填充材(即封裝膠體)呈不規則坡形，以滾壓方式貼附散熱貼片於晶片上時，可能因散熱貼片未順應晶片與封裝膠體緊密貼合而有拱起及空隙的情況產生。此外，由於散熱貼片會完全覆蓋住晶片與封裝膠體，因此在貼附後無法有效確認散熱貼片與晶片和封裝膠體之間是否緊密貼合，進而可能因散熱貼片拱起及形成空隙而導致散熱效率不佳的問題。因此，如何使薄膜覆晶封裝結構具有良好的散熱效率，將成為重要的一門課題。In order to improve the heat dissipation effect, the current chip on film (COF) package will attach a heat dissipation patch to the surface of the package structure, especially the surface with a chip. Generally speaking, the heat dissipation patch is attached to the chip packaging structure by rolling. Since the chip has a certain height, and the underfill material (ie, the packaging colloid) covering the periphery of the chip is irregularly sloped, it is rolled When the heat dissipation patch is attached to the chip in a manner, it may occur that the heat dissipation patch does not conform to the tight fit of the chip and the packaging gel, and there may be arching and voids. In addition, since the heat dissipation patch completely covers the chip and the encapsulant, it is not possible to effectively confirm whether the heat dissipation patch is tightly attached to the chip and the encapsulation colloid after attaching, which may cause the heat dissipation patch to arch and form voids. The problem of poor heat dissipation efficiency. Therefore, how to make the thin film flip chip packaging structure have good heat dissipation efficiency will become an important topic.

本發明提供一種薄膜覆晶封裝結構，其具有良好的散熱效率。The invention provides a thin film flip chip packaging structure, which has good heat dissipation efficiency.

本發明提供一種薄膜覆晶封裝結構包括可撓性基材、線路層、晶片、封裝膠體以及散熱貼片。線路層與晶片位於可撓性基材上。晶片電性連接線路層。線路層位於可撓性基材與晶片之間。晶片具有彼此相對的第一側面與第二側面。封裝膠體至少填充於可撓性基材與晶片之間。封裝膠體包括覆蓋晶片的第一側面的第一部分與覆蓋晶片的第二側面的第二部分。散熱貼片位於可撓性基材上，且覆蓋晶片以及封裝膠體。散熱貼片具有至少二開孔，且二開孔分別位於晶片的相對兩側。二開孔的其一局部暴露出封裝膠體的第一部分，且二開孔的另一局部暴露出封裝膠體的第二部分。The invention provides a thin film flip chip packaging structure including a flexible substrate, a circuit layer, a chip, a packaging gel and a heat dissipation patch. The circuit layer and the chip are located on the flexible substrate. The chip is electrically connected to the circuit layer. The circuit layer is located between the flexible substrate and the wafer. The wafer has a first side and a second side opposite to each other. The encapsulant is at least filled between the flexible substrate and the chip. The encapsulant includes a first portion covering the first side of the wafer and a second portion covering the second side of the wafer. The heat dissipation patch is located on the flexible substrate and covers the chip and the packaging gel. The heat dissipation patch has at least two openings, and the two openings are respectively located on opposite sides of the wafer. One part of the two openings exposes the first part of the encapsulating colloid, and the other part of the two openings exposes the second part of the encapsulating colloid.

本發明另提供一種薄膜覆晶封裝結構包括可撓性基材、線路層、晶片、封裝膠體以及散熱貼片。線路層與晶片位於可撓性基材上。晶片電性連接線路層。線路層位於可撓性基材與晶片之間。晶片具有背向可撓性基材的背面以及連接背面且彼此相對的第一側面與第二側面。封裝膠體至少填充於可撓性基材與晶片之間。封裝膠體包括覆蓋晶片的第一側面的第一部分與覆蓋晶片的第二側面的第二部分。散熱貼片位於可撓性基材上，且覆蓋晶片以及封裝膠體。散熱貼片具有開孔，且開孔局部暴露出晶片的背面、封裝膠體的第一部分以及封裝膠體的第二部分。The invention also provides a thin film flip chip packaging structure including a flexible substrate, a circuit layer, a chip, a packaging gel and a heat dissipation patch. The circuit layer and the chip are located on the flexible substrate. The chip is electrically connected to the circuit layer. The circuit layer is located between the flexible substrate and the wafer. The wafer has a back surface facing away from the flexible substrate, and a first side surface and a second side surface connected to the back surface and facing each other. The encapsulant is at least filled between the flexible substrate and the chip. The encapsulant includes a first portion covering the first side of the wafer and a second portion covering the second side of the wafer. The heat dissipation patch is located on the flexible substrate and covers the chip and the packaging gel. The heat dissipation patch has an opening, and the opening partially exposes the back surface of the wafer, the first part of the encapsulation gel, and the second part of the encapsulation gel.

基於上述，本發明的薄膜覆晶封裝結構的散熱貼片具有至少二開孔，二開孔分別位於晶片的相對兩側，使二開孔的其一局部暴露出封裝膠體的第一部分，且二開孔的另一局部暴露出封裝膠體的第二部分。此外，本發明的薄膜覆晶封裝結構的散熱貼片也可以是具有自晶片的一側跨越晶片的背面至晶片的另一側的開孔，使開孔局部暴露出晶片的背面、封裝膠體的第一部分以及封裝膠體的第二部分，因此藉由在散熱貼片上設置開孔可以有助於作業人員即時確認散熱貼片是否有平順貼合於晶片與封裝膠體上，進而可使本發明的薄膜覆晶封裝結構具有良好的散熱效率。Based on the above, the heat dissipation patch of the thin-film flip-chip packaging structure of the present invention has at least two openings, the two openings are located on opposite sides of the wafer, respectively, so that one of the two openings partially exposes the first part of the packaging colloid, and two The other part of the opening exposes the second part of the encapsulant. In addition, the heat dissipation patch of the thin film flip chip packaging structure of the present invention may also have an opening that spans from one side of the wafer across the back surface of the wafer to the other side of the wafer, so that the opening partially exposes the back surface of the wafer and the encapsulant The first part and the second part of the encapsulating colloid, therefore, by providing an opening in the heat dissipation patch, it can help the operator to confirm whether the heat dissipation patch fits smoothly on the chip and the encapsulation colloid in real time. The thin film flip chip packaging structure has good heat dissipation efficiency.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。The invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

圖1A是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。圖1B是圖1A沿剖線A-A’的剖面示意圖。請同時參考圖1A與圖1B，在本實施例中，薄膜覆晶封裝結構100包括可撓性基材110、線路層120、晶片130、封裝膠體140以及散熱貼片150。可撓性基材110的材質例如是聚乙烯對苯二甲酸酯（polyethylene terephthalate, PET）、聚醯亞胺（Polyimide, PI）、聚醚（polyethersulfone, PES）、碳酸脂（polycarbonate, PC）或其他適合的可撓性材料。FIG. 1A is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view of Fig. 1A taken along line A-A'. Please refer to FIG. 1A and FIG. 1B at the same time. In this embodiment, the flip-chip thin film packaging structure 100 includes a flexible substrate 110, a circuit layer 120, a chip 130, an encapsulant 140, and a heat sink 150. The material of the flexible substrate 110 is, for example, polyethylene terephthalate (PET), polyimide (Polyimide, PI), polyether (PES), carbonate (polycarbonate, PC) Or other suitable flexible materials.

在本實施例中，線路層120位於可撓性基材110上，其中線路層120可以包括多個引腳122，如圖1A所示。晶片130位於可撓性基材110上，且電性連接線路層120。晶片130可以是採用覆晶（flip-chip）的方式電性連接至線路層120，如圖1B所示。進一步而言，線路層120位於可撓性基材110與晶片130之間，且晶片130的相對兩側具有彼此相對的第一側面130a與第二側面130b。更具體而言，在本實施例中，晶片130具有相對的兩個短邊側與相對的兩個長邊側，而彼此相對的第一側面130a與第二側面130b位於長邊側。特別說明的是，本發明不限制多個引腳122的配置方式與晶片130的種類，可視實際設計需求而定。In this embodiment, the circuit layer 120 is located on the flexible substrate 110, wherein the circuit layer 120 may include a plurality of pins 122, as shown in FIG. 1A. The chip 130 is located on the flexible substrate 110 and is electrically connected to the circuit layer 120. The chip 130 may be electrically connected to the circuit layer 120 in a flip-chip manner, as shown in FIG. 1B. Further, the circuit layer 120 is located between the flexible substrate 110 and the wafer 130, and opposite sides of the wafer 130 have a first side 130a and a second side 130b opposite to each other. More specifically, in the present embodiment, the wafer 130 has two opposite short-side sides and two opposite long-side sides, and the first side 130a and the second side 130b opposite to each other are located on the long side. In particular, the present invention does not limit the arrangement of the plurality of pins 122 and the type of the chip 130, which can be determined according to actual design requirements.

在本實施例中，封裝膠體140至少填充於可撓性基材110與晶片130之間。詳細而言，封裝膠體140包括覆蓋晶片130的第一側面130a的第一部分142與覆蓋晶片130的第二側面130b的第二部分144。封裝膠體140的材料例如是環氧模壓樹脂(Epoxy Molding Compound, EMC)。特別說明的是，在本實施例中，第一部分142繪示為覆蓋整個第一側面130a，且第二部分144繪示為覆蓋整個第二側面130b，然而本發明對此不作限制，第一部分142可僅覆蓋部分的第一側面130a，第二部分144可僅覆蓋部分的第二側面130b。In this embodiment, the encapsulant 140 is at least filled between the flexible substrate 110 and the wafer 130. In detail, the encapsulant 140 includes a first portion 142 covering the first side 130a of the wafer 130 and a second portion 144 covering the second side 130b of the wafer 130. The material of the encapsulant 140 is, for example, epoxy molding resin (Epoxy Molding Compound, EMC). In particular, in this embodiment, the first part 142 is shown to cover the entire first side 130a, and the second part 144 is shown to cover the entire second side 130b, however, the invention is not limited to this, the first part 142 Only a part of the first side 130a may be covered, and the second part 144 may only cover a part of the second side 130b.

在本實施例中，散熱貼片150位於可撓性基材110上，且覆蓋晶片130以及封裝膠體140。散熱貼片150具有第一開孔152與第二開孔154。第一開孔152與第二開孔154分別位於晶片130的相對兩側。更具體而言，在本實施例中，第一開孔152與第二開孔154分別位於晶片130的兩個長邊側。此外，第一開孔152局部暴露出封裝膠體140的第一部分142；而第二開孔154局部暴露出封裝膠體140的第二部分144。藉由第一開孔152與第二開孔154的設置，可以有助於作業人員即時確認散熱貼片150是否有平順貼合於晶片130與封裝膠體140上，進而可使本發明的薄膜覆晶封裝結構100具有良好的散熱效率。特別說明的是，在本實施例中僅繪示第一開孔152與第二開孔154，然而本發明不限制開孔數量為兩個，可視實際設計需求而定。此外，儘管在圖1A中繪示的第一開孔152與第二開孔154的開孔大小相同，然而本發明不限於此，可視實際需求調整開孔大小。換句話說，第一開孔152與第二開孔154的開孔大小可以相同或不同。In this embodiment, the heat dissipation patch 150 is located on the flexible substrate 110 and covers the chip 130 and the encapsulant 140. The heat dissipation patch 150 has a first opening 152 and a second opening 154. The first opening 152 and the second opening 154 are respectively located on opposite sides of the wafer 130. More specifically, in this embodiment, the first opening 152 and the second opening 154 are respectively located on the two long sides of the wafer 130. In addition, the first opening 152 partially exposes the first portion 142 of the encapsulant 140; and the second opening 154 partially exposes the second portion 144 of the encapsulant 140. The arrangement of the first opening 152 and the second opening 154 can help the operator to immediately confirm whether the heat dissipation patch 150 is smoothly attached to the chip 130 and the encapsulant 140, so that the film of the present invention can be covered The crystal package structure 100 has good heat dissipation efficiency. In particular, in this embodiment, only the first opening 152 and the second opening 154 are shown. However, the present invention does not limit the number of openings to two, depending on the actual design requirements. In addition, although the opening sizes of the first opening 152 and the second opening 154 shown in FIG. 1A are the same, the present invention is not limited thereto, and the opening size can be adjusted according to actual needs. In other words, the opening sizes of the first opening 152 and the second opening 154 may be the same or different.

在一些實施例中，為了更全面的觀察散熱貼片150中同一區塊的貼合情形，因此薄膜覆晶封裝結構100的第一開孔152與第二開孔154於晶片130的相對兩側可以為對位配置。在此，對位配置即在第一方向R1上第一開孔152或第二開孔154互相對準。換句話說，第一開孔152與第二開孔154分別位於第二方向R2的相同位置上而形成對位。In some embodiments, in order to more fully observe the bonding of the same block in the heat dissipation patch 150, the first opening 152 and the second opening 154 of the flip-chip packaging structure 100 are on opposite sides of the chip 130 Can be configured for alignment. Here, the alignment configuration, that is, the first opening 152 or the second opening 154 is aligned with each other in the first direction R1. In other words, the first opening 152 and the second opening 154 are located at the same position in the second direction R2 to form the alignment.

在一些實施例中，為了有效地維持線路層120的特性，薄膜覆晶封裝結構100還可以包括防焊層102。防焊層102位於線路層120上，以避免線路層120產生氧化。防焊層102可以覆蓋部分線路層120，並裸露出另一部分線路層120以用於與晶片130和外部元件電性連接。防焊層102的材料例如是綠漆。In some embodiments, in order to effectively maintain the characteristics of the circuit layer 120, the thin film flip chip packaging structure 100 may further include a solder resist layer 102. The solder resist layer 102 is located on the circuit layer 120 to prevent the circuit layer 120 from being oxidized. The solder resist layer 102 may cover part of the circuit layer 120 and expose another part of the circuit layer 120 for electrical connection with the wafer 130 and external components. The material of the solder mask 102 is, for example, green paint.

在一些實施例中，散熱貼片150可以包括金屬層156與絕緣薄膜158。在本實施例中，金屬層156覆蓋晶片130、封裝膠體140的第一部分142以及封裝膠體140的第二部分144，絕緣薄膜158覆蓋金屬層156，而散熱貼片150的第一開孔152與第二開孔154同時形成於金屬層156與絕緣薄膜158。換句話說，金屬層156與絕緣薄膜158藉由第一開孔152局部暴露出第一部分142與藉由第二開孔154暴露出第二部分144。絕緣薄膜158的面積可以是大於金屬層156的面積，因此絕緣薄膜158可以完全覆蓋金屬層156。在一些實施例中，金屬層156與絕緣薄膜158可以進一步延伸至防焊層102並與防焊層102貼合。金屬層156的材料例如是具有良好導熱能力的銅或鋁；而絕緣薄膜158的材料例如是聚醯亞胺等可撓性材料，用以保護金屬層156，避免金屬層156刮傷受損，並加強固定金屬層156於可撓性基材110上；絕緣薄膜158的材料也可以是包括散熱粒子的絕緣材料，因此可以進一步提升薄膜覆晶封裝結構100的散熱效率。In some embodiments, the heat dissipation patch 150 may include a metal layer 156 and an insulating film 158. In this embodiment, the metal layer 156 covers the wafer 130, the first portion 142 of the encapsulant 140 and the second portion 144 of the encapsulant 140, the insulating film 158 covers the metal layer 156, and the first opening 152 of the heat dissipation patch 150 is The second opening 154 is simultaneously formed in the metal layer 156 and the insulating film 158. In other words, the metal layer 156 and the insulating film 158 partially expose the first portion 142 through the first opening 152 and the second portion 144 through the second opening 154. The area of the insulating film 158 may be larger than the area of the metal layer 156, so the insulating film 158 may completely cover the metal layer 156. In some embodiments, the metal layer 156 and the insulating film 158 may further extend to and adhere to the solder resist layer 102. The material of the metal layer 156 is, for example, copper or aluminum with good thermal conductivity; the material of the insulating film 158 is a flexible material such as polyimide to protect the metal layer 156 and prevent the metal layer 156 from being scratched and damaged. Furthermore, the metal layer 156 is strengthened and fixed on the flexible substrate 110; the material of the insulating film 158 may also be an insulating material including heat dissipation particles, so that the heat dissipation efficiency of the thin film flip chip packaging structure 100 can be further improved.

請繼續參考圖1B，晶片130具有背向可撓性基材110的背面130c。封裝膠體140的第一部分142具有第一表面142a；而封裝膠體140的第二部分144具有第二表面144a。在本實施例中，第一表面142a與第二表面144a分別連接晶片130的背面130c的相對兩邊緣。散熱貼片150順應貼合晶片130的背面130c、封裝膠體140的第一部分142的第一表面142a以及封裝膠體140的第二部分144的第二表面144a。詳細而言，由於晶片130運行時，大部分的熱會經由晶片130的背面130c或經由封裝膠體140傳遞至外界，因此散熱貼片150順應貼合晶片130的背面130c、第一部分142的第一表面142a以及第二部分144的第二表面144a可以增加散熱面積，進而可以更進一步提升本發明的薄膜覆晶封裝結構100的散熱效率。Please continue to refer to FIG. 1B, the wafer 130 has a back surface 130 c facing away from the flexible substrate 110. The first portion 142 of the encapsulant 140 has a first surface 142a; and the second portion 144 of the encapsulant 140 has a second surface 144a. In this embodiment, the first surface 142a and the second surface 144a are respectively connected to opposite edges of the back surface 130c of the wafer 130. The heat dissipation patch 150 conforms to the back 130 c of the wafer 130, the first surface 142 a of the first portion 142 of the encapsulant 140 and the second surface 144 a of the second portion 144 of the encapsulant 140. In detail, when the wafer 130 is in operation, most of the heat is transferred to the outside through the back surface 130c of the wafer 130 or through the encapsulant 140. Therefore, the heat dissipation patch 150 conforms to the first surface of the back surface 130c of the wafer 130 and the first portion 142 The surface 142a and the second surface 144a of the second portion 144 can increase the heat dissipation area, and thus can further improve the heat dissipation efficiency of the thin film flip-chip packaging structure 100 of the present invention.

在本實施例中，第一部分142的第一表面142a具有自晶片130延伸至可撓性基材110的第一長度L1；而第二部分144的第二表面144a具有自晶片130延伸至可撓性基材110的第二長度L2。詳細而言，在本實施例中，第一長度L1為在R1方向上自晶片130的背面130c的一邊緣順應第一表面142a由上而下延伸至可撓性基材110的長度；而第二長度L2為在R1方向上自晶片130的背面130c的另一邊緣順應第二表面144a由上而下延伸至可撓性基材110的長度。散熱貼片150的第一開孔152至少暴露出80%的第一長度L1；而第二開孔154至少暴露出80%的第二長度L2。在一些實施例中，散熱貼片150的第一開孔152可以是暴露出部分的第一長度L1；而第二開孔154可以是暴露出部分的第二長度L2。在一些其他實施例中，散熱貼片150的第一開孔152也可以是完全暴露出第一長度L1；而第二開孔154也可以是完全暴露出第二長度L2，如圖1B所示。因此藉由散熱貼片150的第一開孔152至少暴露出80%的第一長度L1；而第二開孔154至少暴露出80%的第二長度L2可以更有效的觀測到散熱貼片150與晶片130及封裝膠體140之間的緊貼程度，並即時調整未平順貼合的情形，進而可以改善後續的產品良率以及可靠度。In this embodiment, the first surface 142a of the first portion 142 has a first length L1 extending from the wafer 130 to the flexible substrate 110; and the second surface 144a of the second portion 144 has a extending from the wafer 130 to the flexible Length L2 of the base material 110. In detail, in this embodiment, the first length L1 is a length extending from the top of the back surface 130c of the wafer 130 to the flexible substrate 110 from the top to the bottom of the first surface 142a in the R1 direction; The two lengths L2 are the lengths extending from the other edge of the back surface 130c of the wafer 130 in the R1 direction to the second surface 144a to the flexible substrate 110 from top to bottom. The first opening 152 of the heat dissipation patch 150 exposes at least 80% of the first length L1; and the second opening 154 exposes at least 80% of the second length L2. In some embodiments, the first opening 152 of the heat dissipation patch 150 may be the first length L1 of the exposed portion; and the second opening 154 may be the second length L2 of the exposed portion. In some other embodiments, the first opening 152 of the heat dissipation patch 150 may also completely expose the first length L1; and the second opening 154 may also completely expose the second length L2, as shown in FIG. 1B . Therefore, the first opening 152 of the heat dissipation patch 150 exposes at least 80% of the first length L1; and the second opening 154 exposes at least 80% the second length L2 of the heat dissipation patch 150. The degree of adhesion between the chip 130 and the encapsulant 140, and the situation of non-smooth adhesion can be adjusted in real time, which can improve the subsequent product yield and reliability.

在此必須說明的是，以下實施例沿用上述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明，關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。It must be noted here that the following embodiments continue to use the element labels and partial contents of the above embodiments, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted, and the description of the omitted portions Reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

圖2是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。請參考圖2，本實施例的薄膜覆晶封裝結構100a類似於上述實施例的薄膜覆晶封裝結構100，而其差別在於：本實施例的薄膜覆晶封裝結構100a的第一開孔152與第二開孔154於晶片130的相對兩側(第一側面130a與第二側面130b)為錯位配置。在此，錯位配置即在第一方向R1上第一開孔152或第二開孔154不會互相對準。換句話說，第一開孔152與第二開孔154分別位於第二方向R2的不同位置上而形成錯位。藉由第一開孔152與第二開孔154於晶片130的相對兩側為錯位配置可以進一步確認晶片130上其他位置上散熱貼片150與晶片130及封裝膠體140之間的緊貼程度，進而有效提升薄膜覆晶封裝結構100a的整體散熱效率。FIG. 2 is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. Please refer to FIG. 2, the thin film flip chip packaging structure 100 a of this embodiment is similar to the thin film flip chip packaging structure 100 of the above embodiment, and the difference is that the first opening 152 of the thin film flip chip packaging structure 100 a of this embodiment is different from The second openings 154 are disposed on opposite sides of the wafer 130 (the first side 130 a and the second side 130 b ). Here, the misalignment configuration means that the first opening 152 or the second opening 154 will not be aligned with each other in the first direction R1. In other words, the first opening 152 and the second opening 154 are respectively located at different positions in the second direction R2 to form a misalignment. The first opening 152 and the second opening 154 are misaligned on opposite sides of the chip 130 to further confirm the tightness between the heat dissipation patch 150 and the chip 130 and the encapsulant 140 at other positions on the chip 130. Therefore, the overall heat dissipation efficiency of the thin film flip chip packaging structure 100a is effectively improved.

圖3是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。請參考圖3，本實施例的薄膜覆晶封裝結構100b類似於上述實施例的薄膜覆晶封裝結構100，而其差別在於：本實施例的薄膜覆晶封裝結構100b的散熱貼片1501的第一開孔1521與第二開孔1541可以進一步暴露出晶片130的背面130c。詳細而言，金屬層1561與絕緣薄膜1581覆蓋部分的第一部分142、部分的第二部分144與部分的背面130c，並藉由第一開孔1521及第二開孔1541暴露出另一部分的第一部分142、另一部分的第二部分144與另一部分的背面130c。FIG. 3 is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. Referring to FIG. 3, the thin-film flip-chip package structure 100b of this embodiment is similar to the thin-film flip-chip package structure 100 of the above embodiment, and the difference is that the heat dissipation patch 1501 of the thin-film flip-chip package structure 100b of this embodiment An opening 1521 and a second opening 1541 can further expose the back surface 130c of the wafer 130. In detail, the metal layer 1561 and the insulating film 1581 cover part of the first part 142, part of the second part 144, and part of the back surface 130c, and expose the other part of the first part through the first opening 1521 and the second opening 1541. One part 142, another part second part 144 and another part back 130c.

圖4A是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。圖4B是圖4A沿剖線B-B’的剖面示意圖。請參考圖4A與圖4B，本實施例的薄膜覆晶封裝結構100c類似於上述實施例的薄膜覆晶封裝結構100，而其差別在於：本實施例的散熱貼片1502具有開孔159，且開孔159局部暴露出晶片130的背面130c、封裝膠體140的第一部分142以及封裝膠體140的第二部分144。在本實施例中，散熱貼片1502僅具有一開孔159，且開孔159自晶片130的一側沿著第一方向R1延伸、跨越晶片130的背面130c至晶片130的另一側，因而局部暴露出封裝膠體140的第一部分142、晶片130的背面130c以及封裝膠體140的第二部分144。進一步而言，如圖4B所示，開孔159可以包括第一區塊159a、第二區塊159b以及第三區塊159c，其中第三區塊159c連接第一區塊159a與第二區塊159b。更進一步而言，第一區塊159a局部暴露出封裝膠體140的第一部分142；第二區塊159b局部暴露出封裝膠體140的第二部分144；而第三區塊159c局部暴露出晶片130的背面130c。特別說明的是，在本實施例中僅繪示一開孔159，然而本發明不限制自晶片的一側跨越晶片的背面至晶片的另一側的開孔數量為一個，可視實際設計需求而定。4A is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. Fig. 4B is a schematic cross-sectional view of Fig. 4A along section line B-B'. 4A and 4B, the thin film flip chip packaging structure 100c of this embodiment is similar to the thin film flip chip packaging structure 100 of the above embodiment, and the difference is that the heat dissipation patch 1502 of this embodiment has an opening 159, and The opening 159 partially exposes the back surface 130 c of the wafer 130, the first portion 142 of the encapsulant 140 and the second portion 144 of the encapsulant 140. In this embodiment, the heat dissipation patch 1502 has only one opening 159, and the opening 159 extends from one side of the wafer 130 along the first direction R1, across the back surface 130c of the wafer 130 to the other side of the wafer 130, thus The first portion 142 of the encapsulant 140, the back surface 130c of the wafer 130, and the second portion 144 of the encapsulant 140 are partially exposed. Further, as shown in FIG. 4B, the opening 159 may include a first block 159a, a second block 159b, and a third block 159c, wherein the third block 159c connects the first block 159a and the second block 159b. Furthermore, the first block 159a partially exposes the first portion 142 of the encapsulant 140; the second block 159b partially exposes the second portion 144 of the encapsulant 140; and the third block 159c partially exposes the chip 130 Back 130c. In particular, only one opening 159 is shown in this embodiment, however, the present invention does not limit the number of openings from one side of the wafer across the back of the wafer to the other side of the wafer to one, depending on actual design requirements set.

在一些實施例中，散熱貼片1502可以包括金屬層1562與絕緣薄膜1582。金屬層1562覆蓋晶片130、封裝膠體140的第一部分142以及封裝膠體140的第二部分144。絕緣薄膜1582覆蓋金屬層1562，而散熱貼片1502的開孔159同時形成於金屬層1562與絕緣薄膜1582。換句話說，金屬層1562與絕緣薄膜1582覆蓋部分的第一部分142與部分的第二部分144，並藉由開孔159暴露出另一部分的第一部分142與另一部分的第二部分144。In some embodiments, the heat dissipation patch 1502 may include a metal layer 1562 and an insulating film 1582. The metal layer 1562 covers the wafer 130, the first portion 142 of the encapsulant 140 and the second portion 144 of the encapsulant 140. The insulating film 1582 covers the metal layer 1562, and the opening 159 of the heat dissipation patch 1502 is simultaneously formed in the metal layer 1562 and the insulating film 1582. In other words, the metal layer 1562 and the insulating film 1582 cover part of the first part 142 and part of the second part 144, and expose the other part of the first part 142 and the second part 144 through the opening 159.

請繼續參考圖4B，散熱貼片1502順應貼合晶片130的背面130c、封裝膠體140的第一部分142的第一表面142a以及封裝膠體140的第二部分144的第二表面144a。在一些實施例中，散熱貼片1502的開孔159至少暴露出80%的第一長度L1與80%的第二長度L2。散熱貼片1502、金屬層1562與絕緣薄膜1582可以類似圖1B中散熱貼片150、金屬層156與絕緣薄膜158所描述的內容，於此不再贅述。4B, the heat dissipation patch 1502 conforms to the back surface 130c of the wafer 130, the first surface 142a of the first portion 142 of the encapsulant 140, and the second surface 144a of the second portion 144 of the encapsulant 140. In some embodiments, the opening 159 of the heat dissipation patch 1502 exposes at least 80% of the first length L1 and 80% of the second length L2. The heat dissipation patch 1502, the metal layer 1562, and the insulating film 1582 may be similar to those described in the heat dissipation patch 150, the metal layer 156, and the insulating film 158 in FIG. 1B, and details are not described herein again.

圖5A是本發明一實施例的薄膜覆晶封裝結構的剖面示意圖。請參考圖5A，本實施例的薄膜覆晶封裝結構100d類似於上述實施例的薄膜覆晶封裝結構100，而其差別在於：本實施例的薄膜覆晶封裝結構100d的散熱貼片1503的第一開孔152與第二開孔154被絕緣薄膜1583覆蓋。換句話說，第一開孔152與第二開孔154僅貫穿金屬層156。詳細而言，當絕緣薄膜1583為透明度較高的材料時，第一開孔152與第二開孔154可以被絕緣薄膜1583覆蓋，作業人員可以直接透過絕緣薄膜1583觀測到第一開孔152與第二開孔154中的情形。5A is a schematic cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the invention. Referring to FIG. 5A, the thin-film flip-chip package structure 100d of this embodiment is similar to the thin-film flip-chip package structure 100 of the above embodiment, and the difference is that the heat dissipation patch 1503 of the thin-film flip-chip package structure 100d of this embodiment An opening 152 and a second opening 154 are covered by an insulating film 1583. In other words, the first opening 152 and the second opening 154 only penetrate the metal layer 156. In detail, when the insulating film 1583 is a material with high transparency, the first opening 152 and the second opening 154 can be covered by the insulating film 1583, and the operator can directly observe the first opening 152 and the first opening 152 through the insulating film 1583. The situation in the second opening 154.

圖5B是本發明一實施例的薄膜覆晶封裝結構的剖面示意圖。請參考圖5B，本實施例的薄膜覆晶封裝結構100e類似於上述實施例的薄膜覆晶封裝結構100c，而其差別在於：本實施例的薄膜覆晶封裝結構100e的散熱貼片1504的開孔159被絕緣薄膜1583覆蓋。換句話說，開孔159僅貫穿金屬層1562。詳細而言，第一區塊159a、第二區塊159b以及第三區塊159c皆被絕緣薄膜1583覆蓋。由於絕緣薄膜1583為透明度較高的材料，因此作業人員可以直接透過絕緣薄膜1583觀測到開孔159中的情形。5B is a schematic cross-sectional view of a flip-chip thin film packaging structure according to an embodiment of the invention. Referring to FIG. 5B, the thin film flip chip packaging structure 100e of this embodiment is similar to the thin film flip chip packaging structure 100c of the above embodiment, and the difference is that the heat dissipation patch 1504 of the thin film flip chip packaging structure 100e of this embodiment is opened. The hole 159 is covered with an insulating film 1583. In other words, the opening 159 only penetrates the metal layer 1562. In detail, the first block 159a, the second block 159b, and the third block 159c are covered by the insulating film 1583. Since the insulating film 1583 is a material with high transparency, the operator can directly observe the situation in the opening 159 through the insulating film 1583.

綜上所述，本發明的薄膜覆晶封裝結構的散熱貼片具有至少二開孔，二開孔分別位於晶片的相對兩側，使二開孔的其一局部暴露出封裝膠體的第一部分，且二開孔的另一局部暴露出封裝膠體的第二部分。此外，本發明的薄膜覆晶封裝結構的散熱貼片也可以是具有自晶片的一側跨越晶片的背面至晶片的另一側的開孔，使開孔局部暴露出晶片的背面、封裝膠體的第一部分以及封裝膠體的第二部分。因此藉由在散熱貼片上設置開孔可以有助於作業人員即時確認散熱貼片是否有平順貼合於晶片與封裝膠體上，進而可使本發明的薄膜覆晶封裝結構具有良好的散熱效率。In summary, the heat dissipation patch of the thin-film flip-chip packaging structure of the present invention has at least two openings, which are respectively located on opposite sides of the chip, so that one of the two openings partially exposes the first part of the encapsulant, And the other part of the two openings exposes the second part of the encapsulating colloid. In addition, the heat dissipation patch of the thin film flip chip packaging structure of the present invention may also have an opening that spans from one side of the wafer across the back surface of the wafer to the other side of the wafer, so that the opening partially exposes the back surface of the wafer and the encapsulant The first part and the second part of the encapsulant. Therefore, by providing an opening in the heat dissipation patch, it can help the operator to confirm whether the heat dissipation patch is smoothly attached to the chip and the packaging colloid, so that the thin film flip chip packaging structure of the present invention has good heat dissipation efficiency .

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100、100a、100b、100c、100d、100e:薄膜覆晶封裝結構100, 100a, 100b, 100c, 100d, 100e: thin film flip chip packaging structure

102:防焊層102: solder mask

110:可撓性基材110: Flexible substrate

120:線路層120: line layer

122:引腳122: Pin

130:晶片130: chip

130a:第一側面130a: first side

130b:第二側面130b: second side

130c:背面130c: back

140:封裝膠體140: encapsulating colloid

142:第一部分142: Part One

142a:第一表面142a: first surface

144:第二部分144: Part Two

144a:第二表面144a: second surface

150、1501、1502、1503、1504:散熱貼片150, 1501, 1502, 1503, 1504: cooling patch

152、1521:第一開孔152, 1521: the first opening

154、1541:第二開孔154, 1541: second opening

159:開孔159: opening

156、1561、1562:金屬層156, 1561, 1562: metal layer

158、1581、1582、1583:絕緣薄膜158, 1581, 1582, 1583: insulating film

159a、159b、159c:區塊159a, 159b, 159c: block

L1:第一長度L1: the first length

L2:第二長度L2: second length

R1、R2:方向R1, R2: direction

圖1A是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。 圖1B是圖1A沿剖線A-A’的剖面示意圖。 圖2是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。 圖3是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。 圖4A是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。 圖4B是圖4A沿剖線B-B’的剖面示意圖。 圖5A是本發明一實施例的薄膜覆晶封裝結構的剖面示意圖。 圖5B是本發明一實施例的薄膜覆晶封裝結構的剖面示意圖。 特別說明的是，儘管圖1B是圖1A沿剖線A-A’的剖面示意圖及圖4B是圖4A沿剖線B-B’的剖面示意圖，然而，在圖1B與圖4B中為了清楚表示相關構件之間的關係，因此圖1B與圖4B並未按照與圖1A及圖4A對應的比例繪示。 FIG. 1A is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view of Fig. 1A taken along line A-A'. FIG. 2 is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. FIG. 3 is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. 4A is a schematic top view of a flip-chip thin film packaging structure according to an embodiment of the invention. Fig. 4B is a schematic cross-sectional view of Fig. 4A along section line B-B'. 5A is a schematic cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the invention. 5B is a schematic cross-sectional view of a flip-chip thin film packaging structure according to an embodiment of the invention. In particular, although FIG. 1B is a schematic cross-sectional view of FIG. 1A along section line AA′ and FIG. 4B is a cross-sectional schematic view of FIG. 4A along section line BB′, however, in FIGS. 1B and 4B for clarity, The relationship between related components, therefore, FIGS. 1B and 4B are not shown in proportions corresponding to FIGS. 1A and 4A.

100:薄膜覆晶封裝結構 100: Thin film flip chip packaging structure

102:防焊層 102: solder mask

110:可撓性基材 110: Flexible substrate

120:線路層 120: line layer

130:晶片 130: chip

130a:第一側面 130a: first side

130b:第二側面 130b: second side

130c:背面 130c: back

140:封裝膠體 140: encapsulating colloid

142:第一部分 142: Part One

142a:第一表面 142a: first surface

144:第二部分 144: Part Two

144a:第二表面 144a: second surface

150:散熱貼片 150: cooling patch

152:第一開孔 152: The first opening

154:第二開孔 154: Second opening

156:金屬層 156: Metal layer

158:絕緣薄膜 158: Insulating film

L1:第一長度 L1: the first length

L2:第二長度 L2: second length

R1:方向 R1: direction

Claims (10)

一種薄膜覆晶封裝結構，包括：可撓性基材；線路層，位於該可撓性基材上；晶片，位於該可撓性基材上，且電性連接該線路層，其中該線路層位於該可撓性基材與該晶片之間，且該晶片具有彼此相對的第一側面與第二側面；封裝膠體，至少填充於該可撓性基材與該晶片之間，且該封裝膠體包括覆蓋該晶片的該第一側面的第一部分與覆蓋該晶片的該第二側面的第二部分；以及散熱貼片，位於該可撓性基材上，且覆蓋該晶片以及該封裝膠體，其中該散熱貼片具有至少二開孔，且該二開孔分別位於該晶片的相對兩側且該二開孔於該晶片的相對兩側為錯位配置，該二開孔的其一局部暴露出該封裝膠體的該第一部分，且該二開孔的另一局部暴露出該封裝膠體的該第二部分。 A thin film flip-chip packaging structure includes: a flexible substrate; a circuit layer on the flexible substrate; a chip on the flexible substrate and electrically connected to the circuit layer, wherein the circuit layer Is located between the flexible substrate and the chip, and the chip has a first side and a second side opposite to each other; encapsulant, at least filled between the flexible substrate and the chip, and the encapsulant Including a first portion covering the first side of the chip and a second portion covering the second side of the chip; and a heat dissipation patch, located on the flexible substrate, and covering the chip and the encapsulant, wherein The heat dissipation patch has at least two openings, and the two openings are respectively located on opposite sides of the chip and the two openings are misaligned on the opposite sides of the chip. Part of the two openings expose the The first part of the encapsulant is encapsulated, and the other part of the two openings exposes the second part of the encapsulant. 如申請專利範圍第1項所述的薄膜覆晶封裝結構，其中該散熱貼片包括金屬層與絕緣薄膜，該金屬層覆蓋該晶片、該封裝膠體的該第一部分以及該封裝膠體的該第二部分，該絕緣薄膜覆蓋該金屬層。 The thin film flip-chip packaging structure as described in item 1 of the patent scope, wherein the heat dissipation patch includes a metal layer and an insulating film, the metal layer covers the chip, the first part of the encapsulant and the second part of the encapsulant In part, the insulating film covers the metal layer. 如申請專利範圍第2項所述的薄膜覆晶封裝結構，其中該散熱貼片的該二開孔形成於該金屬層，且該二開孔被該絕緣薄膜覆蓋。 The thin film flip chip packaging structure as described in item 2 of the patent application range, wherein the two openings of the heat dissipation patch are formed in the metal layer, and the two openings are covered by the insulating film. 如申請專利範圍第1項所述的薄膜覆晶封裝結構，其中該晶片還具有背向該可撓性基材的背面，該封裝膠體的該第一部分具有第一表面，且該封裝膠體的該第二部分具有第二表面，該散熱貼片順應貼合於該晶片的該背面、該第一部分的該第一表面以及該第二部分的該第二表面。 The thin film flip chip packaging structure as described in item 1 of the patent application range, wherein the wafer further has a back surface facing away from the flexible substrate, the first part of the encapsulating colloid has a first surface, and the encapsulating colloid The second portion has a second surface, and the heat dissipation patch conforms to the back surface of the wafer, the first surface of the first portion, and the second surface of the second portion. 如申請專利範圍第4項所述的薄膜覆晶封裝結構，其中該第一部分的該第一表面具有自該晶片延伸至該可撓性基材的第一長度，該第二部分的該第二表面具有自該晶片延伸至該可撓性基材的第二長度，該散熱貼片的該二開孔的其一至少暴露出80%的該第一長度，且該二開孔的另一至少暴露出80%的該第二長度。 The thin film flip-chip packaging structure as described in item 4 of the patent application scope, wherein the first surface of the first portion has a first length extending from the wafer to the flexible substrate, and the second portion of the second portion The surface has a second length extending from the wafer to the flexible substrate, one of the two openings of the heat dissipation patch exposes at least 80% of the first length, and the other of the two openings at least 80% of this second length is exposed. 一種薄膜覆晶封裝結構，包括：可撓性基材；線路層，位於該可撓性基材上；晶片，位於該可撓性基材上，且電性連接該線路層，其中該線路層位於該可撓性基材與該晶片之間，且該晶片具有背向該可撓性基材的背面以及連接該背面且彼此相對的第一側面與第二側面；封裝膠體，至少填充於該可撓性基材與該晶片之間，且該封裝膠體包括覆蓋該晶片的該第一側面的第一部分與覆蓋該晶片的該第二側面的第二部分；以及 散熱貼片，位於該可撓性基材上，且覆蓋該晶片以及該封裝膠體，其中該散熱貼片具有開孔，且該開孔局部暴露出該晶片的該背面、該封裝膠體的該第一部分以及該封裝膠體的該第二部分。 A thin film flip-chip packaging structure includes: a flexible substrate; a circuit layer on the flexible substrate; a chip on the flexible substrate and electrically connected to the circuit layer, wherein the circuit layer Is located between the flexible substrate and the wafer, and the wafer has a back surface facing away from the flexible substrate, and a first side and a second side connected to the back surface and opposite to each other; the encapsulant is at least filled in the Between the flexible substrate and the wafer, and the encapsulant includes a first portion covering the first side of the wafer and a second portion covering the second side of the wafer; and The heat dissipation patch is located on the flexible substrate and covers the chip and the encapsulating colloid, wherein the heat dissipation patch has an opening, and the opening partially exposes the back surface of the chip and the encapsulating colloid A part and the second part of the encapsulating colloid. 如申請專利範圍第6項所述的薄膜覆晶封裝結構，其中該散熱貼片包括金屬層與絕緣薄膜，該金屬層覆蓋該晶片、該封裝膠體的該第一部分以及該封裝膠體的該第二部分，該絕緣薄膜覆蓋該金屬層。 The thin film flip-chip packaging structure as described in item 6 of the patent application range, wherein the heat dissipation patch includes a metal layer and an insulating film, the metal layer covers the chip, the first part of the encapsulant and the second part of the encapsulant In part, the insulating film covers the metal layer. 如申請專利範圍第7項所述的薄膜覆晶封裝結構，其中該散熱貼片的該開孔形成於該金屬層，且該開孔被該絕緣薄膜覆蓋。 The thin film flip chip packaging structure as described in item 7 of the patent application range, wherein the opening of the heat dissipation patch is formed in the metal layer, and the opening is covered by the insulating film. 如申請專利範圍第6項所述的薄膜覆晶封裝結構，其中該封裝膠體的該第一部分具有第一表面，且該封裝膠體的該第二部分具有第二表面，該散熱貼片順應貼合於該晶片的該背面、該第一部分的該第一表面以及該第二部分的該第二表面。 The thin film flip-chip packaging structure as described in item 6 of the patent application range, wherein the first part of the encapsulating colloid has a first surface, and the second part of the encapsulating colloid has a second surface, and the heat dissipation patch conforms to the fit The back surface of the wafer, the first surface of the first portion, and the second surface of the second portion. 如申請專利範圍第9項所述的薄膜覆晶封裝結構，其中該第一部分的該第一表面具有自該晶片延伸至該可撓性基材的第一長度，該第二部分的該第二表面具有自該晶片延伸至該可撓性基材的第二長度，該散熱貼片的該開孔至少暴露出80%的該第一長度與80%的該第二長度。The thin film flip-chip packaging structure as described in item 9 of the patent application range, wherein the first surface of the first portion has a first length extending from the wafer to the flexible substrate, and the second portion of the second portion The surface has a second length extending from the wafer to the flexible substrate, and the opening of the heat dissipation patch exposes at least 80% of the first length and 80% of the second length.
TW108107506A 2019-03-06 2019-03-06 Chip on film package structure TWI697079B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW108107506A TWI697079B (en) 2019-03-06 2019-03-06 Chip on film package structure
CN201910374014.2A CN111668172B (en) 2019-03-06 2019-05-07 Thin film flip chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108107506A TWI697079B (en) 2019-03-06 2019-03-06 Chip on film package structure

Publications (2)

Publication Number Publication Date
TWI697079B true TWI697079B (en) 2020-06-21
TW202034467A TW202034467A (en) 2020-09-16

Family

ID=72176481

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108107506A TWI697079B (en) 2019-03-06 2019-03-06 Chip on film package structure

Country Status (2)

Country Link
CN (1) CN111668172B (en)
TW (1) TWI697079B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743915B (en) * 2020-07-31 2021-10-21 大陸商河南烯力新材料科技有限公司 Chip on film package structure and display device
TWI794115B (en) * 2022-06-14 2023-02-21 大陸商北京集創北方科技股份有限公司 Thin Film Chip Package Structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114613266A (en) * 2022-03-07 2022-06-10 深圳市华星光电半导体显示技术有限公司 Display module and display device
CN114721188A (en) * 2022-03-29 2022-07-08 颀中科技（苏州）有限公司 Forming method of flip chip packaging structure, flip chip packaging structure and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674241A (en) * 2004-03-22 2005-09-28 夏普株式会社 Semiconductor device and manufacturing method thereof, and liquid crystal module and semiconductor module having the same
CN101404267A (en) * 2007-10-03 2009-04-08 松下电器产业株式会社 Semiconductor device and method of manufacturing the same
US20120193803A1 (en) * 2011-01-28 2012-08-02 Renesas Electronics Corporation Semiconductor device, method for producing semiconductor device, and display
TW201810561A (en) * 2016-06-02 2018-03-16 南茂科技股份有限公司 Chip on film package structure
US20180342437A1 (en) * 2015-12-02 2018-11-29 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10043737B2 (en) * 2015-12-02 2018-08-07 Novatek Microelectronics Corp. Chip on film package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674241A (en) * 2004-03-22 2005-09-28 夏普株式会社 Semiconductor device and manufacturing method thereof, and liquid crystal module and semiconductor module having the same
CN101404267A (en) * 2007-10-03 2009-04-08 松下电器产业株式会社 Semiconductor device and method of manufacturing the same
US20120193803A1 (en) * 2011-01-28 2012-08-02 Renesas Electronics Corporation Semiconductor device, method for producing semiconductor device, and display
US20180342437A1 (en) * 2015-12-02 2018-11-29 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package
TW201810561A (en) * 2016-06-02 2018-03-16 南茂科技股份有限公司 Chip on film package structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743915B (en) * 2020-07-31 2021-10-21 大陸商河南烯力新材料科技有限公司 Chip on film package structure and display device
TWI794115B (en) * 2022-06-14 2023-02-21 大陸商北京集創北方科技股份有限公司 Thin Film Chip Package Structure

Also Published As

Publication number Publication date
TW202034467A (en) 2020-09-16
CN111668172B (en) 2022-05-03
CN111668172A (en) 2020-09-15

Similar Documents

Publication Publication Date Title
TWI697079B (en) Chip on film package structure
US6982488B2 (en) Semiconductor package and method for fabricating the same
US7327032B2 (en) Semiconductor package accomplishing fan-out structure through wire bonding
US9570405B2 (en) Semiconductor device and method for manufacturing same
US20150069596A1 (en) Semiconductor device and method of manufacturing the same
US7994635B2 (en) Power semiconductor module
JP2011101044A (en) Stacked package and method of manufacturing the same
TWI428995B (en) Shrink package on board
CN104241235A (en) Semiconductor device
KR20150125814A (en) Semiconductor Package Device
US20040222519A1 (en) Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
TWI700786B (en) Chip-on-film package structure
TW200812023A (en) Heat slug for package structure
TW201644328A (en) Chip package structure
TWI767543B (en) Package structure
TWI463610B (en) Substrate structure and die package integrating the substrate structure
TWI447889B (en) Chip package structure
US7190063B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic apparatus
JP2005252074A (en) Semiconductor device and electronic apparatus
US20080087999A1 (en) Micro BGA package having multi-chip stack
US20080088039A1 (en) Substrate with heat-dissipating dummy pattern for semiconductor packages
TW200847372A (en) Tape type semiconductor package and its substrate
TWI776142B (en) Chip on film package structure
KR100421777B1 (en) semiconductor package
US20160064301A1 (en) Semiconductor device