TWI556366B - Chip-on-film package structure and flexible circuit board thereof - Google Patents

Chip-on-film package structure and flexible circuit board thereof Download PDF

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Publication number
TWI556366B
TWI556366B TW103118292A TW103118292A TWI556366B TW I556366 B TWI556366 B TW I556366B TW 103118292 A TW103118292 A TW 103118292A TW 103118292 A TW103118292 A TW 103118292A TW I556366 B TWI556366 B TW I556366B
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Taiwan
Prior art keywords
trench
wafer
encapsulant
solder resist
package structure
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TW103118292A
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Chinese (zh)
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TW201545284A (en
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林士熙
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南茂科技股份有限公司
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Priority to TW103118292A priority Critical patent/TWI556366B/en
Priority to CN201410402892.8A priority patent/CN105321895B/en
Publication of TW201545284A publication Critical patent/TW201545284A/en
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Publication of TWI556366B publication Critical patent/TWI556366B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Description

薄膜覆晶封裝結構及其可撓性線路載板 Film flip chip package structure and flexible circuit carrier

本發明是有關於一種封裝結構及其線路載板,且特別是有關於一種薄膜覆晶封裝結構及其可撓性線路載板。 The present invention relates to a package structure and a line carrier thereof, and more particularly to a film flip chip package structure and a flexible line carrier.

隨著半導體技術的改良,使得液晶顯示器具有低的消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點,因而廣泛地應用在行動電話、筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。其中,顯示器之驅動晶片(driver IC)更是液晶顯示器不可或缺的重要元件。 With the improvement of semiconductor technology, liquid crystal displays have the advantages of low power consumption, light weight, high resolution, high color saturation, long life, etc., and thus are widely used in mobile phones, notebook computers or desktop computers. LCD screens and LCD TVs and other electronic products that are closely related to life. Among them, the driver IC of the display is an indispensable component of the liquid crystal display.

因應液晶顯示裝置驅動晶片各種應用之需求,一般是採用捲帶自動接合(tape automatic bonding,TAB)封裝技術進行晶片封裝,其中又分成薄膜覆晶(Chip-On-Film,COF)封裝及捲帶承載封裝(Tape Carrier Package,TCP)。通常而言,以捲帶自動接合方式進行晶片封裝的製程,係首先使晶片上的凸塊與可撓性基板上的內引腳產生共晶接合而電性連接。接著,於晶片與可撓性 基板之間形成封裝膠體,藉以保護凸塊與內引腳之間的電性接點。 In order to meet the needs of various applications of liquid crystal display device driving wafers, tape automatic bonding (TAB) packaging technology is generally used for chip packaging, which is further divided into Chip-On-Film (COF) package and tape winding. Tape Carrier Package (TCP). Generally, the process of wafer packaging by tape and tape automatic bonding is to first electrically bond the bumps on the wafer to the inner leads on the flexible substrate. Next, on the wafer and flexibility An encapsulant is formed between the substrates to protect the electrical contacts between the bumps and the inner leads.

通常而言,薄膜覆晶封裝的封裝膠體是以點膠(potting)的方式形成於封裝基材上,以填充於晶片與封裝基材之間以及晶片之四周。在以點膠針頭繞行晶片之周邊以將封裝膠體注入時,封裝膠體130會藉由毛細現象而自晶片之周邊往內部延伸而填滿晶片與封裝基材之間所構成的空間,其中為使封裝膠能順利流動,未固化的封裝膠體具有相當程度的流動性。然而,基於封裝膠體之流動性,使其亦會朝向遠離晶片的方向流動,進而造成封裝膠體的塗佈範圍(potting area)的管控不易,較難符合一些特殊設計規範。 Generally, a packaged colloid of a film flip chip package is formed on a package substrate in a potting manner to fill between the wafer and the package substrate and around the wafer. When the encapsulant is injected around the periphery of the wafer by the dispensing needle, the encapsulant 130 extends from the periphery of the wafer to the inside by the capillary phenomenon to fill the space formed between the wafer and the package substrate. The encapsulant can flow smoothly, and the uncured encapsulant has a considerable degree of fluidity. However, based on the fluidity of the encapsulant, it also flows in a direction away from the wafer, which makes the potting area of the encapsulant difficult to control, and it is difficult to meet some special design specifications.

另一方面,由於薄膜覆晶封裝結構之後會做彎折以進行後續之應用,因應部分產品設計之要求,例如指紋辨識感測器等,其彎折的位置非常靠近晶片,而固化後的封裝膠體會阻礙可撓性基板的彎折,故封裝膠體的塗佈範圍有逐漸縮減的趨勢。然而,基於封裝膠體之流動性,使封裝膠體塗佈範圍(potting area)的管控不易,以至於塗佈範圍無法有效縮減,而難以符合產品設計之要求。 On the other hand, since the film flip-chip package structure will be bent for subsequent applications, in accordance with some product design requirements, such as fingerprint identification sensors, the bending position is very close to the wafer, and the cured package The colloid hinders the bending of the flexible substrate, so the coating range of the encapsulant tends to be gradually reduced. However, based on the fluidity of the encapsulant, the control of the potting area of the encapsulant is not easy, so that the coating range cannot be effectively reduced, and it is difficult to meet the requirements of product design.

本發明提供一種薄膜覆晶封裝結構及其可撓性線路載板,其可符合縮減封裝膠體的塗佈範圍的設計趨勢,並可使塗佈範圍落在容許公差值內。 The present invention provides a thin film flip-chip package structure and a flexible wiring carrier thereof, which can conform to the design trend of reducing the coating range of the encapsulant, and can make the coating range fall within the tolerance value.

本發明提出一種薄膜覆晶封裝結構,其包括可撓性線路載板、晶片以及封裝膠體。可撓性線路載板包括可撓性基材、圖案化線路層以及擋止材料。可撓性基材具有表面以及位於前述表面的晶片接合區與溝渠,且溝渠環繞於晶片接合區之外。圖案化線路層配置於前述表面上。擋止材料填充於溝渠中。晶片配置於可撓性基材上且位於晶片接合區內,並與圖案化線路層電性連接。封裝膠體形成於晶片與可撓性基材之間以及晶片之四周,其中封裝膠體與擋止材料接觸,且封裝膠體的側緣位於擋止材料上。 The invention provides a thin film flip chip package structure comprising a flexible circuit carrier, a wafer and an encapsulant. The flexible circuit carrier includes a flexible substrate, a patterned wiring layer, and a stop material. The flexible substrate has a surface and a wafer bond region and trench on the surface, and the trench surrounds the wafer bond region. The patterned wiring layer is disposed on the aforementioned surface. The stop material is filled in the trench. The wafer is disposed on the flexible substrate and located in the wafer bonding region and electrically connected to the patterned wiring layer. The encapsulant is formed between the wafer and the flexible substrate and around the wafer, wherein the encapsulant is in contact with the stopper material, and the side edges of the encapsulant are on the stopper material.

本發明提出一種可撓性線路載板,其包括可撓性基材、圖案化線路層以及擋止材料。可撓性基材具有表面以及位於前述表面的晶片接合區與溝渠,且溝渠環繞於晶片接合區之外。圖案化線路層配置於前述表面上。擋止材料填充於溝渠中。 The present invention provides a flexible wiring carrier that includes a flexible substrate, a patterned wiring layer, and a stop material. The flexible substrate has a surface and a wafer bond region and trench on the surface, and the trench surrounds the wafer bond region. The patterned wiring layer is disposed on the aforementioned surface. The stop material is filled in the trench.

在本發明的一實施例中,上述的溝渠具有內緣與外緣。封裝膠體的側緣位於內緣與外緣之間。 In an embodiment of the invention, the trench has an inner edge and an outer edge. The side edges of the encapsulant are located between the inner and outer edges.

在本發明的一實施例中,上述的溝渠的外緣與相鄰的晶片的側緣之間的最短距離介於100微米與800微米之間。 In an embodiment of the invention, the shortest distance between the outer edge of the trench and the side edge of the adjacent wafer is between 100 microns and 800 microns.

在本發明的一實施例中,上述的溝渠的寬度介於10微米與50微米之間。 In an embodiment of the invention, the trench has a width between 10 microns and 50 microns.

在本發明的一實施例中,上述的擋止材料暴露於溝渠的上表面與可撓性基材的表面為共平面。 In an embodiment of the invention, the stopper material exposed to the upper surface of the trench is coplanar with the surface of the flexible substrate.

在本發明的一實施例中,上述的可撓性線路載板更包括防焊層。防焊層配置於可撓性基材上,局部覆蓋圖案化線路層並 定義出開窗區,其中晶片接合區與溝渠位於開窗區內。 In an embodiment of the invention, the flexible circuit carrier further includes a solder resist layer. The solder resist layer is disposed on the flexible substrate to partially cover the patterned circuit layer and A windowing zone is defined in which the wafer land and the trench are located in the windowing zone.

在本發明的一實施例中,上述的擋止材料的材質與防焊層的材質相同。 In an embodiment of the invention, the material of the stopper material is the same as the material of the solder resist layer.

在本發明的一實施例中,上述的圖案化線路層包括多個引腳。各個引腳包括內引腳與連接前述內引腳之外引腳。內引腳通過擋止材料以延伸至晶片接合區內,而與晶片電性連接。 In an embodiment of the invention, the patterned circuit layer includes a plurality of pins. Each pin includes an inner pin and a pin connected to the aforementioned inner pin. The inner lead is electrically connected to the wafer by a stopper material extending into the wafer bonding region.

在本發明的一實施例中,上述的擋止材料包括防焊油墨、乾膜防焊油墨(Dry Film Solder Mask,DFSM)或液態感光型防焊油墨。 In an embodiment of the invention, the stopper material includes a solder resist ink, a dry film solder mask ink (DFSM) or a liquid photosensitive solder resist ink.

在本發明的一實施例中,上述的溝渠的外緣與相鄰的晶片接合區的側緣之間的最短距離介於100微米與800微米之間。 In an embodiment of the invention, the shortest distance between the outer edge of the trench and the side edge of the adjacent wafer bonding region is between 100 microns and 800 microns.

基於上述,本發明的薄膜覆晶封裝結構包括可撓性線路載板,而可撓性線路載板的可撓性基材具有溝渠,其中溝渠環繞於可撓性基材上的晶片接合區之外,且填充有擋止材料。其中,在使晶片與圖案化線路層電性連接後,需形成封裝膠體於晶片與可撓性基材之間以及晶片之四周,以保護晶片與圖案化線路層之間的電性接點。基於封裝膠體之流動性,在以點膠針頭繞行晶片之周邊以將封裝膠體注入晶片的主動表面與可撓性基材的表面之間所構成的空間時,封裝膠體亦會朝向遠離晶片的方向(即溝渠方向)流動。 Based on the above, the film flip chip package structure of the present invention comprises a flexible circuit carrier, and the flexible substrate of the flexible circuit carrier has a trench, wherein the trench surrounds the wafer bonding region on the flexible substrate. In addition, it is filled with a stopper material. After the wafer is electrically connected to the patterned circuit layer, an encapsulant is formed between the wafer and the flexible substrate and around the wafer to protect the electrical contact between the wafer and the patterned wiring layer. Based on the fluidity of the encapsulant, when the encapsulation is wound around the periphery of the wafer to inject the encapsulant into the space formed between the active surface of the wafer and the surface of the flexible substrate, the encapsulant will also face away from the wafer. The direction (ie the direction of the ditch) flows.

由於本發明的封裝膠體在擋止材料上的流動速度小於封裝膠體在可撓性基材上的流動速度,也就是說,封裝膠體與擋止 材料之間的表面附著力大於封裝膠體與可撓性基材之間的表面附著力,藉以在封裝膠體流動至溝渠而與擋止材料相接觸時,封裝膠體會受到擋止材料的限制而逐漸停止流動,以令其側緣止於擋止材料上。在此,本發明可藉由溝渠的外緣定義出封裝膠體的塗佈範圍的容許公差上限,及溝渠的內緣定義出封裝膠體的塗佈範圍的容許公差下限,換言之,藉由設置溝渠於可撓性基板上,並於溝渠內填充擋止材料,可使封裝膠體的塗佈範圍落在預期的尺寸及規定的容許公差值內,而不會超出於溝渠的外緣以外的可撓性基材的其他區域,可有效縮減封裝膠體的塗佈區域,以利於後續應用中薄膜覆晶封裝結構於鄰近晶片處的彎折,且符合產品的應用需求。 Since the flow rate of the encapsulant of the present invention on the stopper material is smaller than the flow speed of the encapsulant on the flexible substrate, that is, the encapsulant and the stopper The surface adhesion between the materials is greater than the surface adhesion between the encapsulant and the flexible substrate, so that when the encapsulant flows to the trench and contacts the stopper material, the encapsulant is gradually restricted by the stopper material. Stop the flow so that its side edges stop on the stop material. Here, the present invention can define the upper limit of the tolerance of the coating range of the encapsulant by the outer edge of the trench, and the inner edge of the trench defines the lower tolerance limit of the coating range of the encapsulant, in other words, by providing a ditch. The flexible substrate is filled with a stopper material in the trench, so that the coating range of the encapsulant can fall within the expected size and the specified tolerance value without being flexible beyond the outer edge of the trench. Other areas of the substrate can effectively reduce the coating area of the encapsulant to facilitate the bending of the film flip chip structure adjacent to the wafer in subsequent applications, and meet the application requirements of the product.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧薄膜覆晶封裝結構 100‧‧‧film flip chip package structure

110‧‧‧可撓性線路載板 110‧‧‧Flexible line carrier

111‧‧‧可撓性基材 111‧‧‧Flexible substrate

111a‧‧‧表面 111a‧‧‧ surface

111b‧‧‧晶片接合區 111b‧‧‧ wafer junction area

111c‧‧‧溝渠 111c‧‧‧ Ditch

112‧‧‧圖案化線路層 112‧‧‧ patterned circuit layer

112a‧‧‧引腳 112a‧‧‧ pin

112b‧‧‧內引腳 112b‧‧‧ inner pin

112c‧‧‧外引腳 112c‧‧‧External pin

113‧‧‧擋止材料 113‧‧‧stop material

113a‧‧‧上表面 113a‧‧‧ upper surface

114‧‧‧防焊層 114‧‧‧ solder mask

114a‧‧‧開窗區 114a‧‧‧window area

120‧‧‧晶片 120‧‧‧ wafer

121‧‧‧主動表面 121‧‧‧Active surface

122‧‧‧凸塊 122‧‧‧Bumps

130‧‧‧封裝膠體 130‧‧‧Package colloid

D‧‧‧距離 D‧‧‧Distance

G‧‧‧最短距離 G‧‧‧Short distance

OE‧‧‧外緣 OE‧‧‧ outer edge

IE‧‧‧內緣 IE‧‧‧ inner edge

W‧‧‧寬度 W‧‧‧Width

圖1是本發明一實施例的薄膜覆晶封裝結構的俯視圖。 1 is a top plan view of a thin film flip chip package structure in accordance with an embodiment of the present invention.

圖2是圖1的薄膜覆晶封裝結構沿著剖線A-A的剖面示意圖。 2 is a cross-sectional view of the thin film flip chip package structure of FIG. 1 taken along line A-A.

圖1是本發明一實施例的薄膜覆晶封裝結構的俯視圖。圖2是圖1的薄膜覆晶封裝結構沿著剖線A-A的剖面示意圖,其 中圖1未繪示封裝膠體130以清楚表示與便於說明。請參考圖1與圖2,在本實施例中,薄膜覆晶封裝結構100包括可撓性線路載板110、晶片120以及封裝膠體130,其中可撓性線路載板110包括可撓性基材111、圖案化線路層112以及擋止材料113。 1 is a top plan view of a thin film flip chip package structure in accordance with an embodiment of the present invention. 2 is a cross-sectional view of the thin film flip chip package structure of FIG. 1 taken along line A-A, The encapsulant 130 is not shown in FIG. 1 for clarity and convenience of description. Referring to FIG. 1 and FIG. 2 , in the embodiment, the thin film flip chip package structure 100 includes a flexible circuit carrier 110 , a wafer 120 , and an encapsulant 130 , wherein the flexible circuit carrier 110 includes a flexible substrate 111. Patterning the wiring layer 112 and the stopper material 113.

可撓性基材111具有表面111a以及位於表面111a的晶片接合區111b與溝渠111c,且溝渠111c環繞於晶片接合區111b之外。通常而言,可撓性基材111的材質可包括聚醯亞胺(Polyimide,PI)、聚乙烯對苯二甲酸酯(polyethylene terephthalate,PET)、聚醚(polyethersulfone,PES)、碳酸脂(polycarbonate,PC)或其他適合的可撓性材料,而溝渠111c例如是以光微影蝕刻的方式形成於可撓性基材111上,其寬度W可介於10微米至15微米之間。 The flexible substrate 111 has a surface 111a and a wafer bonding region 111b and a trench 111c on the surface 111a, and the trench 111c surrounds the wafer bonding region 111b. Generally, the material of the flexible substrate 111 may include polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), and carbonate ( Polycarbonate, PC) or other suitable flexible material, and the trench 111c is formed on the flexible substrate 111, for example, by photolithographic etching, and has a width W of between 10 micrometers and 15 micrometers.

圖案化線路層112配置於表面111a上,其中圖案化線路層112可包括多個引腳112a,其中這些引腳112a的材質例如是銅、銀、錫、鋁、鎳、金或其他合適的導電金屬。另一方面,擋止材料113填充於溝渠111c中,而晶片120配置於可撓性基材111上且位於晶片接合區111b內,並與圖案化線路層112電性連接。此處,晶片120例如是指紋辨識感測晶片,但本發明不限於此。詳言之,各個引腳112a包括內引腳112b與連接內引腳112b之外引腳112c,晶片120具有位於其主動表面121上的多個凸塊122(圖2示意地繪示出兩個),其中主動表面121面對表面111a。在本實施例中,這些內引腳112b通過擋止材料113以延伸至晶片接合區111b內,而各個內引腳112b與對應的凸塊122例如是藉由熱壓方 式而相互共晶接合,以達成圖案化線路層112與晶片120之間的電性連接。 The patterned wiring layer 112 is disposed on the surface 111a, wherein the patterned wiring layer 112 may include a plurality of pins 112a, wherein the materials of the pins 112a are, for example, copper, silver, tin, aluminum, nickel, gold or other suitable conductive metal. On the other hand, the stopper material 113 is filled in the trench 111c, and the wafer 120 is disposed on the flexible substrate 111 and located in the wafer bonding region 111b, and is electrically connected to the patterned wiring layer 112. Here, the wafer 120 is, for example, a fingerprint recognition sensing wafer, but the present invention is not limited thereto. In detail, each pin 112a includes an inner pin 112b and a pin 112c other than the inner pin 112b. The wafer 120 has a plurality of bumps 122 on its active surface 121 (Fig. 2 schematically shows two ), wherein the active surface 121 faces the surface 111a. In the present embodiment, the inner leads 112b are extended by the blocking material 113 into the wafer bonding region 111b, and the inner leads 112b and the corresponding bumps 122 are, for example, by hot pressing. The eutectic bonding is performed to achieve an electrical connection between the patterned wiring layer 112 and the wafer 120.

在本實施例中,可撓性線路載板110更包括防焊層114。 防焊層114配置於可撓性基材111上,以局部覆蓋圖案化線路層112並定義出開窗區114a,其中晶片接合區111b與溝渠111c位於開窗區114a內,而開窗區114a暴露出內引腳112b。具體而言,防焊層114可用以保護引腳112a,亦即在防焊層114的覆蓋下,可防止引腳112a因刮傷、汙染而短路或斷路。此外,擋止材料113的材質為絕緣材質,且與防焊層114可為相同材質所構成,例如是防焊油墨、乾膜防焊油墨或液態感光型防焊油墨,但本發明不限於此。在其他實施例中,擋止材料113與防焊層114亦可分別由不同材質所構成。 In the present embodiment, the flexible circuit carrier 110 further includes a solder resist layer 114. The solder resist layer 114 is disposed on the flexible substrate 111 to partially cover the patterned wiring layer 112 and defines a window opening region 114a, wherein the wafer bonding region 111b and the trench 111c are located in the window opening region 114a, and the window opening region 114a The inner pin 112b is exposed. Specifically, the solder resist layer 114 can be used to protect the leads 112a, that is, under the coverage of the solder resist layer 114, to prevent the pins 112a from being short-circuited or broken due to scratches or contamination. In addition, the material of the stopper material 113 is made of an insulating material, and the solder resist layer 114 may be made of the same material, for example, solder resist ink, dry film solder resist ink or liquid photosensitive solder resist ink, but the invention is not limited thereto. . In other embodiments, the stopper material 113 and the solder resist layer 114 may also be made of different materials.

如圖2所示,溝渠111c具有內緣IE與外緣OE,其中溝渠111c的外緣OE與相鄰的晶片120的側緣之間的最短距離G約介於100微米與800微米之間,且較佳地是介於100微米與300微米之間。在此,晶片接合區111b例如是由晶片120在可撓性基材111上的正投影區域所定義,溝渠111c的外緣OE與相鄰的晶片接合區111b的側緣之間的最短距離實質上與前述最短距離G一致,亦即介於100微米與800微米之間,且較佳地是介於100微米與300微米之間。另一方面,擋止材料113暴露於溝渠111c的上表面113a是與可撓性基材111的表面111a為共平面,如此可避免通過擋止材料113上方的內引腳112b產生彎曲,以維持引腳 112a的平面一致性,進而降低引腳112a於製程中斷裂的機率。 As shown in FIG. 2, the trench 111c has an inner edge IE and an outer edge OE, wherein the shortest distance G between the outer edge OE of the trench 111c and the side edge of the adjacent wafer 120 is between about 100 micrometers and 800 micrometers. And preferably between 100 microns and 300 microns. Here, the wafer bonding region 111b is defined, for example, by the orthographic projection area of the wafer 120 on the flexible substrate 111, and the shortest distance between the outer edge OE of the trench 111c and the side edge of the adjacent wafer bonding region 111b is substantially The upper surface is coincident with the aforementioned shortest distance G, that is, between 100 micrometers and 800 micrometers, and preferably between 100 micrometers and 300 micrometers. On the other hand, the upper surface 113a of the stopper material 113 exposed to the trench 111c is coplanar with the surface 111a of the flexible substrate 111, so that the bending of the inner lead 112b above the stopper material 113 can be avoided to maintain Pin The planar uniformity of 112a, which in turn reduces the probability of pin 112a breaking during the process.

封裝膠體130形成於晶片120的主動表面121與可撓性基材111的表面111a之間,並且包覆晶片120之四周,用以保護各個內引腳112b與對應的凸塊122之間所構成的電性接點。通常而言,封裝膠體130為底部填充膠(underfill material),而其材質例如是環氧樹脂或其他高分子材料,並且為了使封裝膠體130能順利填滿晶片120與可撓性基材111之間的微小空間,薄膜覆晶封裝結構100通常是利用點膠的方式,以點膠針頭繞行晶片120之周邊以將封裝膠體130注入,其中封裝膠體130會藉由毛細現象而自晶片120之周邊往內部延伸而填滿晶片120的主動表面121與可撓性基材111的表面111a之間所構成的空間,而為使封裝膠體130能順利流動,未固化的封裝膠體130必須具有相當程度的流動性。然而,基於封裝膠體130之流動性,使其亦會朝向遠離晶片120的方向流動,也就是朝向溝渠111c的方向流動,並與溝渠111c內的擋止材料113相接觸。 The encapsulant 130 is formed between the active surface 121 of the wafer 120 and the surface 111a of the flexible substrate 111, and covers the periphery of the wafer 120 to protect between the inner leads 112b and the corresponding bumps 122. Electrical contacts. Generally, the encapsulant 130 is an underfill material, such as an epoxy resin or other polymer material, and the encapsulant 130 can smoothly fill the wafer 120 and the flexible substrate 111. In a small space, the film flip-chip package structure 100 is usually by means of dispensing, and the periphery of the wafer 120 is wound around the wafer 120 to dispense the encapsulant 130, wherein the encapsulant 130 is caused by the capillary phenomenon from the wafer 120. The periphery extends to the inside to fill the space formed between the active surface 121 of the wafer 120 and the surface 111a of the flexible substrate 111. To enable the encapsulant 130 to flow smoothly, the uncured encapsulant 130 must have a considerable degree. Mobility. However, based on the fluidity of the encapsulant 130, it also flows in a direction away from the wafer 120, that is, in the direction toward the trench 111c, and is in contact with the stopper material 113 in the trench 111c.

在本實施例中,無論是常溫或高溫環境下,封裝膠體130在擋止材料113的上表面113a上的流動速度均是小於封裝膠體130在可撓性基材111的表面111a上的流動速度,也就是說,封裝膠體130與擋止材料113之間的表面附著力大於封裝膠體130與可撓性基材111之間的表面附著力,藉以讓未固化的封裝膠體130在流動至溝渠111c時,可被擋止於擋止材料113上。 In the present embodiment, the flow velocity of the encapsulant 130 on the upper surface 113a of the stopper material 113 is smaller than the flow velocity of the encapsulant 130 on the surface 111a of the flexible substrate 111, whether in a normal temperature or high temperature environment. That is, the surface adhesion between the encapsulant 130 and the stopper material 113 is greater than the surface adhesion between the encapsulant 130 and the flexible substrate 111, so that the uncured encapsulant 130 flows to the trench 111c. At this time, it can be blocked on the stopper material 113.

簡言之,在形成封裝膠體130於可撓性基材111上的過 程中,朝向溝渠111c流動的封裝膠體130可受到擋止材料113的限制,而不會溢流至溝渠111c之外的可撓性基材111上的其他區域。因此,固化後的封裝膠體130的側緣可位於擋止材料113上,且位於溝渠111c的內緣IE與外緣OE之間,以便於後續製程的進行。也就是說,可藉由溝渠111c的外緣OE定義出封裝膠體130的塗佈範圍的容許公差值的上限,及溝渠111c的內緣IE定義出封裝膠體130的塗佈範圍的容許公差值的下限,故在以點膠針頭繞行晶片120之周邊以將封裝膠體130注入後,封裝膠體130的側緣將會至少超出內緣IE,並以不超出外緣OE為原則。 In short, the formation of the encapsulant 130 on the flexible substrate 111 has been During the process, the encapsulant 130 flowing toward the trench 111c can be restricted by the stopper material 113 without overflowing to other regions on the flexible substrate 111 outside the trench 111c. Therefore, the side edge of the encapsulated encapsulant 130 can be located on the stopper material 113 and located between the inner edge IE and the outer edge OE of the trench 111c to facilitate subsequent processes. That is, the upper limit of the tolerance value of the coating range of the encapsulant 130 can be defined by the outer edge OE of the trench 111c, and the inner edge IE of the trench 111c defines the tolerance of the coating range of the encapsulant 130. The lower limit of the value, so after the periphery of the wafer 120 is wound with the dispensing needle to inject the encapsulant 130, the side edge of the encapsulant 130 will at least exceed the inner edge IE, and the principle of not exceeding the outer edge OE.

另一方面,當封裝膠體130流動超出內緣IE時,基於封裝膠體130與擋止材料113之間的表面附著力大於封裝膠體130與可撓性基材111之間的表面附著力的緣故,封裝膠體130會受到擋止材料113的限制而逐漸停止流動,以令其側緣止於擋止材料113上。此時,封裝膠體130的側緣與內緣IE的距離D例如是小於等於6微米,且較佳是小於3微米。 On the other hand, when the encapsulant 130 flows beyond the inner edge IE, the surface adhesion between the encapsulant 130 and the stopper material 113 is greater than the surface adhesion between the encapsulant 130 and the flexible substrate 111, The encapsulant 130 is gradually restricted from flowing by the stopper material 113 so that its side edge terminates on the stopper material 113. At this time, the distance D between the side edge of the encapsulant 130 and the inner edge IE is, for example, 6 μm or less, and preferably less than 3 μm.

舉例而言,薄膜覆晶封裝結構100可彎折以進行後續之應用,例如指紋辨識感測器等,其中薄膜覆晶封裝結構100彎折處的位置可能相當接近晶片120。然而,固化後的封裝膠體130會阻礙可撓性基板110的彎折,因此在產品微型化的需求下,封裝膠體130的塗佈範圍也相應地需縮小。由於本發明的薄膜覆晶封裝結構100可透過溝渠111c和擋止材料113控制封裝膠體130的塗佈範圍,並使封裝膠體130的塗佈範圍落在容許公差值的上 限與下限之間,因此固化後的封裝膠體130可被有效縮減,從而符合產品的應用需求。 For example, the thin film flip chip package structure 100 can be bent for subsequent applications, such as a fingerprint sensor or the like, wherein the position of the bend of the film flip chip package structure 100 may be relatively close to the wafer 120. However, the encapsulated colloid 130 after curing may hinder the bending of the flexible substrate 110, so that the coating range of the encapsulant 130 is correspondingly reduced in response to the demand for miniaturization of the product. Since the film flip chip package structure 100 of the present invention can control the coating range of the encapsulant 130 through the trench 111c and the stopper material 113, and the coating range of the encapsulant 130 falls within the tolerance value. Between the limit and the lower limit, the encapsulated encapsulant 130 after curing can be effectively reduced to meet the application requirements of the product.

綜上所述,本發明的薄膜覆晶封裝結構包括可撓性線路載板,而可撓性線路載板的可撓性基材具有溝渠,其中溝渠環繞於可撓性基材上的晶片接合區之外,且填充有擋止材料。其中,在使晶片與圖案化線路層電性連接後,需形成封裝膠體於晶片與可撓性基材之間以及晶片之四周,以保護晶片與圖案化線路層之間的電性接點。基於封裝膠體之流動性,在以點膠針頭繞行晶片之周邊以將封裝膠體注入晶片的主動表面與可撓性基材的表面之間所構成的空間時,封裝膠體亦會朝向遠離晶片的方向(即溝渠方向)流動。 In summary, the thin film flip chip package structure of the present invention comprises a flexible circuit carrier, and the flexible substrate of the flexible circuit carrier has a trench, wherein the trench surrounds the wafer on the flexible substrate Outside the zone, it is filled with a stop material. After the wafer is electrically connected to the patterned circuit layer, an encapsulant is formed between the wafer and the flexible substrate and around the wafer to protect the electrical contact between the wafer and the patterned wiring layer. Based on the fluidity of the encapsulant, when the encapsulation is wound around the periphery of the wafer to inject the encapsulant into the space formed between the active surface of the wafer and the surface of the flexible substrate, the encapsulant will also face away from the wafer. The direction (ie the direction of the ditch) flows.

由於本發明的封裝膠體在擋止材料上的流動速度小於封裝膠體在可撓性基材上的流動速度,也就是說,封裝膠體與擋止材料之間的表面附著力大於封裝膠體與可撓性基材之間的表面附著力,藉以在封裝膠體流動至溝渠而與擋止材料相接觸時,封裝膠體會受到擋止材料的限制而逐漸停止流動,以令其側緣止於擋止材料上。在此,本發明可藉由溝渠的外緣定義出封裝膠體的塗佈範圍的容許公差上限,及溝渠的內緣定義出封裝膠體的塗佈範圍的容許公差下限,換言之,藉由設置溝渠於可撓性基板上,並於溝渠內填充擋止材料,可使封裝膠體的塗佈範圍落在預期的尺寸及規定的容許公差值內,而不會超出於溝渠的外緣以外的可撓性基材的其他區域,可有效縮減封裝膠體的塗佈區域,以利於後 續應用中薄膜覆晶封裝結構於鄰近晶片處的彎折,且符合產品的應用需求。 Since the flow rate of the encapsulant of the present invention on the stopper material is smaller than the flow speed of the encapsulant on the flexible substrate, that is, the surface adhesion between the encapsulant and the stopper is greater than that of the encapsulant and the flexible The surface adhesion between the substrates, so that when the encapsulant flows to the trench and contacts the stopper material, the encapsulant is restricted by the stopper material and gradually stops flowing so that the side edges stop at the stopper material. on. Here, the present invention can define the upper limit of the tolerance of the coating range of the encapsulant by the outer edge of the trench, and the inner edge of the trench defines the lower tolerance limit of the coating range of the encapsulant, in other words, by providing a ditch. The flexible substrate is filled with a stopper material in the trench, so that the coating range of the encapsulant can fall within the expected size and the specified tolerance value without being flexible beyond the outer edge of the trench. Other areas of the substrate can effectively reduce the coating area of the encapsulant to facilitate In the continued application, the film flip-chip package structure is bent at the adjacent wafer and meets the application requirements of the product.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧薄膜覆晶封裝結構 100‧‧‧film flip chip package structure

110‧‧‧可撓性線路載板 110‧‧‧Flexible line carrier

111‧‧‧可撓性基材 111‧‧‧Flexible substrate

111a‧‧‧表面 111a‧‧‧ surface

111c‧‧‧溝渠 111c‧‧‧ Ditch

112a‧‧‧引腳 112a‧‧‧ pin

112b‧‧‧內引腳 112b‧‧‧ inner pin

112c‧‧‧外引腳 112c‧‧‧External pin

113‧‧‧擋止材料 113‧‧‧stop material

113a‧‧‧上表面 113a‧‧‧ upper surface

114‧‧‧防焊層 114‧‧‧ solder mask

114a‧‧‧開窗區 114a‧‧‧window area

120‧‧‧晶片 120‧‧‧ wafer

121‧‧‧主動表面 121‧‧‧Active surface

122‧‧‧凸塊 122‧‧‧Bumps

130‧‧‧封裝膠體 130‧‧‧Package colloid

D‧‧‧距離 D‧‧‧Distance

G‧‧‧最短距離 G‧‧‧Short distance

OE‧‧‧外緣 OE‧‧‧ outer edge

IE‧‧‧內緣 IE‧‧‧ inner edge

W‧‧‧寬度 W‧‧‧Width

Claims (17)

一種薄膜覆晶封裝結構,包括:一可撓性線路載板,包括:一可撓性基材,具有一表面以及位於該表面的一晶片接合區與一溝渠,且該溝渠環繞於該晶片接合區之外;一圖案化線路層,配置於該表面上;以及一擋止材料,填充於該溝渠中;一晶片,配置於該可撓性基材上且位於該晶片接合區內,並與該圖案化線路層電性連接;以及一封裝膠體,形成於該晶片與該可撓性基材之間以及該晶片之四周,其中該封裝膠體與該擋止材料接觸,且該封裝膠體的側緣位於該擋止材料上。 A film flip chip package structure comprising: a flexible circuit carrier, comprising: a flexible substrate having a surface and a wafer bonding region and a trench on the surface, and the trench is surrounded by the wafer bonding a patterned circuit layer disposed on the surface; and a stopper material filled in the trench; a wafer disposed on the flexible substrate and located in the wafer bonding region, and The patterned circuit layer is electrically connected; and an encapsulant is formed between the wafer and the flexible substrate and around the wafer, wherein the encapsulant is in contact with the blocking material, and the side of the encapsulant The edge is on the stop material. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該溝渠具有一內緣與一外緣,該封裝膠體的該側緣位於該內緣與該外緣之間。 The film flip-chip package structure of claim 1, wherein the trench has an inner edge and an outer edge, and the side edge of the encapsulant is located between the inner edge and the outer edge. 如申請專利範圍第2項所述的薄膜覆晶封裝結構,其中該溝渠的該外緣與相鄰的該晶片的一側緣之間的最短距離介於100微米與800微米之間。 The thin film flip chip package structure of claim 2, wherein a shortest distance between the outer edge of the trench and a side edge of the adjacent wafer is between 100 micrometers and 800 micrometers. 如申請專利範圍第3項所述的薄膜覆晶封裝結構,其中該溝渠的寬度介於10微米與50微米之間。 The thin film flip chip package structure of claim 3, wherein the trench has a width of between 10 micrometers and 50 micrometers. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該擋止材料暴露於該溝渠的一上表面與該可撓性基材的該表面為共 平面。 The film flip chip package structure according to claim 1, wherein the stopper material is exposed to an upper surface of the trench and the surface of the flexible substrate is flat. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該可撓性線路載板更包括:一防焊層,配置於該可撓性基材上,該防焊層局部覆蓋該圖案化線路層並定義出一開窗區,其中該晶片接合區與該溝渠位於該開窗區內。 The thin film flip chip package structure of claim 1, wherein the flexible circuit carrier further comprises: a solder resist layer disposed on the flexible substrate, the solder resist layer partially covering the pattern The circuit layer is defined and defines an open window region, wherein the wafer bonding region and the trench are located in the window opening region. 如申請專利範圍第6項所述的薄膜覆晶封裝結構,其中該擋止材料的材質與該防焊層的材質相同。 The film flip chip package structure according to claim 6, wherein the material of the stopper material is the same as the material of the solder resist layer. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該圖案化線路層包括多個引腳,各該引腳包括一內引腳與連接該內引腳之一外引腳,該內引腳通過該擋止材料以延伸至該晶片接合區內,而與該晶片電性連接。 The thin film flip chip package structure of claim 1, wherein the patterned circuit layer comprises a plurality of pins, each of the pins comprising an inner pin and an outer pin connecting the inner pin, The inner lead is electrically connected to the wafer by the stopper material extending into the wafer bonding region. 如申請專利範圍第1項所述的薄膜覆晶封裝結構,其中該擋止材料包括防焊油墨、乾膜防焊油墨或液態感光型防焊油墨。 The film flip chip package structure according to claim 1, wherein the stopper material comprises a solder resist ink, a dry film solder resist ink or a liquid photosensitive solder resist ink. 一種可撓性線路載板,包括:一可撓性基材,具有一表面以及位於該表面的一晶片接合區與一溝渠,且該溝渠環繞於該晶片接合區之外;一圖案化線路層,配置於該表面上;以及一擋止材料,填充於該溝渠中。 A flexible circuit carrier comprising: a flexible substrate having a surface and a die bond region and a trench on the surface, the trench surrounding the die bond region; a patterned circuit layer Disposed on the surface; and a stopper material filled in the trench. 如申請專利範圍第10項所述的可撓性線路載板,其中該擋止材料暴露於該溝渠的一上表面與該可撓性基材的該表面為共平面。 The flexible circuit carrier of claim 10, wherein the upper surface of the barrier material exposed to the trench is coplanar with the surface of the flexible substrate. 如申請專利範圍第10項所述的可撓性線路載板,更包括:一防焊層,配置於該可撓性基材上,該防焊層局部覆蓋該圖案化線路層並定義出一開窗區,其中該晶片接合區與該溝渠位於該開窗區內。 The flexible circuit carrier of claim 10, further comprising: a solder resist layer disposed on the flexible substrate, the solder resist layer partially covering the patterned circuit layer and defining a a window opening region, wherein the wafer bonding region and the trench are located in the window opening region. 如申請專利範圍第12項所述的可撓性線路載板,其中該擋止材料的材質與該防焊層的材質相同。 The flexible circuit carrier according to claim 12, wherein the material of the stopper material is the same as the material of the solder resist layer. 如申請專利範圍第10項所述的可撓性線路載板,其中該圖案化線路層包括多個引腳,各該引腳包括一內引腳與連接該內引腳之一外引腳,該內引腳通過該擋止材料以延伸至該晶片接合區內。 The flexible circuit carrier of claim 10, wherein the patterned circuit layer comprises a plurality of pins, each of the pins comprising an inner pin and an outer pin connecting the inner pin. The inner lead passes through the stop material to extend into the wafer bond area. 如申請專利範圍第10項所述的可撓性線路載板,其中該擋止材料包括防焊油墨、乾膜防焊油墨或液態感光型防焊油墨。 The flexible circuit carrier as claimed in claim 10, wherein the blocking material comprises a solder resist ink, a dry film solder resist ink or a liquid photosensitive solder resist ink. 如申請專利範圍第10項所述的可撓性線路載板,其中該溝渠的一外緣與相鄰的該晶片接合區的一側緣之間的最短距離介於100微米與800微米之間。 The flexible circuit carrier of claim 10, wherein a shortest distance between an outer edge of the trench and a side edge of the adjacent wafer bonding region is between 100 micrometers and 800 micrometers. . 如申請專利範圍第16項所述的可撓性線路載板,其中該溝渠的寬度介於10微米與50微米之間。 The flexible circuit carrier of claim 16, wherein the trench has a width between 10 microns and 50 microns.
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