TWI440102B - Molding method of multiple substrates between flat matrixes for semiconductor packages - Google Patents

Molding method of multiple substrates between flat matrixes for semiconductor packages Download PDF

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TWI440102B
TWI440102B TW098133487A TW98133487A TWI440102B TW I440102 B TWI440102 B TW I440102B TW 098133487 A TW098133487 A TW 098133487A TW 98133487 A TW98133487 A TW 98133487A TW I440102 B TWI440102 B TW I440102B
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substrate
molding
mold
semiconductor package
wafers
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TW098133487A
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TW201113957A (en
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Wen Jeng Fan
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

半導體封裝之多基板平板模封方法Multi-substrate flat panel sealing method for semiconductor package

本發明係有關於半導體裝置，特別係有關於一種半導體封裝之多基板平板模封方法。The present invention relates to a semiconductor device, and more particularly to a multi-substrate plate molding method for a semiconductor package.

目前半導體產業中，對於大量生產而言，通常是藉由轉移製模(Transfer Molding)的封裝方式具有最佳的成本-績效比。在轉移製模之製程中，以人工或自動送料方式將如導線架或印刷電路板等基板送入模具的模穴之後，密閉模具並施以高壓夾持。再將預熱(軟化)的粒狀封裝塑封材料藉由注入器送入模穴中，並填滿整個模穴中，經過烘烤固化之後即完成半導體元件之封裝。In the current semiconductor industry, for mass production, it is usually the best cost-to-performance ratio by means of Transfer Molding. In the process of transferring the mold, the substrate such as the lead frame or the printed circuit board is fed into the mold cavity of the mold by manual or automatic feeding, and the mold is sealed and subjected to high pressure clamping. The preheated (softened) granular encapsulated molding material is then fed into the cavity by the injector and filled into the entire cavity, and the package of the semiconductor component is completed after baking and curing.

在習知的半導體封裝之MAP模封方法中，上下模具的設計並不相同。如第1A圖所示，其係將一基板120固定於一平板狀下模具112上。該基板120上已設置有複數個晶片151，並藉由複數個銲線153電性連接該些晶片151與該基板120。通常該基板120係為模封陣列加工(Mold Array Process,MAP)之基板。接著，壓合一具有模穴111A之上模具111於該下模具112，使該些晶片151能容置於該上模具111與該下模具112所形成之一模封空間140內。在封膠製程中，將溫度與壓力控制在一定條件之下，藉由一注入器161將一模封化合物160灌入至該模封空間140，以密封保護該些晶片151。如第1B圖所示，移除該上模具111與該下模具112之後，再將該模封化合物160固化。最後，如第1C圖所示，切割該模封化合物160以形成複數個封裝體162。包含切割後之基板120、該封裝體162、該些晶片151即構成為一獨立的半導體封裝構造180。在轉移製模時，該模封化合物160未固化之前的前驅物會在該模封空間140內部流動。當該些晶片151至該模穴111A之縱向間隙與該些晶片151之間的橫向間隙兩者差異過大，會造成模流速度無法平衡，故必須在該些晶片151與該模穴111A之間預留足夠的空間A，以避免該些晶片151上模流速度過低。一旦受到模流不平衡之影響，會導致該模封化合物160在充填時包覆氣體而在該些晶片151上殘留空洞(mold void)，嚴重影響了封裝品質。In the conventional MAP molding method for semiconductor packages, the design of the upper and lower molds is not the same. As shown in FIG. 1A, a substrate 120 is fixed to a flat lower mold 112. A plurality of wafers 151 are disposed on the substrate 120, and the wafers 151 and the substrate 120 are electrically connected by a plurality of bonding wires 153. Usually, the substrate 120 is a substrate of a Mold Array Process (MAP). Then, the mold 111 having the cavity 111A is pressed into the lower mold 112 so that the wafers 151 can be accommodated in the molding space 140 formed by the upper mold 111 and the lower mold 112. In the encapsulation process, the temperature and pressure are controlled under certain conditions, and a mold compound 160 is poured into the mold cavity 140 by an injector 161 to seal and protect the wafers 151. As shown in FIG. 1B, after the upper mold 111 and the lower mold 112 are removed, the mold compound 160 is cured. Finally, as shown in FIG. 1C, the mold compound 160 is diced to form a plurality of packages 162. The diced substrate 120, the package 162, and the 151 are formed as a separate semiconductor package structure 180. At the time of transfer molding, the precursor before the molding compound 160 is uncured may flow inside the molding space 140. When the difference between the longitudinal gaps of the wafers 151 to the cavity 111A and the lateral gaps between the wafers 151 is too large, the mold flow velocity cannot be balanced, so it is necessary to be between the wafers 151 and the cavity 111A. Sufficient space A is reserved to avoid the mold flow speed on the wafers 151 being too low. Once affected by the mold flow imbalance, the mold compound 160 is coated with gas at the time of filling to leave a void on the wafers 151, which seriously affects the package quality.

因此，以往的封膠方法為了預留該空間A以維持模流平衡，所以需要較厚的封裝厚度，並且該模穴111A需要有一相當深度，不利於清模。如果要降低模穴深度以薄化封裝厚度，只能選擇更晶圓薄化的晶片，但會增加了製造成本。Therefore, in the conventional encapsulation method, in order to reserve the space A to maintain the mold flow balance, a thicker package thickness is required, and the cavity 111A needs to have a considerable depth, which is disadvantageous for clearing the mold. If the cavity depth is to be reduced to thin the package thickness, only wafers that are thinner than wafers can be selected, but the manufacturing cost is increased.

為了解決上述之問題，本發明之主要目的係在於一種半導體封裝之多基板平板模封方法，在上下平板模各設置基板，基板上在晶片之間的縱向間隙可作為共用模流通道。藉此，能夠薄化封裝高度或者能堆疊更多晶片，並維持良好模流平衡。In order to solve the above problems, the main object of the present invention is a multi-substrate flat panel molding method for a semiconductor package. A substrate is disposed on each of the upper and lower flat molds, and a longitudinal gap between the wafers on the substrate can be used as a common mold flow passage. Thereby, the package height can be thinned or more wafers can be stacked, and a good mold flow balance can be maintained.

本發明之次一目的係在於提供一種半導體封裝之多基板平板模封方法，毋須使用習知有模穴的上模具，具有模具設計簡化與容易清模之功效。A second object of the present invention is to provide a multi-substrate flat-plate molding method for a semiconductor package, which does not require the use of a conventional mold-clamping upper mold, and has the advantages of simplified mold design and easy mold clearing.

本發明之再一目的係在於提供一種半導體封裝之多基板平板模封方法，能夠提高封膠效率，並輔助切割封膠之對準與定位。A further object of the present invention is to provide a multi-substrate flat panel molding method for a semiconductor package, which can improve the sealing efficiency and assist in the alignment and positioning of the cutting encapsulant.

本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種半導體封裝之多基板平板模封方法，主要包含有以下步驟：提供一上平板模、一下平板模以及一中間模。設置一第一基板於該上平板模與設置一第二基板於該下平板模，以在該第一基板與該第二基板之間形成一模封空間，並且該第一基板與該第二基板在該模封空間內各設置有複數個第一晶片與複數個第二晶片。形成一模封化合物於該模封空間內，同時結合該第一基板與該第二基板，以密封該些第一晶片與該些第二晶片。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a multi-substrate flat panel molding method for a semiconductor package, which mainly comprises the following steps: providing an upper flat mold, a lower flat mold and an intermediate mold. Forming a first substrate on the upper plate mold and a second substrate on the lower plate mold to form a molding space between the first substrate and the second substrate, and the first substrate and the second substrate The substrate is provided with a plurality of first wafers and a plurality of second wafers in the molding space. Forming a molding compound in the molding space while bonding the first substrate and the second substrate to seal the first wafer and the second wafers.

本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

在前述之半導體封裝之多基板平板模封方法中，可另包含之步驟為：沿著該第一基板與該第二基板之間的平行等分面，對切該模封化合物，以分離該第一基板與該第二基板。In the multi-substrate flat panel molding method of the semiconductor package described above, the method further includes the steps of: cutting the mold compound along a parallel bisector between the first substrate and the second substrate to separate the a first substrate and the second substrate.

在前述之半導體封裝之多基板平板模封方法中，該模封化合物之側邊在該平行等分面處可形成有一切割導槽。In the multi-substrate flat panel molding method of the semiconductor package described above, the side of the mold compound may be formed with a cutting guide at the parallel bisector.

在前述之半導體封裝之多基板平板模封方法中，該第一基板與該第二基板皆可具有一模封區，內可包含複數個矩陣排列之封裝基板單元。In the multi-substrate flat panel molding method of the semiconductor package, the first substrate and the second substrate may each have a mold-sealing region, and may include a plurality of matrix-arranged package substrate units.

在前述之半導體封裝之多基板平板模封方法中，可另包含有一單體化分離步驟，以使該第一基板與該第二基板之封裝基板單元分離，以形成複數個半導體封裝構造。In the multi-substrate flat panel molding method of the semiconductor package described above, a singulation separation step may be further included to separate the first substrate from the package substrate unit of the second substrate to form a plurality of semiconductor package structures.

在前述之半導體封裝之多基板平板模封方法中，該些第一晶片與該些第二晶片之設置係可為多晶片堆疊型態。In the multi-substrate flat panel molding method of the semiconductor package, the first wafers and the second wafers may be in a multi-wafer stack configuration.

在前述之半導體封裝之多基板平板模封方法中，在該第一基板與該第二基板之設置步驟中，該些第一晶片與該些第二晶片之間可供該模封化合物形成之縱向間隙不小於相鄰該些第一晶片之間可供該模封化合物形成之水平間隙。In the above-mentioned multi-substrate flat-plate molding method of the semiconductor package, in the step of disposing the first substrate and the second substrate, the molding compound is formed between the first wafer and the second wafers. The longitudinal gap is not less than a horizontal gap between the adjacent first wafers for forming the mold compound.

在前述之半導體封裝之多基板平板模封方法中，該模封化合物的形成方法係可為轉移模製(transfer molding)。In the multi-substrate flat panel molding method of the semiconductor package described above, the method of forming the mold compound may be transfer molding.

在前述之半導體封裝之多基板平板模封方法中，該模封化合物的形成方法係可為壓縮模製(compression molding)。In the multi-substrate flat panel molding method of the semiconductor package described above, the method of forming the mold compound may be compression molding.

由以上技術方案可以看出，本發明之半導體封裝之多基板平板模封方法，有以下優點與功效：It can be seen from the above technical solutions that the multi-substrate flat panel sealing method of the semiconductor package of the present invention has the following advantages and effects:

一、可藉由在第一基板與第二基板之間形成一模封空間與形成模封化合物於模封空間內作為其中一技術手段，由於模封化合物可同時結合第一基板與第二基板，以密封第一晶片與第二晶片，故可水平對切模封化合物，以形成上下基板間的多個封裝體。因此，能夠薄化封裝高度或者堆疊更多晶片，並維持良好模流平衡。1. Forming a molding space between the first substrate and the second substrate and forming a molding compound in the molding space as one of the technical means, since the molding compound can simultaneously bond the first substrate and the second substrate In order to seal the first wafer and the second wafer, the compound can be horizontally diced to form a plurality of packages between the upper and lower substrates. Therefore, it is possible to thin the package height or stack more wafers and maintain a good mold flow balance.

二、可藉由提供上平板模、下平板模以及中間模作為其中一技術手段，由於是使用無模穴之平板模，毋須使用習知有模穴的上模具，具有模具設計簡化與容易清模之功效。Secondly, by providing the upper plate die, the lower plate die and the intermediate die as one of the technical means, since the flat die is used without a cavity, it is not necessary to use the upper die which has a conventional cavity, and the die design is simplified and easy to clear. The effect of the model.

三、可藉由在第一基板與第二基板之間形成一模封空間、形成模封化合物於模封空間內與在第一基板與第二基板之間的平行等分面處形成有切割導槽作為其中一技術手段，除了能夠提高封膠效率外，更可以輔助切割封膠之對準與定位。3. Forming a cut at a parallel bisector between the first substrate and the second substrate by forming a molding space between the first substrate and the second substrate, forming a molding compound in the molding space, and forming a molding compound As one of the technical means, the guide groove can not only improve the sealing efficiency, but also assist the alignment and positioning of the cutting sealant.

以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

依據本發明之第一具體實施例，一種半導體封裝之多基板平板模封方法舉例說明於第2圖之流程方塊圖與第3A至3H圖之元件截面示意圖。該半導體封裝之多基板平板模封方法根據第2圖，主要包含以下步驟：「提供上平板模、下平板模與中間模」之步驟1、「設置第一基板於上平板模與設置第二基板於下平板模以形成模封空間」之步驟2以及「形成模封化合物於模封空間內」之步驟3，而在步驟3之後的「水平對切模封化合物」步驟4可依需要執行，詳細步驟請參閱第3A至3H圖，說明如下所示。According to a first embodiment of the present invention, a multi-substrate flat panel molding method for a semiconductor package is illustrated in a flow block diagram of FIG. 2 and a cross-sectional view of an element of FIGS. 3A to 3H. According to FIG. 2, the multi-substrate flat panel molding method of the semiconductor package mainly comprises the following steps: “providing an upper flat mold, a lower flat mold and an intermediate mold”, “setting a first substrate on the upper flat mold and setting a second” Step 2 of the substrate is formed in the lower plate mold to form the molding space" and the step 3 of "forming the molding compound in the molding space", and the step 4 of "horizontal tangential sealing compound" after the step 3 can be performed as needed For detailed steps, please refer to Figures 3A to 3H, as explained below.

首先，執行步驟1。請參閱第3A圖所示，提供一上平板模211、一下平板模212以及一中間模213。在本實施例中，該上平板模211與該下平板模212皆為無模穴或低模穴之平面模板。因此，不需要使用習知有模穴的上模具，具有模具設計簡化與容易清模之功效。在一較佳實施例中，由於該上平板模211、該下平板模212與該中間模213係可為組合式模具，除了上述具有容易清理之功效外，亦非常便於製程中架設使用。First, go to step 1. Referring to FIG. 3A, an upper plate die 211, a lower plate die 212, and an intermediate die 213 are provided. In the embodiment, the upper plate die 211 and the lower plate die 212 are planar templates of no cavity or low cavity. Therefore, it is not necessary to use an upper mold having a conventional cavity, and the mold design is simplified and the mold is easily cleaned. In a preferred embodiment, since the upper flat die 211, the lower flat die 212 and the intermediate die 213 can be combined molds, in addition to the above-mentioned functions of easy cleaning, it is also very convenient for erection in the process.

執行步驟2。請參閱第3B與3C圖所示，執行一架模操作。首先，如第3B圖所示，設置一第一基板220於該上平板模211與設置一第二基板230於該下平板模212。在本實施例中，該第二基板230與該第一基板220係可供模封陣列加工(Mold Array Process,MAP)製造之晶片載體，並具有相同功能與尺寸。更具體地，如第4圖所示，該第一基板220可具有一模封區221，內包含複數個矩陣排列之封裝基板單元223(即圖中虛線所分割的區域)。此外，該第一基板220可另具有一預留區222，以便於脫模之後的轉移與拿持。在本實施例中，該第一基板220與該第二基板230係可為實質相同之元件，故該第二基板230可亦具有模封區、內包含之封裝基板單元與預留區。Go to step 2. Refer to Figures 3B and 3C for a single die operation. First, as shown in FIG. 3B, a first substrate 220 is disposed on the upper plate die 211 and a second substrate 230 is disposed on the lower plate die 212. In this embodiment, the second substrate 230 and the first substrate 220 are available for a die carrier fabricated by Mold Array Process (MAP) and have the same functions and dimensions. More specifically, as shown in FIG. 4, the first substrate 220 may have a molding region 221 containing a plurality of matrix-arranged package substrate units 223 (ie, regions divided by broken lines in the drawing). In addition, the first substrate 220 may further have a reserved area 222 to facilitate transfer and holding after demolding. In this embodiment, the first substrate 220 and the second substrate 230 can be substantially identical components. Therefore, the second substrate 230 can also have a molding area, a package substrate unit and a reserved area included therein.

接著，如第3C圖所示，架設該中間模213並使其對準於該些模封區，再壓合該上平板模211至該中間模213並對齊該下平板模212，以在該第一基板220與該第二基板230之間形成一模封空間240，並且該第一基板220與該第二基板230在該模封空間240內各設置有複數個第一晶片251與複數個第二晶片252。在本實施例中，該些第一晶片251與該些第二晶片252之設置係可為多晶片堆疊型態，並藉由複數個銲線253、254分別電性連接於該第一基板220與該第二基板230。更進一步地，該上平板模211與該下平板模212在該第一基板220與該第二基板230之間形成一共用之模封空間240，並能提供足夠的模流通道，以利後續模封製程進行。詳細而言，再如第3C圖所示，該些第一晶片251、該些第二晶片252與該些銲線253、254係完全容置於該上平板模211、該下平板模212與該中間模213所構成之該模封空間240內。Next, as shown in FIG. 3C, the intermediate mold 213 is erected and aligned to the mold sealing regions, and the upper flat mold 211 is pressed to the intermediate mold 213 and aligned with the lower flat mold 212. A molding space 240 is formed between the first substrate 220 and the second substrate 230, and the first substrate 220 and the second substrate 230 are respectively disposed in the molding space 240 with a plurality of first wafers 251 and a plurality of Second wafer 252. In this embodiment, the first wafers 251 and the second wafers 252 are disposed in a multi-wafer stack, and are electrically connected to the first substrate 220 by a plurality of bonding wires 253 and 254, respectively. And the second substrate 230. Further, the upper plate die 211 and the lower plate die 212 form a common molding space 240 between the first substrate 220 and the second substrate 230, and can provide sufficient mold flow passage for subsequent operation. The molding process is carried out. In detail, as shown in FIG. 3C, the first wafer 251, the second wafers 252, and the bonding wires 253 and 254 are completely accommodated in the upper flat die 211 and the lower flat die 212. The intermediate mold 213 is formed in the mold cavity 240.

執行步驟3。請參閱第3D與3E圖所示，執行一模封操作。首先，如第3D圖所示，藉由一注入器261，執行一注膠操作。在本實施例中，由該注入器261提供之模封化合物經由流道(runner，圖中未繪出)流入至該中間模213之鑄澆口214。接著，如第3E圖所示，注膠完成後，形成一模封化合物260於該模封空間240(即被該模封化合物260所填滿之區域)內，同時結合該第一基板220與該第二基板230，以密封該些第一晶片251與該些第二晶片252。在本實施例中，該模封化合物260的形成方法係可為轉移模製(transfer molding)。特別是，如第3E圖所示，在該第一基板220與該第二基板230之設置步驟中，該些第一晶片251與該些第二晶片252之間可供該模封化合物260形成之縱向間隙S1不小於相鄰該些第一晶片251之間可供該模封化合物260形成之水平間隙S2之二分之一，故能使得整體的封裝體積更為縮小。此外，位於該第一基板220之最外側之該些第一晶片251至該中間模213之距離係約相同於水平間隙S2之二分之一，以使該些第一晶片251在切割之後能具有相同尺寸。由於縱向間隙S1是被該第一基板220與該第二基板230所共用之模流通道，故縱向間隙S1與水平間隙S2處的模流速度得以平衡。更具體而言，在上下基板晶片之間的縱向間隙S1可相當於習知的基板上晶片至上模具之空間A。Go to step 3. Refer to Figures 3D and 3E to perform a molding operation. First, as shown in Fig. 3D, a glue injection operation is performed by an injector 261. In the present embodiment, the molding compound supplied from the injector 261 flows into the gate 214 of the intermediate mold 213 via a runner (not shown). Next, as shown in FIG. 3E, after the filling is completed, a molding compound 260 is formed in the molding space 240 (ie, the region filled by the molding compound 260), and simultaneously bonding the first substrate 220 with The second substrate 230 is configured to seal the first wafer 251 and the second wafers 252. In the present embodiment, the molding compound 260 is formed by a transfer molding method. In particular, as shown in FIG. 3E, in the step of disposing the first substrate 220 and the second substrate 230, the molding compound 260 is formed between the first wafer 251 and the second wafers 252. The longitudinal gap S1 is not less than one-half of the horizontal gap S2 between the adjacent first wafers 251 for forming the mold compound 260, so that the overall package volume can be further reduced. In addition, the distance from the first wafer 251 to the intermediate mold 213 at the outermost side of the first substrate 220 is about the same as one-half of the horizontal gap S2, so that the first wafers 251 can be cut after cutting. Have the same size. Since the longitudinal gap S1 is a mold flow path shared by the first substrate 220 and the second substrate 230, the mold flow velocity at the longitudinal gap S1 and the horizontal gap S2 is balanced. More specifically, the longitudinal gap S1 between the upper and lower substrate wafers may correspond to the space A of the wafer on the substrate to the upper mold.

在脫模之後，可執行步驟4。請參閱第3F與3G圖所示，藉由一水平切割刀具271，沿著該第一基板220與該第二基板230之間的平行等分面241，對切該模封化合物260，以分離該第一基板220與該第二基板230。首先，如第3F圖所示，該平行等分面241係為一虛線表示之假想平面，並非實際設置於該封模化合物260內。接著，如第3G圖所示，以該水平切割刀具271，沿著該平行等分面241對切該模封化合物260，以使該第一基板220與該第二基板230各自分離。由於該上平板模211與該下平板模212之間形成之共用模封空間240，使得該第一基板220與該第二基板230同時被該模封化合物260所覆蓋。因此，在該水平切割刀具271對切該模封化合物260之後，會使該模封化合物260分離而分別形成於該些第一晶片251與該些第二晶片252上，並在該些第一晶片251與該些第二晶片252上會形成有一封膠厚度。詳細而言，該厚度係約等於或小於上述縱向間隙S1的二分之一(視切割間隙而定)。After demolding, step 4 can be performed. Referring to FIGS. 3F and 3G, the die-cut compound 260 is cut along the parallel bisector 241 between the first substrate 220 and the second substrate 230 by a horizontal cutting tool 271 to separate The first substrate 220 and the second substrate 230. First, as shown in FIG. 3F, the parallel bisector 241 is an imaginary plane indicated by a broken line, and is not actually disposed in the mold compound 260. Next, as shown in FIG. 3G, the cutter 271 is cut at the horizontal direction, and the mold compound 260 is cut along the parallel bisector 241 so that the first substrate 220 and the second substrate 230 are separated from each other. Due to the common molding space 240 formed between the upper plate die 211 and the lower plate die 212, the first substrate 220 and the second substrate 230 are simultaneously covered by the molding compound 260. Therefore, after the horizontal cutting tool 271 cuts the molding compound 260, the molding compound 260 is separated and formed on the first wafer 251 and the second wafer 252, respectively, and An adhesive thickness is formed on the wafer 251 and the second wafers 252. In detail, the thickness is approximately equal to or less than one-half of the longitudinal gap S1 (depending on the cutting gap).

請再參閱第3H圖所示，藉由一垂直切割刀具272，執行一單體化分離步驟，以使該第一基板220與該第二基板230之封裝基板單元223分離，以形成複數個半導體封裝構造280，並且將該模封化合物260分割為複數個封裝體262。在第3H圖中，僅繪示出其中之一形成於該封裝基板單元223上之半導體封裝構造280作為代表。在一較佳實施例中，上述水平對切模封化合物之步驟，可實施在單體化分離步驟之前或之後，或可不實施。倘若不實施水平對切的步驟僅實施單體化分離步驟，對應之第一基板220與第二基板230之封裝基板單元223仍被單體化分離後的封裝體262結合。在單體化分離步驟之後，可另以軟板等連接器(圖中未繪出)電性連接該第一基板220與該第二基板230共用同一模封化合物260之封裝基板單元223。Referring to FIG. 3H, a vertical separation step 272 is performed to separate the first substrate 220 from the package substrate unit 223 of the second substrate 230 to form a plurality of semiconductors. The package structure 280 is packaged and the mold compound 260 is divided into a plurality of packages 262. In the 3H drawing, only the semiconductor package structure 280 in which one of them is formed on the package substrate unit 223 is shown as a representative. In a preferred embodiment, the step of leveling the die-cut compound may be performed before or after the singulation step or may not be performed. If the step of dicing is not performed, only the singulation step is performed, and the corresponding substrate substrate 223 of the first substrate 220 and the second substrate 230 are still combined by the singulated package 262. After the singulation step, the package substrate unit 223 of the same mold compound 260 is electrically connected to the first substrate 220 and the second substrate 230 by a connector such as a flexible board (not shown).

在本發明中，利用形成一模封空間於第一基板與第二基板之間，再形成模封化合物於共用模封空間內作為其中一技術手段，故能夠薄化封裝高度，並維持良好模流平衡。請參閱第5圖所示，其繪示本發明與習知之模封高度比較示意圖，可由圖中看出習知的封裝體在晶片上厚度T1明顯大於本發明之封裝體在晶片上厚度T2許多。詳細而言，習知的半導體封裝構造180之該厚度T1係由該些晶片151至該模穴111A之空間A(如第1圖所示)所決定，故厚度T1約等於該空間A之高度。更進一步地，由於本發明係對切該模封化合物260，故使得該半導體封裝構造280之封裝體在晶片上厚度T2約等於或小於上述縱向間隙S1(如第3E圖所示)的二分之一。又縱向間隙S1可相當於該空間A之高度。因此，請再參閱第4圖所示，在相當的模流平衡條件下，經由本發明之模封方法進行模封之後，本發明之半導體封裝構造280之封裝體在晶片上厚度T2與習知的半導體封裝構造180之封裝體在晶片上厚度T1做比較，會明顯降低了一高度差H，在相同晶片堆疊數量或晶片高度的限制下，本實施例的整體封裝厚度可比習知構造更為降低，亦能提高封膠效率。此外，毋須配置晶圓薄化的晶片，也能提供充足的模流空間。In the present invention, by forming a molding space between the first substrate and the second substrate, and forming a molding compound in the common molding space as one of the technical means, the package height can be thinned and the good mode can be maintained. Flow balance. Please refer to FIG. 5, which is a schematic diagram showing the comparison between the present invention and the conventional mold height. It can be seen from the figure that the thickness T1 of the conventional package on the wafer is significantly larger than the thickness T2 of the package of the present invention on the wafer. . In detail, the thickness T1 of the conventional semiconductor package structure 180 is determined by the space A of the wafer 151 to the cavity 111A (as shown in FIG. 1), so the thickness T1 is approximately equal to the height of the space A. . Further, since the present invention is directed to the die-cut compound 260, the thickness of the package of the semiconductor package structure 280 on the wafer is approximately equal to or smaller than the longitudinal gap S1 (as shown in FIG. 3E). one. Further, the longitudinal gap S1 may correspond to the height of the space A. Therefore, referring to FIG. 4, the thickness of the package of the semiconductor package structure 280 of the present invention on the wafer T2 and the conventional ones after molding by the molding method of the present invention under the condition of equivalent mold flow balance Comparing the thickness T1 of the package of the semiconductor package structure 180 on the wafer, the height difference H is significantly reduced. Under the limitation of the same number of wafer stacks or the height of the wafer, the overall package thickness of the embodiment can be more than the conventional structure. Lowering can also improve the sealing efficiency. In addition, there is no need to configure wafers with thin wafers to provide sufficient mold flow space.

依據本發明之第二具體實施例，另一種半導體封裝之多基板平板模封方法舉例說明於第6A與6B圖之元件截面示意圖。其中與第一實施例相同的主要元件將以相同符號標示，不再詳予贅述。According to a second embodiment of the present invention, a multi-substrate flat panel molding method for another semiconductor package is illustrated in a cross-sectional view of the elements of FIGS. 6A and 6B. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail.

在本實施例中，該模封化合物260的形成方法係可為壓縮模製(compression molding)。詳細而言，如第6A圖所示，利用形成於該中間模213之突出部，以在該模封化合物260之側邊在該平行等分面241處形成有一切割導槽363。之後，完成模封操作，並移除模具。再如第6B圖所示，藉由該水平切割刀具271執行一切割操作，以分離該第一基板220與該第二基板230。在水平對切該模封化合物260之步驟中，本發明能藉由該切割導槽363之設置，輔助該水平切割刀具271之對準與定位，在製程中能夠直接沿著該切割導槽363順勢對切，加快了整體的製程效率。In the present embodiment, the method of forming the mold compound 260 may be compression molding. In detail, as shown in FIG. 6A, a protruding portion formed at the intermediate mold 213 is used to form a cutting guide groove 363 at the side of the mold compound 260 at the parallel bisector 241. After that, the molding operation is completed and the mold is removed. Further, as shown in FIG. 6B, a cutting operation is performed by the horizontal cutting blade 271 to separate the first substrate 220 from the second substrate 230. In the step of horizontally cutting the mold compound 260, the present invention can assist the alignment and positioning of the horizontal cutting tool 271 by the setting of the cutting guide 363, and can directly follow the cutting guide 363 during the process. Taking advantage of the trend, speeding up the overall process efficiency.

依據本發明之第三具體實施例，另一種半導體封裝之多基板平板模封方法舉例說明於第7A與7B圖之元件截面示意圖。其中與第一實施例相同的主要元件將以相同符號標示，不再詳予贅述。According to a third embodiment of the present invention, another multi-substrate flat panel molding method for a semiconductor package is illustrated in a cross-sectional view of the elements of FIGS. 7A and 7B. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail.

在本實施例中，如第7A圖所示，該第一基板220與該第二基板230比習知結構皆增加設置了至少一第一晶片251與第二晶片252。更具體地，該中間模213之尺寸須在該第一基板220與該第二基板230之設置步驟中，維持充足的縱向間隙S1(如同第一實施例)，以保持模流平衡。再如第7B圖所示，同樣係沿著該平行等分面241，水平對切該模封化合物260，以分離該第一基板220與該第二基板230。之後，再經由與第一實施例相同之單體化分離步驟，形成各自獨立的半導體封裝構造380(如第8圖所示)。In this embodiment, as shown in FIG. 7A, the first substrate 220 and the second substrate 230 are further provided with at least one first wafer 251 and second wafer 252. More specifically, the size of the intermediate mold 213 is such that in the step of disposing the first substrate 220 and the second substrate 230, a sufficient longitudinal gap S1 (as in the first embodiment) is maintained to maintain the mold flow balance. Further, as shown in FIG. 7B, the molding compound 260 is horizontally cut along the parallel bisector 241 to separate the first substrate 220 and the second substrate 230. Thereafter, a separate semiconductor package structure 380 (shown in FIG. 8) is formed via the same singulation separation step as in the first embodiment.

請參閱第8圖所示，其繪示本發明第三實施例與習知之封裝高度相同時所堆疊之晶片數量比較示意圖，可由圖中看出在本發明與習知的封裝厚度相同與保持相同模流平衡之情況下，本發明能堆疊了較多的晶片。詳細而言，這是因為習知的半導體封裝構造180為了要維持模流平衡，必須要留有足夠的空間A(如第1圖所示)，而使得該半導體封裝構造180之厚度無法降低。一旦增加晶片堆疊的數量，便會降低該空間A而發生模流無法平衡之情形。然而，在本發明中，由於該第一基板220與該第二基板230係可共用形成於該些第一晶片251與該些第二晶片252間的模封化合物260，故在水平對切該模封化合物260之後，封裝體在晶片上厚度T2會自然地減少至約為該縱向間隙S1(如第7A圖所示)的一半或視切割情況而更小。也就是說，藉由上述方法所製成之半導體封裝構造380可在與習知的半導體封裝構造180具有相同厚度之情況下，堆疊數量更多的晶片，以增進整體的性能或容量。Please refer to FIG. 8 , which is a schematic diagram showing the comparison of the number of wafers stacked in the third embodiment of the present invention, which can be the same as the conventional package thickness. In the case of mold flow balance, the present invention can stack more wafers. In detail, this is because the conventional semiconductor package structure 180 must have sufficient space A (as shown in FIG. 1) in order to maintain the mold flow balance, so that the thickness of the semiconductor package structure 180 cannot be reduced. Once the number of wafer stacks is increased, the space A is lowered and the mold flow is unbalanced. However, in the present invention, since the first substrate 220 and the second substrate 230 can share the molding compound 260 formed between the first wafer 251 and the second wafers 252, the horizontal alignment is performed. After molding compound 260, the thickness T2 of the package on the wafer is naturally reduced to about half of the longitudinal gap S1 (as shown in Figure 7A) or smaller depending on the cutting condition. That is, the semiconductor package structure 380 fabricated by the above method can stack a larger number of wafers with the same thickness as the conventional semiconductor package structure 180 to enhance overall performance or capacity.

以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

步驟1　提供上平板模、下平板模與中間模Step 1 Provide upper plate die, lower plate die and intermediate die

步驟2　設置第一基板於上平板模與設置第二基板於下平板模以形成模封空間Step 2: setting the first substrate on the upper plate mold and the second substrate on the lower plate mold to form a molding space

步驟3　形成模封化合物於模封空間內Step 3 Form a molding compound in the mold cavity

步驟4　水平對切模封化合物Step 4 Horizontally cutting the compound

S1．．．縱向間隙S1. . . Vertical clearance

S2．．．水平間隙S2. . . Horizontal gap

T1．．．習知封裝體在晶片上厚度T1. . . Conventional package thickness on the wafer

T2．．．本發明之封裝體在晶片上厚度T2. . . The thickness of the package of the present invention on the wafer

H．．．高度差H. . . Height difference

A．．．晶片上至模穴之空間A. . . Space on the wafer to the cavity

111．．．上模具111. . . Upper mold

111A．．．模穴111A. . . Cavity

112．．．下模具112. . . Lower mold

120．．．基板120. . . Substrate

140．．．模封空間140. . . Molded space

151．．．晶片151. . . Wafer

153．．．銲線153. . . Welding wire

160．．．模封化合物160. . . Molding compound

161．．．注入器161. . . Injector

162．．．封裝體162. . . Package

180．．．半導體封裝構造180. . . Semiconductor package construction

211．．．上平板模211. . . Upper plate die

212．．．下平板模212. . . Lower plate mode

213．．．中間模213. . . Intermediate mode

214．．．鑄澆口214. . . Cast gate

220．．．第一基板220. . . First substrate

221．．．模封區221. . . Molded area

222．．．預留區222. . . Reserved area

223．．．封裝基板單元223. . . Package substrate unit

230．．．第二基板230. . . Second substrate

240．．．模封空間240. . . Molded space

241．．．平行等分面241. . . Parallel bisector

251．．．第一晶片251. . . First wafer

252．．．第二晶片252. . . Second chip

253．．．銲線253. . . Welding wire

254．．．銲線254. . . Welding wire

260．．．模封化合物260. . . Molding compound

261．．．注入器261. . . Injector

262．．．封裝體262. . . Package

271．．．水平切割刀具271. . . Horizontal cutting tool

272．．．垂直切割刀具272. . . Vertical cutting tool

280．．．半導體封裝構造280. . . Semiconductor package construction

363．．．切割導槽363. . . Cutting guide

380．．．半導體封裝構造380. . . Semiconductor package construction

第1A至1C圖：為習知的一種半導體封裝之模封方法之元件截面示意圖，1A to 1C are schematic cross-sectional views of components of a conventional semiconductor package molding method,

第2圖：依據本發明之第一具體實施例的一種半導體封裝之多基板平板模封方法之流程方塊圖。2 is a flow block diagram of a multi-substrate flat panel molding method for a semiconductor package in accordance with a first embodiment of the present invention.

第3A至3H圖：依據本發明之第一具體實施例的半導體封裝之多基板平板模封方法之元件截面示意圖。3A to 3H are cross-sectional views showing the components of the multi-substrate flat panel molding method of the semiconductor package in accordance with the first embodiment of the present invention.

第4圖：依據本發明之第一具體實施例的半導體封裝之多基板平板模封方法繪示其基板與封裝基板單元之上視圖。4 is a top view of a substrate and package substrate unit of a semiconductor package according to a first embodiment of the present invention.

第5圖：依據本發明之第一具體實施例的半導體封裝之多基板平板模封方法繪示其所製成之封裝構造與習知之封裝高度比較示意圖。FIG. 5 is a schematic diagram showing a comparison between a package structure made by a multi-substrate and a package height of a semiconductor package according to a first embodiment of the present invention.

第6A與6B圖：依據本發明之第二具體實施例的半導體封裝之多基板平板模封方法之元件截面示意圖。6A and 6B are cross-sectional views showing the components of the multi-substrate flat panel molding method of the semiconductor package in accordance with the second embodiment of the present invention.

第7A與7B圖：依據本發明之第三具體實施例的半導體封裝之多基板平板模封方法之元件截面示意圖。7A and 7B are cross-sectional views showing the components of the multi-substrate flat panel molding method of the semiconductor package in accordance with the third embodiment of the present invention.

第8圖：依據本發明之第三具體實施例的半導體封裝之多基板平板模封方法繪示其與習知之封裝高度相同時所堆疊之晶片數量比較示意圖。Figure 8 is a schematic diagram showing the comparison of the number of wafers stacked when the multi-substrate flat-plate molding method of the semiconductor package according to the third embodiment of the present invention is the same as the conventional package height.

S1．．．縱向間隙S1. . . Vertical clearance

S2．．．水平間隙S2. . . Horizontal gap

211．．．上平板模211. . . Upper plate die

212．．．下平板模212. . . Lower plate mode

213．．．中間模213. . . Intermediate mode

220．．．第一基板220. . . First substrate

230．．．第二基板230. . . Second substrate

251．．．第一晶片251. . . First wafer

252．．．第二晶片252. . . Second chip

253．．．銲線253. . . Welding wire

254．．．銲線254. . . Welding wire

260．．．模封化合物260. . . Molding compound

261．．．注入器261. . . Injector

Claims (10)

一種半導體封裝之多基板平板模封方法，包含：提供一上平板模、一下平板模以及一中間模；設置一第一基板於該上平板模與設置一第二基板於該下平板模，以在該第一基板與該第二基板之間形成一模封空間，並且該第一基板與該第二基板在該模封空間內各設置有複數個第一晶片與複數個第二晶片；形成一模封化合物於該模封空間內，同時結合該第一基板與該第二基板，以密封該些第一晶片與該些第二晶片；以及沿著該第一基板與該第二基板之間的平行等分面，對切該模封化合物，以分離該第一基板與該第二基板。 A multi-substrate flat panel molding method for a semiconductor package, comprising: providing an upper plate die, a lower plate die and an intermediate die; and providing a first substrate on the upper plate die and a second substrate on the lower plate die, Forming a molding space between the first substrate and the second substrate, and the first substrate and the second substrate are respectively provided with a plurality of first wafers and a plurality of second wafers in the molding space; forming a molding compound is disposed in the molding space, and simultaneously bonding the first substrate and the second substrate to seal the first wafer and the second wafer; and along the first substrate and the second substrate The parallel bisector, the die-cut compound is cut to separate the first substrate from the second substrate. 根據申請專利範圍第1項所述之半導體封裝之多基板平板模封方法，其中該模封化合物之側邊在該平行等分面處形成有一切割導槽。 A multi-substrate flat panel molding method for a semiconductor package according to claim 1, wherein a side of the mold compound is formed with a cutting guide at the parallel bisector. 根據申請專利範圍第1項所述之半導體封裝之多基板平板模封方法，其中該第一基板與該第二基板皆具有一模封區，內包含複數個矩陣排列之封裝基板單元。 The multi-substrate flat-plate molding method for a semiconductor package according to the first aspect of the invention, wherein the first substrate and the second substrate each have a mold-sealing region, and the package substrate unit comprises a plurality of matrix arrays. 根據申請專利範圍第3項所述之半導體封裝之多基板平板模封方法，另包含有一單體化分離步驟，以使該第一基板與該第二基板之封裝基板單元分離， 以形成複數個半導體封裝構造。 The multi-substrate flat panel molding method for a semiconductor package according to claim 3, further comprising a singulation separation step for separating the first substrate from the package substrate unit of the second substrate, To form a plurality of semiconductor package structures. 根據申請專利範圍第1項所述之半導體封裝之多基板平板模封方法，其中該些第一晶片與該些第二晶片之設置係為多晶片堆疊型態。 The multi-substrate flat panel molding method of the semiconductor package of claim 1, wherein the first wafers and the second wafers are arranged in a multi-wafer stack configuration. 根據申請專利範圍第1或5項所述之半導體封裝之多基板平板模封方法，其中在該第一基板與該第二基板之設置步驟中，該些第一晶片與該些第二晶片之間可供該模封化合物形成之縱向間隙不小於相鄰該些第一晶片之間可供該模封化合物形成之水平間隙之二分之一。 The multi-substrate flat panel molding method of the semiconductor package according to claim 1 or 5, wherein in the disposing step of the first substrate and the second substrate, the first wafer and the second wafers are The longitudinal gap that can be formed by the molding compound is not less than one-half of the horizontal gap between adjacent ones of the first wafers that can be formed by the molding compound. 根據申請專利範圍第1項所述之半導體封裝之多基板平板模封方法，其中該模封化合物的形成方法係為轉移模製(transfer molding)。 A multi-substrate flat panel molding method for a semiconductor package according to claim 1, wherein the molding compound is formed by transfer molding. 根據申請專利範圍第1項所述之半導體封裝之多基板平板模封方法，其中該模封化合物的形成方法係為壓縮模製(compression molding)。 A multi-substrate flat panel molding method for a semiconductor package according to claim 1, wherein the molding compound is formed by compression molding. 一種半導體封裝之多基板平板模封方法，包含：提供一上平板模、一下平板模以及一中間模；設置一第一基板於該上平板模與設置一第二基板於該下平板模，以在該第一基板與該第二基板之間形成一模封空間，並且該第一基板與該第二基板在該模封空間內各設置有複數個第一晶片與複數個第二晶片；以及形成一模封化合物於該模封空間內，同時結合該第 一基板與該第二基板，以密封該些第一晶片與該些第二晶片；其中在該第一基板與該第二基板之設置步驟中，該些第一晶片與該些第二晶片之間可供該模封化合物形成之縱向間隙不小於相鄰該些第一晶片之間可供該模封化合物形成之水平間隙之二分之一。 A multi-substrate flat panel molding method for a semiconductor package, comprising: providing an upper plate die, a lower plate die and an intermediate die; and providing a first substrate on the upper plate die and a second substrate on the lower plate die, Forming a molding space between the first substrate and the second substrate, and the first substrate and the second substrate are respectively provided with a plurality of first wafers and a plurality of second wafers in the molding space; Forming a molding compound in the molding space while combining the first a substrate and the second substrate to seal the first wafer and the second wafer; wherein in the step of disposing the first substrate and the second substrate, the first wafer and the second wafer The longitudinal gap that can be formed by the molding compound is not less than one-half of the horizontal gap between adjacent ones of the first wafers that can be formed by the molding compound. 一種半導體封裝之多基板平板模封方法，包含：提供一上平板模、一下平板模以及一中間模；同時設置一第一基板於該上平板模與設置一第二基板於該下平板模，以在該第一基板與該第二基板之間形成一在不同封裝構造之間的共用模封空間，並且該第一基板與該第二基板在該模封空間內各設置有複數個第一晶片與複數個第二晶片；形成一模封化合物於該模封空間內，同時結合該第一基板與該第二基板，以密封該些第一晶片與該些第二晶片；藉由一水平切割刀具，對切該模封化合物，以分離該第一基板與該第二基板；以及藉由一垂直切割刀具，執行一單體化分離步驟，以使該第一基板與該第二基板之複數個封裝基板單元分離，以形成複數個半導體封裝構造。 A multi-substrate flat panel molding method for a semiconductor package, comprising: providing an upper flat mold, a lower flat mold, and an intermediate mold; and simultaneously providing a first substrate on the upper flat mold and a second substrate on the lower flat mold; Forming a common molding space between the first substrate and the second substrate between different package structures, and the first substrate and the second substrate are respectively provided with a plurality of first in the molding space. And a plurality of second wafers; forming a molding compound in the molding space, simultaneously bonding the first substrate and the second substrate to seal the first wafer and the second wafer; Cutting the tool, cutting the mold compound to separate the first substrate and the second substrate; and performing a singulation separation step by a vertical cutting tool to make the first substrate and the second substrate A plurality of package substrate units are separated to form a plurality of semiconductor package structures.
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