JP2007081153A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2007081153A
JP2007081153A JP2005267387A JP2005267387A JP2007081153A JP 2007081153 A JP2007081153 A JP 2007081153A JP 2005267387 A JP2005267387 A JP 2005267387A JP 2005267387 A JP2005267387 A JP 2005267387A JP 2007081153 A JP2007081153 A JP 2007081153A
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resin
mold
resin injection
substrate
manufacturing
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Naotsugu Yasuda
直世 安田
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Renesas Technology Corp
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Renesas Technology Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of preventing the generation of surface voids. <P>SOLUTION: The manufacturing method includes a process for arraying a plurality of semiconductor chips 4 and 6 on a substrate 1; a process in which a mold 8 is put on the substrate 1, and resin is injected in a cavity 9 between the substrate 1 and the mold 8 so that a plurality of semiconductor chips 4 and 6 are collectively resin-sealed; and a process for cutting the substrate 1 and the resin into semiconductor chips 4 and 6. A resin injection gate 10 is formed for injecting the resin on one side of the mold 8. An air vent for degassing is formed on the side opposite to one side of the mold 8. The direction of injecting the resin is oriented toward a side where the air vent is formed from a side where the resin injection gate 10 is formed. The mold 8 comprises mold projections 8a, 8b, and 8c that extend downward in the resin injection path between the semiconductor chips 4 and 6 extending in the resin injecting direction outside a product region. The interval between the substrate 1 and the mold projections 8a, 8b, and 8c is shorter than the half of the maximum thickness of the resin. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、モールド・アレイ・パッケージ(mold array package 以下、MAP という。)による半導体装置の製造方法に関するものである。   The present invention relates to a method of manufacturing a semiconductor device using a mold array package (hereinafter referred to as MAP).

MAPによる半導体装置の製造方法は、基板上に複数の半導体チップを配列し、基板上に金型を被せ、基板と金型の間のキャビティに樹脂を注入して、複数の半導体チップを一括して樹脂封止した後に、基板及び樹脂を半導体チップ毎に切断して個別の半導体装置を製造する方法である(例えば、特許文献1、特許文献2参照)。   In the method of manufacturing a semiconductor device by MAP, a plurality of semiconductor chips are arranged on a substrate, a mold is placed on the substrate, a resin is injected into a cavity between the substrate and the mold, and the plurality of semiconductor chips are collectively collected. After the resin sealing, the substrate and the resin are cut for each semiconductor chip to manufacture individual semiconductor devices (see, for example, Patent Document 1 and Patent Document 2).

特開2002−110718号公報JP 2002-110718 A 特開2002−110721号公報JP 2002-110721 A 特開平5−136191号公報JP-A-5-136191

しかし、キャビティに樹脂を注入する際に、半導体チップ上を流れる樹脂の流動抵抗は大きく、半導体チップ間を流れる樹脂の流動抵抗は小さいため、樹脂の流動速度に差が生じて表面ボイドが発生するという問題があった。(例えば、特許文献2参照)また、特許文献3には、MAPに関する記載はないが、金型に設けた突起によって、半導体チップの周囲を流れる樹脂の流動抵抗を大きくすることで、半導体チップ上にボイドが発生するのを防ぐ技術に関する記載がある。近年の半導体装置は小型化、薄型化の傾向が顕著であり、樹脂封止部分においても、体積的な余裕は非常に小さくなっている。このように、小型化、薄型化された樹脂封止部を形成する金型に、樹脂の流れを制御するために、特許文献3に記載の様な突起を設けると、樹脂封止部内に封止される金ワイヤを露出させてしまう可能性があるなど、半導体装置の歩留まりを低下させる可能性がある。また、突起の大きさを小さくして、半導体装置の歩留まりに影響しない程度に制限すると、樹脂の流れを良好に制御できず、ボイドを確実に防ぐのが難しくなるという問題がある。   However, when the resin is injected into the cavity, the flow resistance of the resin flowing over the semiconductor chips is large, and the flow resistance of the resin flowing between the semiconductor chips is small, so that a difference occurs in the flow speed of the resin and surface voids are generated. There was a problem. (For example, refer to Patent Document 2) Although Patent Document 3 does not describe MAP, the flow resistance of the resin flowing around the semiconductor chip is increased by a protrusion provided on the mold, thereby increasing the resistance on the semiconductor chip. Describes a technique for preventing the generation of voids. In recent years, semiconductor devices are remarkably reduced in size and thickness, and the volume margin is very small even in the resin-encapsulated portion. As described above, when a mold as described in Patent Document 3 is provided on the mold for forming a resin sealing portion that is reduced in size and thickness, the resin sealing portion is sealed within the resin sealing portion. There is a possibility that the yield of the semiconductor device is lowered, such as the possibility of exposing the gold wire to be stopped. Further, if the size of the protrusions is reduced to a level that does not affect the yield of the semiconductor device, there is a problem that the resin flow cannot be controlled well and it is difficult to reliably prevent voids.

本発明は、上述のような課題を解決するためになされたもので、その目的は、小型化、薄型化された半導体装置においても、表面ボイドが発生するのを防ぐことができる半導体装置の製造方法を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to manufacture a semiconductor device that can prevent generation of surface voids even in a semiconductor device that is reduced in size and thickness. Get the method.

本発明に係る半導体装置の製造方法は、基板上に複数の半導体チップを配列する工程と、基板上に金型を被せ、基板と金型の間のキャビティに樹脂を注入して、複数の半導体チップを一括して樹脂封止する工程と、基板及び樹脂を半導体チップ毎に切断する工程とを有し、金型の一辺に樹脂を注入するための樹脂注入ゲートが形成され、金型の一辺に対向する辺に空気を抜くためのエアベントが形成され、樹脂注入ゲートが形成された辺からエアベントが形成された辺に向かう方向が樹脂注入方向であり、金型は、樹脂注入方向に沿って延在する半導体チップ間樹脂注入経路で、かつ製品領域外において、下方に伸びる金型突起を有し、金型突起と基板との間隔が、樹脂の最大の厚みの1/2より小さくなるようにする。本発明のその他の特徴は以下に明らかにする。   A method of manufacturing a semiconductor device according to the present invention includes: a step of arranging a plurality of semiconductor chips on a substrate; a mold is placed on the substrate; and a resin is injected into a cavity between the substrate and the mold; A step of resin-sealing the chips collectively and a step of cutting the substrate and the resin for each semiconductor chip, and forming a resin injection gate for injecting the resin into one side of the mold; An air vent for venting air is formed on the opposite side, the direction from the side where the resin injection gate is formed to the side where the air vent is formed is the resin injection direction, and the mold is along the resin injection direction. In the extended resin injection path between semiconductor chips and having a mold protrusion extending downward outside the product region, the distance between the mold protrusion and the substrate is smaller than 1/2 of the maximum thickness of the resin. To. Other features of the present invention will become apparent below.

本発明により、金型突起を設けて樹脂の流れを制御することで、表面ボイドが発生するのを防ぐことができる。   According to the present invention, it is possible to prevent occurrence of surface voids by providing mold protrusions and controlling the flow of resin.

実施の形態1.
以下、本発明の実施の形態1に係る半導体装置の製造方法について図面を参照しながら説明する。
Embodiment 1 FIG.
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.

まず、図1に示すように、基板1上に複数の半導体チップ4,6及びスペーサー5を配列する。ここで、各半導体チップ4,6及びスペーサー5を含む一定の領域が、後に製品となる製品領域3である。本実施の形態において、配線基板の封止部が形成される領域(参照番号)の大きさは37mm×50mmであり、製品領域3の大きさは、10mm×13mmである。   First, as shown in FIG. 1, a plurality of semiconductor chips 4 and 6 and a spacer 5 are arranged on a substrate 1. Here, a certain region including the semiconductor chips 4 and 6 and the spacer 5 is a product region 3 to be a product later. In the present embodiment, the size of the region (reference number) where the sealing portion of the wiring board is formed is 37 mm × 50 mm, and the size of the product region 3 is 10 mm × 13 mm.

図2は、半導体チップ4,6及びスペーサー5積層構造の一例を示す断面図であり、図3はその平面図である。本実施の形態においては、基板1上に積層された下段の半導体チップ4、スペーサ5及び上段の半導体チップ6からなる。この積層構造は、一例であり、半導体チップの数や、スペーサーの有無などは、適宜選択可能である。半導体チップ4,6はそれぞれワイヤ7により基板1に接続されている。本実施の形態において、下段チップ4の大きさは、8mm×8mm、スペーサー5の大きさは6mm×6mm、上段チップ6の大きさは7mm×7mmである。   FIG. 2 is a cross-sectional view showing an example of a laminated structure of the semiconductor chips 4 and 6 and the spacer 5, and FIG. 3 is a plan view thereof. In the present embodiment, the semiconductor chip 4 includes a lower semiconductor chip 4, a spacer 5 and an upper semiconductor chip 6 stacked on the substrate 1. This stacked structure is an example, and the number of semiconductor chips, the presence or absence of spacers, and the like can be selected as appropriate. The semiconductor chips 4 and 6 are connected to the substrate 1 by wires 7 respectively. In the present embodiment, the size of the lower chip 4 is 8 mm × 8 mm, the size of the spacer 5 is 6 mm × 6 mm, and the size of the upper chip 6 is 7 mm × 7 mm.

次に、図4,5に示すように、基板1上に金型8を被せる。そして、基板1と金型8の間のキャビティ9に樹脂を注入して、複数の半導体チップ4,6を一括して樹脂封止する。その後、基板1及び樹脂を半導体チップ4,6毎に切断して個別の半導体装置を製造する。   Next, as shown in FIGS. 4 and 5, a mold 8 is placed on the substrate 1. And resin is inject | poured into the cavity 9 between the board | substrate 1 and the metal mold | die 8, and several semiconductor chips 4 and 6 are resin-sealed collectively. Thereafter, the substrate 1 and the resin are cut into the semiconductor chips 4 and 6 to manufacture individual semiconductor devices.

ここで、図4は、金型の内部を示す上面図であり、図5は、図4のX−X´における金型の断面図である。金型8の一辺に樹脂を注入するための樹脂注入ゲート10が形成され、金型8の一辺に対向する辺に空気を抜くためのエアベント11が形成されている。そして、樹脂注入ゲート10が形成された辺からエアベント11が形成された辺に向かう方向が樹脂注入方向である。   Here, FIG. 4 is a top view showing the inside of the mold, and FIG. 5 is a cross-sectional view of the mold at XX ′ in FIG. A resin injection gate 10 for injecting resin is formed on one side of the mold 8, and an air vent 11 for extracting air is formed on the side opposite to the one side of the mold 8. The direction from the side where the resin injection gate 10 is formed to the side where the air vent 11 is formed is the resin injection direction.

また、半導体チップ4,6上の領域であって、樹脂注入方向に沿って延在する領域が、チップ上樹脂注入経路12aである。そして、図4中で左右に隣接する半導体チップ4,6の間の領域であって、樹脂注入方向に沿って延在する領域が、チップ間樹脂注入経路12bである。さらに、図4中で上下に隣接する製品領域3の間の領域であって、樹脂注入方向に直交して延在する領域が、製品間領域12cである。   Further, the region on the semiconductor chips 4 and 6 and extending along the resin injection direction is the on-chip resin injection path 12a. And the area | region between the semiconductor chips 4 and 6 adjacent on either side in FIG. 4, and the area | region extended along the resin injection | pouring direction is the interchip resin injection | pouring path | route 12b. Further, an area between the product areas 3 adjacent in the vertical direction in FIG. 4 and extending perpendicular to the resin injection direction is an inter-product area 12c.

また、金型8は、下方に伸びる金型突起8a,8b,8cを有する。この金型突起8aは、樹脂注入ゲート10と複数の半導体チップ4,6との間の領域に、樹脂注入ゲート10が形成された辺に平行に設けられている。そして、金型突起8bは、チップ間樹脂注入経路12bで、かつ製品領域3外に設けられている。さらに、金型突起8cは、複数の半導体チップ4,6とエアベント11との間の領域に、エアベント11が形成された辺に平行に設けられている。また、金型突起8a,8b,8cの真下における樹脂の厚みAは、樹脂の最大の厚みBの1/2より小さい(A<B/2)。このように金型突起8a,8b,8cを設けて樹脂の流れを制御することで、チップ間樹脂注入経路12bにおける樹脂の流動抵抗をチップ上樹脂注入経路12aにおける樹脂の流動抵抗に近づけることができるため、表面ボイドが発生するのを防ぐことができる。このように、樹脂の流れを制御するには、十分な高さを有する金型突起8a,8b,8cを設ける必要がある。金型突起8a,8b,8cの高さは、前述の通り、金型突起8a,8b,8cの真下における樹脂の厚みAが、樹脂の最大の厚みBの1/2より小さくなるような高さにする必要がある。このように、十分な高さの突起を設けるためには、半導体チップ4,6やワイヤ7など、半導体装置を構成する様々な部材が配置された製品領域3を避けて、製品領域外の部分に金型突起8a,8b,8cを設ける事が重要である。   The mold 8 has mold protrusions 8a, 8b, and 8c extending downward. The mold protrusion 8a is provided in a region between the resin injection gate 10 and the plurality of semiconductor chips 4 and 6 in parallel with the side where the resin injection gate 10 is formed. The mold protrusion 8b is provided outside the product region 3 in the inter-chip resin injection path 12b. Further, the mold protrusion 8 c is provided in a region between the plurality of semiconductor chips 4 and 6 and the air vent 11 in parallel with the side where the air vent 11 is formed. Further, the thickness A of the resin immediately below the mold protrusions 8a, 8b, 8c is smaller than 1/2 of the maximum thickness B of the resin (A <B / 2). By thus providing the mold protrusions 8a, 8b, and 8c to control the resin flow, the resin flow resistance in the inter-chip resin injection path 12b can be made closer to the resin flow resistance in the on-chip resin injection path 12a. Therefore, the generation of surface voids can be prevented. Thus, in order to control the flow of the resin, it is necessary to provide the mold protrusions 8a, 8b, 8c having a sufficient height. As described above, the height of the mold protrusions 8a, 8b, and 8c is such that the resin thickness A just below the mold protrusions 8a, 8b, and 8c is smaller than 1/2 of the maximum thickness B of the resin. It is necessary to be safe. As described above, in order to provide a sufficiently high protrusion, avoid the product region 3 where various members constituting the semiconductor device such as the semiconductor chips 4 and 6 and the wires 7 are arranged, and a portion outside the product region. It is important to provide the mold protrusions 8a, 8b and 8c.

また、金型突起8bの真下にも樹脂を注入する(A>0)のが好ましい。これにより、金型突起8bの真下において樹脂の剥離が生じるのを防ぐことができるため、金型突起8bの真下における剥離を起点として製品領域3に剥離が伝搬するのを防ぐことができる。   Further, it is preferable to inject resin (A> 0) directly below the mold protrusion 8b. Thereby, since it is possible to prevent the resin from peeling immediately below the mold protrusion 8b, it is possible to prevent the peeling from propagating to the product region 3 starting from the peeling immediately below the mold protrusion 8b.

また、金型突起8bは、チップ上樹脂注入経路12aの中心線上で、かつ製品間領域12cには存在しないのが好ましい。これにより、チップ上樹脂注入経路12aを流れる樹脂の流動抵抗を小さくすることができる。   Further, it is preferable that the mold protrusion 8b does not exist on the center line of the on-chip resin injection path 12a and in the inter-product region 12c. Thereby, the flow resistance of the resin flowing through the on-chip resin injection path 12a can be reduced.

また、金型突起8bの真下における樹脂の厚みAが、上段の半導体チップ6上における樹脂の最小の厚みCよりも小さいのが好ましい(A<C)。そして、金型突起8bが、樹脂注入方向に直交して延在する製品間領域12cに存在し、金型突起8bの樹脂注入方向に垂直な方向の幅Dが、チップ間樹脂注入経路12bの幅Eよりも大きい(D>E)のが好ましい。これにより、チップ間樹脂注入経路12bを流れる樹脂の流動抵抗を大きくすることができる。   Further, it is preferable that the resin thickness A immediately below the mold protrusion 8b is smaller than the minimum resin thickness C on the upper semiconductor chip 6 (A <C). The mold protrusion 8b exists in the inter-product region 12c extending perpendicular to the resin injection direction, and the width D in the direction perpendicular to the resin injection direction of the mold protrusion 8b is equal to that of the inter-chip resin injection path 12b. It is preferable that it is larger than the width E (D> E). Thereby, the flow resistance of the resin flowing through the inter-chip resin injection path 12b can be increased.

具体的には、図6に示すように、キャビティ9を50mm×37mm、製品領域3同士の間隔を3mm、キャビティ9の端と製品領域3との間隔を1.5mm、金型突起8bの樹脂注入方向に垂直な方向の幅を11mm、金型突起8b同士の間隔を5mmとする。また、図7に示すように、金型突起8a,8b,8cの真下における樹脂の厚みを0.2mm、キャビティ9内における樹脂の最大の厚みを0.91mm、上段の半導体チップ6上における樹脂の最小の厚みを0.23mmとする。   Specifically, as shown in FIG. 6, the cavity 9 is 50 mm × 37 mm, the distance between the product areas 3 is 3 mm, the distance between the end of the cavity 9 and the product area 3 is 1.5 mm, and the resin of the mold protrusion 8b. The width in the direction perpendicular to the injection direction is 11 mm, and the distance between the mold protrusions 8b is 5 mm. Further, as shown in FIG. 7, the resin thickness just below the mold protrusions 8a, 8b, 8c is 0.2 mm, the maximum resin thickness in the cavity 9 is 0.91 mm, and the resin on the upper semiconductor chip 6 The minimum thickness is 0.23 mm.

実施の形態2.
図8は、本発明の実施の形態2に係る金型の内部を示す上面図である。図4と同様の構成要素には同じ番号を付し、説明を省略する。
Embodiment 2. FIG.
FIG. 8 is a top view showing the inside of the mold according to Embodiment 2 of the present invention. Constituent elements similar to those in FIG.

金型8は、下方に伸びる金型突起8d(第1の金型突起)と、金属突起8e(第2の金属突起)を有する。金型突起8dは、製品間領域12cに設けられ、隣接する樹脂注入ゲート10間の中心線上には存在しない。そして、金型突起8eは、複数の半導体チップ4,6とエアベント11の間の領域に設けられ、キャビティ9の端部には存在しない。また、金型突起8d,8eの真下における樹脂の厚みは、樹脂の最大の厚みの1/2より小さい。   The mold 8 has a mold protrusion 8d (first mold protrusion) extending downward and a metal protrusion 8e (second metal protrusion). The mold protrusion 8d is provided in the inter-product region 12c and does not exist on the center line between the adjacent resin injection gates 10. The mold protrusion 8 e is provided in a region between the plurality of semiconductor chips 4 and 6 and the air vent 11 and does not exist at the end of the cavity 9. Further, the thickness of the resin directly below the mold protrusions 8d and 8e is smaller than 1/2 of the maximum thickness of the resin.

このように金型突起8d,8eを設けたことにより、半導体チップ4,6上を斜めに樹脂が流れるように制御することができるため、表面ボイドが発生するのを防ぐことができる。   By providing the mold protrusions 8d and 8e in this way, it is possible to control the resin so that the resin flows obliquely on the semiconductor chips 4 and 6, so that the generation of surface voids can be prevented.

また、実施の形態1と同様に、金型突起8d,8eの真下にも樹脂を注入するのが好ましく、金型突起の真下における樹脂の厚みが、半導体チップ上における樹脂の最小の厚みよりも小さいのが好ましい。   Similarly to the first embodiment, it is preferable to inject resin directly under the mold protrusions 8d and 8e, and the thickness of the resin directly under the mold protrusion is smaller than the minimum thickness of the resin on the semiconductor chip. Small is preferable.

そして、金型突起8d,8eは製品領域外に存在するのが好ましい。これにより、半導体装置のパッケージ外形に影響されずに金型突起8d,8eを設けることができる。   The mold protrusions 8d and 8e are preferably present outside the product area. Thus, the mold protrusions 8d and 8e can be provided without being affected by the package shape of the semiconductor device.

基板上に複数の半導体チップを配列した状態を示す上面図である。It is a top view which shows the state which arranged the several semiconductor chip on the board | substrate. 半導体チップの一例を示す断面図である。It is sectional drawing which shows an example of a semiconductor chip. 半導体チップの一例を示す平面図である。It is a top view which shows an example of a semiconductor chip. 金型の内部を示す上面図である。It is a top view which shows the inside of a metal mold | die. 図4のX−X´における金型の断面図である。It is sectional drawing of the metal mold | die in XX 'of FIG. 金型の一例を示す上面図である。It is a top view which shows an example of a metal mold | die. 金型の一例を示す断面図である。It is sectional drawing which shows an example of a metal mold | die. 本発明の実施の形態2に係る金型の内部を示す上面図である。It is a top view which shows the inside of the metal mold | die which concerns on Embodiment 2 of this invention.

符号の説明Explanation of symbols

1 基板
4,6 半導体チップ
3 製品領域
8 金型
8a〜8e 金型突起
9 キャビティ
10 樹脂注入ゲート
11 エアベント
12a 半導体チップ上樹脂注入経路
12b 半導体チップ間樹脂注入経路
12c 製品間領域
DESCRIPTION OF SYMBOLS 1 Board | substrates 4 and 6 Semiconductor chip 3 Product area | region 8 Mold 8a-8e Mold protrusion 9 Cavity 10 Resin injection gate 11 Air vent 12a Resin injection path 12b on a semiconductor chip Resin injection path 12c between semiconductor chips Inter-product area

Claims (11)

基板上に複数の半導体チップを配列する工程と、
前記基板上に金型を被せ、前記基板と前記金型の間のキャビティに樹脂を注入して、前記複数の半導体チップを一括して樹脂封止する工程と、
前記基板及び前記樹脂を半導体チップ毎に切断する工程とを有し、
前記金型の一辺に前記樹脂を注入するための樹脂注入ゲートが形成され、
前記金型の前記一辺に対向する辺に空気を抜くためのエアベントが形成され、
前記樹脂注入ゲートが形成された辺から前記エアベントが形成された辺に向かう方向が樹脂注入方向であり、
前記金型は、前記樹脂注入方向に沿って延在する半導体チップ間樹脂注入経路で、かつ製品領域外において、キャビティ内に伸びる金型突起を有し、
前記金型突起の真下における前記樹脂の厚みが、前記キャビティ内樹脂の最大の厚みの1/2より小さいことを特徴とする半導体装置の製造方法。
Arranging a plurality of semiconductor chips on a substrate;
Covering the substrate with a mold, injecting resin into a cavity between the substrate and the mold, and collectively sealing the plurality of semiconductor chips;
Cutting the substrate and the resin for each semiconductor chip,
A resin injection gate for injecting the resin on one side of the mold is formed,
An air vent for venting air is formed on a side opposite to the one side of the mold,
The direction from the side where the resin injection gate is formed toward the side where the air vent is formed is the resin injection direction,
The mold has a mold projection extending into the cavity in the resin injection path between the semiconductor chips extending along the resin injection direction and outside the product region,
A method of manufacturing a semiconductor device, wherein the thickness of the resin immediately below the mold protrusion is smaller than 1/2 of the maximum thickness of the resin in the cavity.
前記金型突起の真下にも前記樹脂を注入することを特徴とする請求項1に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the resin is also injected directly under the mold protrusion. 前記金型突起は、樹脂注入方向に沿って延在する半導体チップ上樹脂注入経路の中心線上で、かつ前記樹脂注入方向に直交して延在する製品間領域には存在しないことを特徴とする請求項1に記載の半導体装置の製造方法。   The mold protrusion is not present in a center line of a resin injection path on a semiconductor chip extending along a resin injection direction and in an inter-product region extending perpendicular to the resin injection direction. A method for manufacturing a semiconductor device according to claim 1. 前記金型突起の真下における前記樹脂の厚みが、前記半導体チップ上における前記樹脂の最小の厚みよりも小さいことを特徴とする請求項1に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the resin immediately below the mold protrusion is smaller than the minimum thickness of the resin on the semiconductor chip. 前記金型突起の樹脂注入方向に垂直な方向の幅は、前記半導体チップ間樹脂注入経路の幅よりも大きいことを特徴とする請求項1に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein a width of the mold protrusion in a direction perpendicular to a resin injection direction is larger than a width of the resin injection path between the semiconductor chips. 前記金型突起は、前記樹脂注入方向に直交して延在する製品間領域に存在することを特徴とする請求項5に記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein the mold protrusion is present in an inter-product region extending perpendicular to the resin injection direction. 基板上に複数の半導体チップを配列する工程と、
前記基板上に金型を被せ、前記基板と前記金型の間のキャビティに樹脂を注入して、前記複数の半導体チップを一括して樹脂封止する工程と、
前記基板及び前記樹脂を半導体チップ毎に切断する工程とを有し、
前記金型の一辺に前記樹脂を注入するための複数の樹脂注入ゲートが形成され、
前記金型の前記一辺に対向する辺に空気を抜くためのエアベントが形成され、
前記樹脂注入ゲートが形成された辺から前記エアベントが形成された辺に向かう方向が樹脂注入方向であり、
前記金型は、前記樹脂注入方向に直交して延在する製品間領域において下方に伸びる第1の金型突起を有し、
前記第1の金型突起は、隣接する前記樹脂注入ゲート間の中心線上には存在せず、
前記金型突起の真下における前記樹脂の厚みが、前記樹脂の最大の厚みの1/2より小さいことを特徴とする半導体装置の製造方法。
Arranging a plurality of semiconductor chips on a substrate;
Covering the substrate with a mold, injecting resin into a cavity between the substrate and the mold, and collectively sealing the plurality of semiconductor chips;
Cutting the substrate and the resin for each semiconductor chip,
A plurality of resin injection gates for injecting the resin on one side of the mold are formed,
An air vent for venting air is formed on a side opposite to the one side of the mold,
The direction from the side where the resin injection gate is formed toward the side where the air vent is formed is the resin injection direction,
The mold has a first mold protrusion extending downward in an inter-product region extending perpendicular to the resin injection direction,
The first mold protrusion does not exist on the center line between the adjacent resin injection gates,
A method of manufacturing a semiconductor device, wherein the thickness of the resin immediately below the mold protrusion is smaller than 1/2 of the maximum thickness of the resin.
前記金型突起の真下にも前記樹脂を注入することを特徴とする請求項7に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 7, wherein the resin is also injected directly under the mold protrusion. 前記金型突起は、製品領域外に存在することを特徴とする請求項7に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 7, wherein the mold protrusion is present outside a product region. 前記金型突起の真下における前記樹脂の厚みが、前記半導体チップ上における前記樹脂の最小の厚みよりも小さいことを特徴とする請求項7に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 7, wherein a thickness of the resin just below the mold protrusion is smaller than a minimum thickness of the resin on the semiconductor chip. 前記金型は、前記複数の半導体チップと前記エアベントの間の領域において下方に伸びる第2の金型突起を有し、
前記第2の金型突起は、前記キャビティの端部には存在しないことを特徴とする請求項7に記載の半導体装置の製造方法。
The mold has a second mold protrusion extending downward in a region between the plurality of semiconductor chips and the air vent;
The method of manufacturing a semiconductor device according to claim 7, wherein the second mold protrusion does not exist at an end of the cavity.
JP2005267387A 2005-09-14 2005-09-14 Manufacturing method of semiconductor device Pending JP2007081153A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008112924A (en) * 2006-10-31 2008-05-15 Denso Corp Method of manufacturing semiconductor device
KR101845376B1 (en) * 2016-01-13 2018-04-04 시그네틱스 주식회사 Chip molding device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008112924A (en) * 2006-10-31 2008-05-15 Denso Corp Method of manufacturing semiconductor device
KR101845376B1 (en) * 2016-01-13 2018-04-04 시그네틱스 주식회사 Chip molding device

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