JP5259369B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP5259369B2
JP5259369B2 JP2008319938A JP2008319938A JP5259369B2 JP 5259369 B2 JP5259369 B2 JP 5259369B2 JP 2008319938 A JP2008319938 A JP 2008319938A JP 2008319938 A JP2008319938 A JP 2008319938A JP 5259369 B2 JP5259369 B2 JP 5259369B2
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Japan
Prior art keywords
substrate
main surface
chip
semiconductor device
wiring board
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JP2008319938A
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Japanese (ja)
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JP2010147090A (en
Inventor
稔 篠原
富文 井上
誠一郎 津久井
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2008319938A priority Critical patent/JP5259369B2/en
Priority to US12/606,504 priority patent/US8648453B2/en
Publication of JP2010147090A publication Critical patent/JP2010147090A/en
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Publication of JP5259369B2 publication Critical patent/JP5259369B2/en
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

Description

本発明は、半導体装置及びその製造技術に関し、特に、半導体パッケージを多段に積層した構造の半導体装置の信頼性向上に適用して有効な技術に関する。   The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a technique effective when applied to improve the reliability of a semiconductor device having a structure in which semiconductor packages are stacked in multiple stages.

半導体装置の高集積化に伴い、メモリ系の半導体チップと、この半導体チップを制御するコントローラ系の半導体チップを１つの半導体装置に混載し、１つのシステムを構築するＳＩＰ（System In Package）型の半導体装置が開発されている。   Along with the high integration of semiconductor devices, a SIP (System In Package) type in which a memory-type semiconductor chip and a controller-type semiconductor chip for controlling the semiconductor chip are mixedly mounted on a single semiconductor device. Semiconductor devices have been developed.

そして、この半導体装置に内蔵するメモリ系の半導体装置の容量を製品の用途に合わせて変更できる、特許文献１に示すようなＰＯＰ（Package On Package）型の構成が有効とされている（例えば、特許文献１参照）。
特開２００７−１２３４５４号公報 A POP (Package On Package) type configuration as shown in Patent Document 1 that can change the capacity of a memory semiconductor device built in the semiconductor device according to the application of the product is effective (for example, Patent Document 1).
JP 2007-123454 A

しかしながら、前記特許文献１に示すようなＰＯＰ型の半導体装置の場合、上段の配線基板と下段の配線基板を電気的に接続するボール電極（バンプ電極）は、下段の配線基板に搭載された半導体チップの周囲に配置される。そのため、下段の配線基板上に搭載された半導体チップを保護するための封止体が、樹脂を充填（供給）するためのゲート部を半導体チップの上部に設けたトップゲート方式により形成される。   However, in the case of a POP type semiconductor device as shown in Patent Document 1, a ball electrode (bump electrode) that electrically connects an upper wiring board and a lower wiring board is a semiconductor mounted on the lower wiring board. Located around the chip. Therefore, a sealing body for protecting the semiconductor chip mounted on the lower wiring board is formed by a top gate method in which a gate portion for filling (supplying) resin is provided on the upper portion of the semiconductor chip.

このような半導体装置について本願発明者が検討した結果、以下の問題を発見した。   As a result of examination of such a semiconductor device by the present inventor, the following problems were discovered.

まず、配線基板の主面において、封止体が中央部のみに形成され、この封止体の周囲において、上段の配線基板は複数のバンプ電極を介して下段の配線基板と電気的に接続される。すなわち、下段の配線基板の周縁部まで、封止体が形成されていない。また、下段の配線基板、下段の半導体チップ、上段の配線基板、及び上段の半導体チップのそれぞれの厚さや、サイズは、異なっている。そのため、それぞれの熱膨張係数も異なる。   First, on the main surface of the wiring board, a sealing body is formed only at the center, and the upper wiring board is electrically connected to the lower wiring board through a plurality of bump electrodes around the sealing body. The That is, the sealing body is not formed up to the peripheral edge of the lower wiring board. Further, the thickness and size of the lower wiring board, the lower semiconductor chip, the upper wiring board, and the upper semiconductor chip are different. Therefore, each coefficient of thermal expansion is also different.

これにより、バンプ電極を溶融して接合するための熱処理工程において、上段の配線基板と下段の配線基板（特に、下段の配線基板の周縁部）のそれぞれに反りが発生し、バンプ電極の接合部において、未接続が生じるという問題を見出した。   As a result, in the heat treatment process for melting and bonding the bump electrodes, warpage occurs in each of the upper wiring board and the lower wiring board (particularly, the peripheral portion of the lower wiring board), and the bump electrode bonding portion Found a problem that unconnection occurred.

また、トップゲート方式の場合、ゲート部から供給された樹脂は、配線基板の主面上において収束させる。   In the case of the top gate method, the resin supplied from the gate portion is converged on the main surface of the wiring board.

そのため、金型に形成されたキャビティ内に残存する空気を、封止体を形成する領域の外側に排出することが困難となり、形成される封止体の内部に空気が残りやすいという問題を見出した。   Therefore, it becomes difficult to exhaust the air remaining in the cavity formed in the mold to the outside of the region where the sealing body is formed, and the problem is that air tends to remain inside the formed sealing body. It was.

本発明の目的は、半導体装置における信頼性の向上を図ることができる技術を提供することにある。   An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

すなわち、本発明は、第１配線基板の第１基板主面の平面形状が、一対の第１辺と、前記第１辺と交差する一対の第２辺とを有する四角形から成り、第１封止体は、第１配線基板の一方の前記第２辺の中央部から他方の前記第２辺の中央部に向かって形成されており、複数の第１基板主面側ランドは、前記第１封止体と前記配線基板の前記第１辺との間に配置されているものである。   That is, according to the present invention, the planar shape of the first substrate main surface of the first wiring board is a quadrangle having a pair of first sides and a pair of second sides intersecting with the first sides. The stationary body is formed from the central portion of one of the second sides of the first wiring board toward the central portion of the other second side, and the plurality of first substrate main surface side lands are the first land. It is arrange | positioned between the sealing body and the said 1st edge | side of the said wiring board.

また、本発明は、第１配線基板の第１基板主面の平面形状が、一対の第１辺と、前記第１辺と交差する一対の第２辺とを有する四角形から成り、複数の第１基板主面側ランドは、樹脂が供給される領域と前記配線基板の前記第１辺との間に配置されており、前記樹脂で封止する工程では、前記第１配線基板の一方の前記第２辺の中央部から他方の前記第２辺の中央部に向かって前記樹脂を供給し、封止体を形成するものである。   In the present invention, the planar shape of the first substrate main surface of the first wiring board is a quadrangle having a pair of first sides and a pair of second sides intersecting the first side, One board main surface side land is disposed between a region to which resin is supplied and the first side of the wiring board. In the step of sealing with the resin, one of the first wiring boards is The resin is supplied from the central part of the second side toward the central part of the other second side to form a sealing body.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

下段の配線基板の主面に形成される複数のランドを、配線基板の中央部に位置するチップ搭載領域を境に、その両側に振り分けて配置しているため、スルーモールド方式を採用することができ、その結果、下段の配線基板上の封止体を基板の一方の端部から他方の端部にまで亘って形成することができる。これにより、配線基板の反りに対する強度を高めることができ、半導体装置の信頼性の向上を図ることができる。   Since multiple lands formed on the main surface of the lower wiring board are distributed and arranged on both sides of the chip mounting area located in the center of the wiring board, it is possible to adopt the through mold method As a result, the sealing body on the lower wiring board can be formed from one end of the substrate to the other end. As a result, the strength against warping of the wiring board can be increased, and the reliability of the semiconductor device can be improved.

スルーモールド方式を採用することができるため、キャビティ内に残留する空気を、封止体を形成する領域の外側に排出することができる。これにより、封止体の内部にボイドが形成されることを低減でき、半導体装置の信頼性の向上を図ることができる。   Since the through mold method can be adopted, the air remaining in the cavity can be discharged outside the region where the sealing body is formed. Thereby, it is possible to reduce the formation of voids inside the sealing body, and to improve the reliability of the semiconductor device.

以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

さらに、以下の実施の形態では便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。   Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

また、以下の実施の形態において、要素の数など（個数、数値、量、範囲などを含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良いものとする。   Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

（実施の形態１）
図１は本発明の実施の形態１の半導体装置の構造の一例を示す平面図、図２は図１に示す半導体装置の裏面側の構造の一例を示す底面図、図３は図２のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図４は図２のＢ−Ｂ線に沿って切断した構造の一例を示す断面図、図５は図３のＡ部の構造の一例を示す拡大部分断面図である。また、図６は図１に示す半導体装置の第１半導体パッケージの構造の一例を示す平面図、図７は図６に示す第１半導体パッケージの構造を封止体を透過して示す平面図、図８は図６に示す第１半導体パッケージの裏面側の構造を示す底面図、図９は図１に示す半導体装置の第２半導体パッケージの構造の一例を封止体を透過して示す平面図、図１０は図９に示す第２半導体パッケージの裏面側の構造を示す底面図である。さらに、図１１は図１に示す半導体装置の回路ブロック構成の一例を示す回路ブロック図である。 (Embodiment 1)
1 is a plan view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a bottom view showing an example of the structure on the back side of the semiconductor device shown in FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing an example of the structure cut along the line A, FIG. 4 is a cross-sectional view showing an example of the structure cut along the line BB in FIG. 2, and FIG. It is an enlarged partial sectional view showing an example. 6 is a plan view showing an example of the structure of the first semiconductor package of the semiconductor device shown in FIG. 1. FIG. 7 is a plan view showing the structure of the first semiconductor package shown in FIG. FIG. 8 is a bottom view showing the structure of the back surface side of the first semiconductor package shown in FIG. 6, and FIG. 9 is a plan view showing an example of the structure of the second semiconductor package of the semiconductor device shown in FIG. FIG. 10 is a bottom view showing the structure of the back surface side of the second semiconductor package shown in FIG. Further, FIG. 11 is a circuit block diagram showing an example of a circuit block configuration of the semiconductor device shown in FIG.

図１〜図５に示す本実施の形態１の半導体装置は、半導体パッケージを多段に積層した構造のＰＯＰ（Package On Package）型半導体装置８であり、本実施の形態１では、下段側の第１半導体パッケージ７上に上段側の第２半導体パッケージ１７を積層したものである。   The semiconductor device according to the first embodiment shown in FIGS. 1 to 5 is a POP (Package On Package) type semiconductor device 8 having a structure in which semiconductor packages are stacked in multiple stages. In this example, an upper second semiconductor package 17 is stacked on one semiconductor package 7.

本実施の形態１のＰＯＰ型半導体装置８では、下段側の第１半導体パッケージ７に制御系の第１半導体チップが搭載されており、一方、上段側の第２半導体パッケージ１７にはメモリ系の第２半導体チップが搭載されており、このメモリ系の第２半導体チップは、制御系の第１半導体チップによって制御される。したがって、ＰＯＰ型半導体装置８は、ＳＩＰ型の半導体装置でもある。   In the POP type semiconductor device 8 of the first embodiment, the first semiconductor chip of the control system is mounted on the first semiconductor package 7 on the lower stage side, while the second semiconductor package 17 on the upper stage side has the memory system. A second semiconductor chip is mounted, and the second semiconductor chip of the memory system is controlled by the first semiconductor chip of the control system. Therefore, the POP type semiconductor device 8 is also a SIP type semiconductor device.

ＰＯＰ型半導体装置８を、下段側の第１半導体パッケージ７と、上段側の第２半導体パッケージ１７とに分けて説明する。   The POP type semiconductor device 8 will be described by dividing it into a first semiconductor package 7 on the lower stage side and a second semiconductor package 17 on the upper stage side.

まず、下段側の第１半導体パッケージ７の構成について説明すると、制御系の第１半導体チップであるコントローラチップ１と、コントローラチップ１が搭載された第１配線基板２と、コントローラチップ１と第１配線基板２とを電気的に接続する第１導電性部材である複数のワイヤ３と、コントローラチップ１と複数のワイヤ３を樹脂によって封止する第１封止体４と、第１配線基板２の裏面２ｂに設けられた複数の半田ボール５とから成る。   First, the configuration of the lower first semiconductor package 7 will be described. The controller chip 1, which is the first semiconductor chip of the control system, the first wiring board 2 on which the controller chip 1 is mounted, the controller chip 1, and the first A plurality of wires 3 that are first conductive members that electrically connect the wiring board 2, a first sealing body 4 that seals the controller chip 1 and the plurality of wires 3 with resin, and the first wiring board 2 And a plurality of solder balls 5 provided on the back surface 2b.

第１配線基板２は、図５及び図７に示すように、複数の第１ボンディングリード２ｃが形成された第１チップ搭載領域２ｄを有する主面（第１基板主面）２ａと、複数の第１ボンディングリード２ｃのそれぞれと電気的に接続され、かつ前記主面２ａにおいて第１チップ搭載領域２ｄの周囲に配置された複数の主面側ランド（第１基板主面側ランド）２ｅを有している。さらに、主面２ａとは反対側に位置する裏面（第１基板裏面）２ｂと、複数の第１ボンディングリード２ｃのそれぞれと電気的に接続され、かつ前記裏面２ｂに配置された複数の裏面側ランド（第１基板裏面側ランド）２ｆを有している。   As shown in FIGS. 5 and 7, the first wiring substrate 2 includes a main surface (first substrate main surface) 2a having a first chip mounting region 2d in which a plurality of first bonding leads 2c are formed, and a plurality of first bonding substrates 2d. A plurality of main surface side lands (first substrate main surface side lands) 2e electrically connected to each of the first bonding leads 2c and disposed around the first chip mounting region 2d on the main surface 2a. doing. Furthermore, the back surface (first substrate back surface) 2b located on the opposite side of the main surface 2a and the plurality of back surface sides electrically connected to each of the plurality of first bonding leads 2c and disposed on the back surface 2b A land (first substrate back surface side land) 2f is provided.

また、第１配線基板２は、図５に示すようにコア材２ｇと、その表裏両面に形成された配線部２ｉと、表裏両面の配線部２ｉを電気的に接続するスルーホール配線２ｊと、各配線部２ｉを覆う絶縁膜であるソルダレジスト膜２ｈとを有している。これにより、主面側ランド２ｅと第１ボンディングリード２ｃ及び裏面側ランド２ｆが、配線部２ｉとスルーホール配線２ｊを介して電気的に接続されている。ソルダレジスト膜２ｈは、各配線部２ｉは覆っているが、主面側ランド２ｅ、第１ボンディングリード２ｃ及び裏面側ランド２ｆにおいては、それぞれの電極の周縁部のみを覆っており、中央部は開口している。これにより、主面側ランド２ｅ、第１ボンディングリード２ｃ及び裏面側ランド２ｆの各電極は電気的接続が行えるようになっている。   Further, as shown in FIG. 5, the first wiring board 2 includes a core material 2g, wiring portions 2i formed on both front and back surfaces, through-hole wiring 2j that electrically connects the wiring portions 2i on both front and back surfaces, And a solder resist film 2h which is an insulating film covering each wiring portion 2i. Thereby, the main surface side land 2e, the first bonding lead 2c, and the back surface side land 2f are electrically connected via the wiring portion 2i and the through-hole wiring 2j. The solder resist film 2h covers each wiring portion 2i, but the main surface side land 2e, the first bonding lead 2c and the back surface side land 2f cover only the peripheral portion of each electrode, and the central portion is It is open. Thereby, each electrode of the main surface side land 2e, the 1st bonding lead 2c, and the back surface side land 2f can be electrically connected now.

なお、複数の裏面側ランド２ｆは、図２〜図４の半田ボール５の配列に示すように、第１配線基板２の裏面２ｂの外周部に２列に並んでペリフェラル配置で設けられている。   The plurality of backside lands 2f are provided in a peripheral arrangement in two rows on the outer periphery of the backside 2b of the first wiring board 2 as shown in the arrangement of the solder balls 5 in FIGS. .

また、第１半導体パッケージ７に搭載された第１半導体チップである制御系のコントローラチップ１は、図７に示すように第１配線基板２の第１チップ搭載領域２ｄに搭載され、制御回路を有しており、さらに図５に示すように主面（第１チップ主面）１ａ、主面１ａに形成された複数の第１パッド（第１電極パッド）１ｃ、及び主面１ａとは反対側に位置する裏面（第１チップ裏面）１ｂを有している。   Further, the controller chip 1 of the control system which is the first semiconductor chip mounted on the first semiconductor package 7 is mounted on the first chip mounting area 2d of the first wiring board 2 as shown in FIG. Further, as shown in FIG. 5, the main surface (first chip main surface) 1a, a plurality of first pads (first electrode pads) 1c formed on the main surface 1a, and the main surface 1a are opposite to each other. It has a back surface (first chip back surface) 1b located on the side.

なお、コントローラチップ１の主面１ａの複数の第１パッド１ｃは、図７に示すように、主面１ａの４辺の周縁部に沿って並んで設けられている。コントローラチップ１は、図５に示すように、第１配線基板２の主面２ａにペースト材やフィルム状接着材等のダイボンド材６によって固着されている。   In addition, the some 1st pad 1c of the main surface 1a of the controller chip 1 is provided along with the peripheral part of 4 sides of the main surface 1a, as shown in FIG. As shown in FIG. 5, the controller chip 1 is fixed to the main surface 2a of the first wiring board 2 with a die bond material 6 such as a paste material or a film adhesive.

また、コントローラチップ１の複数の第１パッド１ｃと第１配線基板２の複数の第１ボンディングリード２ｃとは、それぞれワイヤ（第１導電性部材）３によって電気的に接続されている。   The plurality of first pads 1 c of the controller chip 1 and the plurality of first bonding leads 2 c of the first wiring board 2 are electrically connected by wires (first conductive members) 3, respectively.

さらに、図６及び図７に示すように、複数の主面側ランド２ｅのそれぞれが露出するように第１封止体４が第１配線基板２の主面２ａ上に形成されており、この第１封止体４によって、コントローラチップ１、複数のワイヤ３及び第１配線基板２の主面２ａが樹脂封止されている。   Further, as shown in FIGS. 6 and 7, the first sealing body 4 is formed on the main surface 2a of the first wiring substrate 2 so that each of the plurality of main surface side lands 2e is exposed. The controller chip 1, the plurality of wires 3, and the main surface 2 a of the first wiring board 2 are resin-sealed by the first sealing body 4.

また、第１配線基板２の裏面２ｂの複数の裏面側ランド２ｆのそれぞれには、図５及び図８に示すように半田ボール５が接合されている。   Further, as shown in FIGS. 5 and 8, solder balls 5 are joined to each of the plurality of back surface lands 2 f of the back surface 2 b of the first wiring substrate 2.

次に、上段側の第２半導体パッケージ１７の構成について説明すると、メモリ系の第２半導体チップである不揮発性メモリ１１と、不揮発性メモリ１１が搭載された第２配線基板１２と、不揮発性メモリ１１と第２配線基板１２とを電気的に接続する第２導電性部材である複数のワイヤ１３と、不揮発性メモリ１１と複数のワイヤ１３を樹脂によって封止する第２封止体１４と、第２配線基板１２の裏面１２ｂに設けられた複数の半田ボール１５とから成る。   Next, the configuration of the second semiconductor package 17 on the upper stage will be described. The nonvolatile memory 11 that is the second semiconductor chip of the memory system, the second wiring substrate 12 on which the nonvolatile memory 11 is mounted, and the nonvolatile memory A plurality of wires 13 that are second conductive members that electrically connect the first wiring board 11 and the second wiring substrate 12, a second sealing body 14 that seals the nonvolatile memory 11 and the plurality of wires 13 with a resin, It consists of a plurality of solder balls 15 provided on the back surface 12 b of the second wiring board 12.

第２配線基板１２は、図５及び図９に示すように、複数の第２ボンディングリード１２ｃが形成された第２チップ搭載領域１２ｄを有する主面（第２基板主面）１２ａと、主面１２ａとは反対側に位置する裏面（第２基板裏面）１２ｂと、複数の第２ボンディングリード１２ｃのそれぞれと電気的に接続され、かつ前記裏面１２ｂに配置された複数の裏面側ランド（第２基板裏面側ランド）１２ｆを有している。   As shown in FIGS. 5 and 9, the second wiring substrate 12 includes a main surface (second substrate main surface) 12a having a second chip mounting region 12d in which a plurality of second bonding leads 12c are formed, and a main surface. A plurality of back surface lands (second surfaces) electrically connected to a back surface (second substrate back surface) 12b located on the opposite side of 12a and each of the plurality of second bonding leads 12c and disposed on the back surface 12b. Substrate back side land) 12f.

また、第２配線基板１２は、第１配線基板２と同様に、図５に示すようにコア材１２ｇと、その表裏両面に形成された配線部１２ｉと、表裏両面の配線部１２ｉを接続するスルーホール配線１２ｊと、各配線部１２ｉを覆う絶縁膜であるソルダレジスト膜１２ｈとを有している。これにより、第２ボンディングリード１２ｃ及び裏面側ランド１２ｆが、配線部１２ｉとスルーホール配線１２ｊを介して電気的に接続されている。ソルダレジスト膜１２ｈは、第１配線基板２と同様に各配線部１２ｉは覆っているが、第２ボンディングリード１２ｃ及び裏面側ランド１２ｆにおいては、それぞれの電極の周縁部のみを覆っており、中央部は開口している。これにより、第２ボンディングリード１２ｃ及び裏面側ランド１２ｆの各電極は電気的接続が行えるようになっている。   Similarly to the first wiring board 2, the second wiring board 12 connects the core material 12g, the wiring part 12i formed on both front and back surfaces, and the wiring parts 12i on both front and back surfaces, as shown in FIG. It has a through-hole wiring 12j and a solder resist film 12h that is an insulating film covering each wiring portion 12i. Thereby, the second bonding lead 12c and the back surface side land 12f are electrically connected to each other through the wiring portion 12i and the through-hole wiring 12j. The solder resist film 12h covers each wiring portion 12i as in the first wiring substrate 2, but the second bonding lead 12c and the back surface side land 12f cover only the peripheral portion of each electrode, The part is open. Thereby, each electrode of the 2nd bonding lead 12c and the back side land 12f can be electrically connected now.

なお、複数の裏面側ランド１２ｆは、図１０の半田ボール１５の配列や図７の第１配線基板２の主面側ランド２ｅの配列に示されるように、第２配線基板１２の裏面１２ｂにおいて対向する１組の辺に沿ってそれぞれ並んで設けられている。   The plurality of back surface lands 12f are formed on the back surface 12b of the second wiring board 12 as shown in the arrangement of the solder balls 15 in FIG. 10 and the arrangement of the main surface side lands 2e in the first wiring board 2 in FIG. They are provided side by side along a pair of opposing sides.

また、第２半導体パッケージ１７に搭載された第２半導体チップであるメモリ系の不揮発性メモリ１１は、図９に示すように第２配線基板１２の第２チップ搭載領域１２ｄに搭載され、メモリ回路を有しており、さらに図５に示すように主面（第２チップ主面）１１ａ、主面１１ａに形成された複数の第２パッド（第２電極パッド）１１ｃ、及び主面１１ａとは反対側に位置する裏面（第２チップ裏面）１１ｂを有している。   Further, the memory nonvolatile memory 11 which is the second semiconductor chip mounted on the second semiconductor package 17 is mounted on the second chip mounting region 12d of the second wiring board 12 as shown in FIG. Further, as shown in FIG. 5, a main surface (second chip main surface) 11a, a plurality of second pads (second electrode pads) 11c formed on the main surface 11a, and a main surface 11a It has a back surface (second chip back surface) 11b located on the opposite side.

なお、不揮発性メモリ１１の主面１１ａの複数の第２パッド１１ｃは、図９に示すように、主面１１ａの４辺のうちの１辺に沿って並んで設けられている。不揮発性メモリ１１も、コントローラチップ１と同様に、図５に示すように、第２配線基板１２の主面１２ａにペースト材やフィルム状接着材等のダイボンド材１６によって固着されている。   The plurality of second pads 11c on the main surface 11a of the nonvolatile memory 11 are provided side by side along one of the four sides of the main surface 11a as shown in FIG. Similarly to the controller chip 1, the non-volatile memory 11 is also fixed to the main surface 12a of the second wiring board 12 by a die bond material 16 such as a paste material or a film adhesive as shown in FIG.

また、不揮発性メモリ１１は、コントローラチップ１によって制御される。   The nonvolatile memory 11 is controlled by the controller chip 1.

また、不揮発性メモリ１１の複数の第２パッド１１ｃと第２配線基板１２の複数の第２ボンディングリード１２ｃとは、それぞれワイヤ（第２導電性部材）１３によって電気的に接続されている。   The plurality of second pads 11 c of the nonvolatile memory 11 and the plurality of second bonding leads 12 c of the second wiring board 12 are electrically connected by wires (second conductive members) 13, respectively.

さらに、図５に示すように第２封止体１４が第２配線基板１２の主面１２ａ上に形成されており、この第１封止体４によって、不揮発性メモリ１１、複数のワイヤ１３及び第２配線基板１２の主面１２ａが樹脂封止されている。   Further, as shown in FIG. 5, the second sealing body 14 is formed on the main surface 12 a of the second wiring board 12, and the first sealing body 4 allows the nonvolatile memory 11, the plurality of wires 13, and The main surface 12a of the second wiring board 12 is resin-sealed.

また、第２配線基板１２の裏面１２ｂの複数の裏面側ランド１２ｆのそれぞれには、図５及び図１０に示すように半田ボール（第２外部端子、バンプ電極）１５が接合されており、上段側の第２配線基板１２の複数の裏面側ランド（電極、ランド）１２ｆと、下段側の第１配線基板２の複数の主面側ランド（電極、ランド）２ｅとが複数の半田ボール１５によって電気的に接続されている。   Further, as shown in FIGS. 5 and 10, solder balls (second external terminals, bump electrodes) 15 are joined to each of the plurality of back surface lands 12 f of the back surface 12 b of the second wiring substrate 12. A plurality of back surface lands (electrodes, lands) 12 f of the second wiring board 12 on the side and a plurality of main surface lands (electrodes, lands) 2 e of the first wiring board 2 on the lower stage are formed by a plurality of solder balls 15. Electrically connected.

なお、半田ボール１５は、図５に示すように、下段側の第１半導体パッケージ７の第１封止体４より高さが高くなければならないため、半田ボール５に比べて遥かに大きい。   As shown in FIG. 5, the solder ball 15 must be higher than the first sealing body 4 of the first semiconductor package 7 on the lower stage side, and therefore is much larger than the solder ball 5.

本実施の形態１のＰＯＰ型半導体装置８では、その下段側の第１半導体パッケージ７における第１配線基板２の主面２ａの平面形状は、図７に示すように、一対の第１辺２ｍと、この第１辺２ｍと交差する一対の第２辺２ｎとを有する四角形から成る。ＰＯＰ型半導体装置８では、第１配線基板２の主面側ランド２ｅの配列方向に沿った方向の辺を第１辺２ｍとし、この第１辺２ｍと交差する方向の辺を第２辺２ｎとしている。   In the POP type semiconductor device 8 of the first embodiment, the planar shape of the main surface 2a of the first wiring substrate 2 in the first semiconductor package 7 on the lower side is a pair of first sides 2m as shown in FIG. And a quadrangle having a pair of second sides 2n intersecting the first side 2m. In the POP type semiconductor device 8, the side in the direction along the arrangement direction of the main surface side lands 2e of the first wiring board 2 is defined as the first side 2m, and the side in the direction intersecting the first side 2m is defined as the second side 2n. It is said.

さらに、ＰＯＰ型半導体装置８では、図６に示すように下段側の第１半導体パッケージ７の第１配線基板２上の第１封止体４は、第１配線基板２の一方の第２辺２ｎの中央部から他方の第２辺２ｎの中央部に向かって形成されている。すなわち、第１封止体４は、一方の第２辺２ｎから対向する他方の第２辺２ｎに到達するように形成されている。   Further, in the POP type semiconductor device 8, the first sealing body 4 on the first wiring board 2 of the first semiconductor package 7 on the lower stage side is one second side of the first wiring board 2 as shown in FIG. 6. It is formed from the central part of 2n toward the central part of the other second side 2n. That is, the first sealing body 4 is formed so as to reach the other second side 2n facing from the second side 2n.

さらに、複数の主面側ランド２ｅは、第１封止体４の両側に配置され、第１封止体４と第１配線基板２の一方の第１辺２ｍとの間と、他方の第１辺２ｍとの間において、それぞれ第１辺２ｍに沿って１列に並んで配置されている。ただし、複数の主面側ランド２ｅは、第１封止体４の両側において、第１辺２ｍに沿ってそれぞれ複数列に亘って配置されていてもよい。   Further, the plurality of main surface side lands 2e are arranged on both sides of the first sealing body 4, and between the first sealing body 4 and one first side 2m of the first wiring board 2, and the other first side. Between each side 2m, they are arranged in a line along the first side 2m. However, the plurality of main surface side lands 2e may be arranged across a plurality of rows along the first side 2m on both sides of the first sealing body 4.

つまり、ＰＯＰ型半導体装置８では、第１配線基板２の主面２ａにおいて、第１封止体４が一方の第２辺２ｎから対向する他方の第２辺２ｎに到達するように、かつ第２辺２ｎより狭い幅（第１チップ搭載領域２ｄより僅かに大きい程度の幅）で形成されており、また、複数の主面側ランド２ｅが、第１封止体４の両側に振り分けられてそれぞれ第１辺２ｍに沿って並んで配置されている。   That is, in the POP type semiconductor device 8, the first sealing body 4 reaches the other second side 2n opposite from the second side 2n on the main surface 2a of the first wiring substrate 2 and It is formed with a width narrower than the two sides 2n (a width slightly larger than the first chip mounting region 2d), and a plurality of main surface lands 2e are distributed to both sides of the first sealing body 4. They are arranged side by side along the first side 2m.

ここで、上段側の第２半導体パッケージ１７の第２半導体チップである不揮発性メモリ１１と、下段側の第１半導体パッケージ７の第１半導体チップであるコントローラチップ（マイコンチップ）１とで、両者の電極パッド数の違いについて説明する。すなわち、本実施の形態１のＰＯＰ型半導体装置８では、上段側の第２半導体パッケージ１７には不揮発性メモリ１１が搭載されており、下段側の第１半導体パッケージ７には上段側の不揮発性メモリ１１を制御するコントローラチップ１が搭載されている。不揮発性メモリ（例えば、ＦＬＡＳＨメモリ）１１は、読み出すためのデータや書き込んだデータを格納しておく記録手段である。   Here, both the nonvolatile memory 11 that is the second semiconductor chip of the second semiconductor package 17 on the upper stage side and the controller chip (microcomputer chip) 1 that is the first semiconductor chip of the first semiconductor package 7 on the lower stage side. The difference in the number of electrode pads will be described. That is, in the POP type semiconductor device 8 of the first embodiment, the non-volatile memory 11 is mounted on the second semiconductor package 17 on the upper stage side, and the non-volatile side on the upper stage side is mounted on the first semiconductor package 7 on the lower stage side. A controller chip 1 that controls the memory 11 is mounted. A non-volatile memory (for example, a FLASH memory) 11 is a recording unit that stores data to be read and written data.

図１１の回路ブロック図に示すように、コントローラチップ１は、ＰＯＰ型半導体装置８、言い換えるとコントローラチップ１と不揮発性メモリ１１により構築されたシステムの内部に位置する不揮発性メモリ１１の制御を行うため、不揮発性メモリ１１と信号の入出力を行う（電気的に接続する）ためのメモリインターフェース（内部インターフェース）を有している。また、ＰＯＰ型半導体装置８、言い換えるとシステムの外部（又は、外部に搭載された外部機器）と信号のやり取り（入出力）も行う（電気的に接続する）ための外部インターフェースも有している。すなわち、コントローラチップ１に形成された複数の第１パッド１ｃは、内部インターフェース用のパッドと、外部インターフェース用のパッドを有している。一方、不揮発性メモリ１１は、外部機器と直接的に信号のやり取りは行わないため、両者の電極パッド数の違いは明らかであり、コントローラチップ１の方が不揮発性メモリ１１より電極パッド数が多い。つまり、ＰＯＰ型半導体装置８において、コントローラチップ１が有する複数の第１パッド１ｃの数（総数）は、不揮発性メモリ１１が有する複数の第２パッド１１ｃの数（総数）よりも多い。   As shown in the circuit block diagram of FIG. 11, the controller chip 1 controls the POP type semiconductor device 8, in other words, the nonvolatile memory 11 located inside the system constructed by the controller chip 1 and the nonvolatile memory 11. Therefore, it has a memory interface (internal interface) for inputting / outputting (electrically connecting) signals to / from the nonvolatile memory 11. The POP type semiconductor device 8, in other words, also has an external interface for exchanging (electrically connecting) signals to and from the outside of the system (or external equipment mounted outside). . In other words, the plurality of first pads 1c formed on the controller chip 1 have internal interface pads and external interface pads. On the other hand, since the nonvolatile memory 11 does not directly exchange signals with external devices, the difference in the number of electrode pads between the two is obvious, and the controller chip 1 has more electrode pads than the nonvolatile memory 11. . That is, in the POP type semiconductor device 8, the number (total number) of the plurality of first pads 1 c included in the controller chip 1 is larger than the number (total number) of the plurality of second pads 11 c included in the nonvolatile memory 11.

さらに、本実施の形態１のＰＯＰ型半導体装置８では、上段側の第２半導体パッケージ１７に搭載されたメモリは１種類のみである。したがって、必然的に不揮発性メモリ１１の電極パッド数は少ない。   Further, in the POP type semiconductor device 8 of the first embodiment, only one type of memory is mounted on the second semiconductor package 17 on the upper stage side. Therefore, the number of electrode pads of the nonvolatile memory 11 is inevitably small.

このように本実施の形態１のＰＯＰ型半導体装置８では、上段側の第２半導体パッケージ１７に搭載される半導体チップがメモリチップであるとともに、その種類が１種類のみであるため、上段側の第２半導体パッケージ１７の裏面側ランド１２ｆの数を少なくすることができ、その結果、下段側の第１半導体パッケージ７の主面側ランド２ｅの数も少なくすることができる。したがって、これら主面側ランド２ｅを第１封止体４の両側に振り分けて配置することが可能になる。   As described above, in the POP type semiconductor device 8 according to the first embodiment, the semiconductor chip mounted on the second semiconductor package 17 on the upper stage side is a memory chip and there is only one type. The number of back surface lands 12f of the second semiconductor package 17 can be reduced, and as a result, the number of main surface side lands 2e of the first semiconductor package 7 on the lower side can also be reduced. Therefore, these main surface side lands 2 e can be distributed and arranged on both sides of the first sealing body 4.

これにより、第１封止体４を第１配線基板２の主面２ａの端部まで配置することができる。したがって、樹脂モールディング時のゲート部を第１配線基板２の主面２ａの端部近傍に配置することができ、第１封止体４の形成時に、スルーモールド方式（一括モールド方式：複数のデバイス領域を樹脂成形金型の１つのキャビティで一括して覆って樹脂モールドを行う方式）を採用することができる。   Thereby, the 1st sealing body 4 can be arrange | positioned to the edge part of the main surface 2a of the 1st wiring board 2. FIG. Therefore, the gate part at the time of resin molding can be arranged near the end of the main surface 2a of the first wiring board 2, and when the first sealing body 4 is formed, a through mold method (batch molding method: a plurality of devices) It is possible to employ a method in which the resin is molded by collectively covering the region with one cavity of the resin mold.

したがって、図６に示すように第１封止体４を第１配線基板２の一方の第２辺２ｎの中央部から、対向する他方の第２辺２ｎの中央部に到達するように形成することが可能になる。その結果、第１封止体４を第１配線基板２の主面２ａ上の端（辺）から対向する端（辺）まで形成可能になるため、第１半導体パッケージ７の剛性を高めることができる。   Accordingly, as shown in FIG. 6, the first sealing body 4 is formed so as to reach the central portion of the other second side 2n opposite from the central portion of the one second side 2n of the first wiring substrate 2. It becomes possible. As a result, the first sealing body 4 can be formed from the end (side) on the main surface 2a of the first wiring substrate 2 to the opposite end (side), so that the rigidity of the first semiconductor package 7 can be increased. it can.

このように、本実施の形態１のＰＯＰ型半導体装置８の下段側の第１半導体パッケージ７の第１封止体４は、スルーモールド方式によって形成されたものである。   As described above, the first sealing body 4 of the first semiconductor package 7 on the lower side of the POP type semiconductor device 8 of the first embodiment is formed by a through mold method.

次に、本実施の形態１のＰＯＰ型半導体装置８の製造方法について説明する。   Next, a method for manufacturing the POP type semiconductor device 8 of the first embodiment will be described.

図１２は図１に示す半導体装置の第１半導体パッケージの組み立てで用いられる配線基板の構造の一例を示す平面図、図１３は図１２に示す配線基板の裏面側の構造の一例を示す裏面図、図１４は図１２のＡ部の構造を示す拡大部分平面図、図１５は図１４のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図１６は図１４のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。また、図１７は図６に示す第１半導体パッケージの組み立てにおけるダイボンディング後の構造の一例を示す部分拡大平面図、図１８は図１７のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図１９は図１７のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。さらに、図２０は図６に示す第１半導体パッケージの組み立てにおけるワイヤボンディング後の構造の一例を示す部分拡大平面図、図２１は図２０のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図２２は図２０のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。また、図２３は図６に示す第１半導体パッケージの組み立てにおける樹脂モールディング後の構造の一例を示す部分拡大平面図、図２４は図２３のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図２５は図２３のＢ−Ｂ線に沿って切断した構造の一例を示す断面図、図２６は図１３のＡ部におけるボールマウント後の構造の一例を示す裏面図、図２７は図２６のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。   12 is a plan view showing an example of the structure of the wiring board used in assembling the first semiconductor package of the semiconductor device shown in FIG. 1, and FIG. 13 is a back view showing an example of the structure on the back side of the wiring board shown in FIG. 14 is an enlarged partial plan view showing the structure of part A in FIG. 12, FIG. 15 is a sectional view showing an example of the structure cut along the line AA in FIG. 14, and FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the line. 17 is a partially enlarged plan view showing an example of the structure after die bonding in the assembly of the first semiconductor package shown in FIG. 6, and FIG. 18 shows an example of the structure cut along the line AA in FIG. 19 is a cross-sectional view showing an example of a structure cut along the line BB in FIG. 20 is a partially enlarged plan view showing an example of the structure after wire bonding in the assembly of the first semiconductor package shown in FIG. 6, and FIG. 21 shows an example of the structure cut along the line AA in FIG. FIG. 22 is a sectional view showing an example of a structure cut along the line BB in FIG. 23 is a partially enlarged plan view showing an example of the structure after resin molding in the assembly of the first semiconductor package shown in FIG. 6, and FIG. 24 shows an example of the structure cut along the line AA in FIG. 25 is a cross-sectional view showing an example of the structure cut along the line BB in FIG. 23, FIG. 26 is a back view showing an example of the structure after ball mounting in the A part of FIG. 13, and FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG.

まず、下段側の第１半導体パッケージ７の製造方法について説明する。   First, a method for manufacturing the first semiconductor package 7 on the lower side will be described.

図１２〜図１６に示すように、第１チップ搭載領域２ｄを有する主面２ａ、主面２ａにおいて第１チップ搭載領域２ｄの周囲に配置された複数の主面側ランド２ｅ、主面２ａとは反対側に位置する裏面２ｂ、及び裏面２ｂに配置された複数の裏面側ランド２ｆを有するデバイス領域９ａが複数個形成されたマトリクス基板（第１配線基板２）９を準備する。なお、図１２に示すように、主面２ａの第１チップ搭載領域２ｄには複数の第１ボンディングリード２ｃが形成されている。また、図１４に示すように、複数の主面側ランド２ｅのそれぞれは、複数の第１ボンディングリード２ｃと電気的に接続されている。また、図１２及び図１４に示すように、複数のデイバス領域９ａの第２辺２ｎと、この第２辺２ｎと隣接し、このデバイス領域９ａの外側に位置するマトリクス基板９の辺（前記第２辺２ｎに最も近い辺）との間には、ゲート部９ｄが配置されている。このゲート部９ｄの表面には、Ａｕメッキ層が形成されており、このゲート部９ｄを介して、ポット部（図示しない）に投入された樹脂がデバイス領域９ａ内に供給される。尚、ゲート部９ｄの表面に、Ａｕメッキ層が形成されているため、後の工程で形成された封止体１８の一部を分離するゲートブレーク工程において、マトリクス基板９から容易に封止体１８の一部を分離（剥離）することができる。さらに、図１５及び図１６に示す複数の裏面側ランド２ｆのそれぞれも複数の第１ボンディングリード２ｃと電気的に接続されている。   As shown in FIGS. 12 to 16, a main surface 2a having a first chip mounting region 2d, a plurality of main surface side lands 2e arranged around the first chip mounting region 2d on the main surface 2a, and a main surface 2a Prepare a matrix substrate (first wiring substrate 2) 9 on which a plurality of device regions 9a having a back surface 2b located on the opposite side and a plurality of back surface lands 2f arranged on the back surface 2b are formed. As shown in FIG. 12, a plurality of first bonding leads 2c are formed in the first chip mounting region 2d of the main surface 2a. Further, as shown in FIG. 14, each of the plurality of main surface side lands 2e is electrically connected to the plurality of first bonding leads 2c. Further, as shown in FIGS. 12 and 14, the second side 2n of the plurality of device areas 9a and the side of the matrix substrate 9 adjacent to the second side 2n and positioned outside the device area 9a (the first side) Between the two sides 2n, the gate portion 9d is disposed. An Au plating layer is formed on the surface of the gate portion 9d, and the resin put into the pot portion (not shown) is supplied into the device region 9a through the gate portion 9d. Since the Au plating layer is formed on the surface of the gate portion 9d, the sealing body can be easily separated from the matrix substrate 9 in the gate break process in which a part of the sealing body 18 formed in the subsequent process is separated. A part of 18 can be separated (peeled). Further, each of the plurality of back surface lands 2f shown in FIGS. 15 and 16 is also electrically connected to the plurality of first bonding leads 2c.

その後、ダイボンディングを行う。ここでは、図１７〜図１９に示すように、主面１ａ、主面１ａに形成された複数の第１パッド１ｃ、及び主面１ａとは反対側に位置する裏面１ｂを有する複数のコントローラチップ１を、マトリクス基板（第１配線基板２）９の複数のデバイス領域９ａのそれぞれの図１４に示す第１チップ搭載領域２ｄ上に搭載する。その際、図５に示すように、各コントローラチップ１はダイボンド材６を介して第１配線基板２上に搭載する。   Thereafter, die bonding is performed. Here, as shown in FIGS. 17 to 19, a plurality of controller chips having a main surface 1a, a plurality of first pads 1c formed on the main surface 1a, and a back surface 1b located on the opposite side of the main surface 1a. 1 is mounted on the first chip mounting region 2d shown in FIG. 14 in each of the plurality of device regions 9a of the matrix substrate (first wiring substrate 2) 9. At that time, as shown in FIG. 5, each controller chip 1 is mounted on the first wiring substrate 2 via the die bonding material 6.

その後、ワイヤボンディングを行う。ここでは、図２０〜図２２に示すように、コントローラチップ１の複数の第１パッド１ｃと、第１配線基板２の複数の第１ボンディングリード２ｃとを複数のワイヤ３（例えば、金線）を介してそれぞれ電気的に接続する。   Thereafter, wire bonding is performed. Here, as shown in FIGS. 20 to 22, a plurality of first pads 1c of the controller chip 1 and a plurality of first bonding leads 2c of the first wiring substrate 2 are connected to a plurality of wires 3 (for example, gold wires). Are electrically connected to each other.

その後、樹脂モールディングを行う。ここでは、図２３〜図２５に示すように、複数の主面側ランド２ｅのそれぞれが露出するように、複数のコントローラチップ１、複数のワイヤ３、及び第１配線基板２の主面２ａを樹脂で一括して封止する。ここで、前述したゲートブレーク工程において、半導体チップ１を封止する封止体１８から、ゲート部９ｄ上に形成された不要な封止体１８（ゲートレジン）を分離し易くするために、図２５に示すように、ゲート部９ｄに対応する上金型の一部（図示しない）に段差部を形成している。これにより、ゲート部９ｄに形成された封止体１８の表面（厚さ）は、デバイス領域９ａに形成された封止体１８の表面（厚さ）よりも低く（薄く）なる。   Thereafter, resin molding is performed. Here, as shown in FIGS. 23 to 25, the plurality of controller chips 1, the plurality of wires 3, and the main surface 2 a of the first wiring board 2 are formed so that each of the plurality of main surface side lands 2 e is exposed. Seal with resin. Here, in the gate break process described above, in order to easily separate the unnecessary sealing body 18 (gate resin) formed on the gate portion 9d from the sealing body 18 that seals the semiconductor chip 1, FIG. As shown in FIG. 25, a stepped portion is formed in a part (not shown) of the upper mold corresponding to the gate portion 9d. Thereby, the surface (thickness) of the sealing body 18 formed in the gate part 9d becomes lower (thin) than the surface (thickness) of the sealing body 18 formed in the device region 9a.

なお、第１配線基板２では、図７に示すようにその主面２ａの平面形状は、一対の第１辺２ｍと、第１辺２ｍと交差する一対の第２辺２ｎとを有する四角形から成り、複数の主面側ランド２ｅは、樹脂が供給される領域（封止体１８（第１封止体４）が形成される領域；モールド領域２ｋ）と第１配線基板２の一方の第１辺２ｍとの間（と、他方の第１辺２ｍとの間）に（おいて、第１辺２ｍに沿って）配置されている。そこで、前記樹脂で封止する工程では、第１配線基板２の一方の第２辺２ｎの中央部から、対向する他方の第２辺２ｎの中央部に向かって前記樹脂を供給し、これによって図２３に示すように一括した封止体１８を形成する。   In the first wiring board 2, as shown in FIG. 7, the planar shape of the main surface 2a is a quadrangle having a pair of first sides 2m and a pair of second sides 2n intersecting the first side 2m. The plurality of main-surface-side lands 2e include a region to which a resin is supplied (a region where the sealing body 18 (first sealing body 4) is formed; a mold region 2k) and one of the first wiring boards 2. It is arranged between the one side 2m (and the other first side 2m) (and along the first side 2m). Therefore, in the step of sealing with the resin, the resin is supplied from the central portion of one second side 2n of the first wiring board 2 toward the central portion of the other second side 2n facing the first wiring substrate 2, thereby As shown in FIG. 23, the sealing body 18 collectively formed is formed.

すなわち、ＰＯＰ型半導体装置８では、上段側の第２半導体パッケージ１７に搭載される半導体チップがメモリチップであるとともに、その種類が１種類のみであるため、上段側の第２半導体パッケージ１７の裏面側ランド１２ｆの数を少なくすることができ、その結果、下段側の第１半導体パッケージ７の主面側ランド２ｅの数も少なくすることができる。したがって、これら主面側ランド２ｅを図２０に示すモールド領域２ｋの両側に振り分けて配置することが可能になる。これにより、封止体１８を図７に示す第１配線基板２の一方の第２辺２ｎの中央部から、対向する他方の第２辺２ｎの中央部に到達するように形成することが可能になり、樹脂モールド方式として、スルーモールド方式（一括モールド方式：複数のデバイス領域を樹脂成形金型の１つのキャビティで一括して覆って樹脂モールドを行う方式）を採用することができる。つまり、図７の第１配線基板２の第１辺２ｍに沿った方向である図２３に示すレジン流動方向１０に沿って樹脂をスルーモールド方式で第１配線基板２に対して供給できる。なお、レジン流動方向１０は、図２３に示された方向と１８０°反対の方向であってもよい。   That is, in the POP type semiconductor device 8, the semiconductor chip mounted on the second semiconductor package 17 on the upper stage side is a memory chip and there is only one kind, so the back surface of the second semiconductor package 17 on the upper stage side. The number of side lands 12f can be reduced, and as a result, the number of main surface side lands 2e of the lower first semiconductor package 7 can also be reduced. Therefore, these main surface side lands 2e can be distributed and arranged on both sides of the mold region 2k shown in FIG. Accordingly, the sealing body 18 can be formed so as to reach the central portion of the other second side 2n opposite from the central portion of one second side 2n of the first wiring board 2 shown in FIG. Thus, as the resin mold method, a through mold method (batch molding method: a method in which a plurality of device regions are collectively covered with one cavity of a resin molding die and resin molding is performed) can be adopted. That is, the resin can be supplied to the first wiring board 2 by the through-mold method along the resin flow direction 10 shown in FIG. 23 which is the direction along the first side 2m of the first wiring board 2 of FIG. The resin flow direction 10 may be a direction 180 ° opposite to the direction shown in FIG.

以上のように、本実施の形態１のＰＯＰ型半導体装置８の組み立てでは、その樹脂モールディング工程で、スルーモールド方式を採用して、複数のデバイス領域９ａを一括して封止して、これにより、一括した細長い封止体１８を形成できる。   As described above, in assembling the POP type semiconductor device 8 according to the first embodiment, the resin molding process employs a through mold method to collectively seal a plurality of device regions 9a. In this manner, a long and narrow sealing body 18 can be formed.

その後、ボールマウントを行う。ここでは、図２６及び図２７に示すように、図５の第１配線基板２の複数の裏面側ランド２ｆのそれぞれに複数の第１外部端子である半田ボール５を形成する。その後、個片化の切断を行って下段側の第１半導体パッケージ７の組み立て完了となる。   Thereafter, ball mounting is performed. Here, as shown in FIGS. 26 and 27, a plurality of solder balls 5 as first external terminals are formed on each of the plurality of back surface lands 2f of the first wiring board 2 in FIG. After that, cutting into individual pieces is performed, and assembly of the first semiconductor package 7 on the lower side is completed.

次に、上段側の第２半導体パッケージ１７の製造方法について説明する。   Next, a method for manufacturing the second semiconductor package 17 on the upper stage will be described.

図２８は図１に示す半導体装置の第２半導体パッケージの組み立てで用いられる配線基板の構造の一例を示す平面図、図２９は図２８に示す配線基板の裏面側の構造の一例を示す裏面図、図３０は図２８のＡ部の構造を示す拡大部分平面図、図３１は図３０のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図３２は図３０のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。また、図３３は図９に示す第２半導体パッケージの組み立てにおけるダイボンディング後の構造の一例を示す部分拡大平面図、図３４は図３３のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図３５は図３３のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。さらに、図３６は図９に示す第２半導体パッケージの組み立てにおけるワイヤボンディング後の構造の一例を示す部分拡大平面図、図３７は図３６のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図３８は図３６のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。また、図３９は図９に示す第１半導体パッケージの組み立てにおける樹脂モールディング後の構造の一例を示す部分拡大平面図、図４０は図３９のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図４１は図３９のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。さらに、図４２は図２９のＡ部におけるボールマウント後の構造の一例を示す裏面図、図４３は図４２のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図４４は図４２のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。   28 is a plan view showing an example of the structure of the wiring board used in assembling the second semiconductor package of the semiconductor device shown in FIG. 1, and FIG. 29 is a back view showing an example of the structure on the back side of the wiring board shown in FIG. 30 is an enlarged partial plan view showing the structure of part A in FIG. 28, FIG. 31 is a sectional view showing an example of the structure cut along the line AA in FIG. 30, and FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the line. 33 is a partially enlarged plan view showing an example of the structure after die bonding in the assembly of the second semiconductor package shown in FIG. 9, and FIG. 34 shows an example of the structure cut along the line AA in FIG. FIG. 35 is a sectional view showing an example of a structure cut along the line BB in FIG. Further, FIG. 36 is a partially enlarged plan view showing an example of the structure after wire bonding in the assembly of the second semiconductor package shown in FIG. 9, and FIG. 37 shows an example of the structure cut along the line AA in FIG. 38 is a sectional view showing an example of a structure cut along the line BB in FIG. 39 is a partially enlarged plan view showing an example of the structure after resin molding in the assembly of the first semiconductor package shown in FIG. 9, and FIG. 40 shows an example of the structure cut along the line AA in FIG. 41 is a cross-sectional view showing an example of a structure cut along the line BB in FIG. Further, FIG. 42 is a rear view showing an example of the structure after the ball mounting in the A part of FIG. 29, FIG. 43 is a sectional view showing an example of the structure cut along the line AA of FIG. 42, and FIG. It is sectional drawing which shows an example of the structure cut | disconnected along 42 BB line.

まず、図２８〜図３２に示すように、図３０の第２チップ搭載領域１２ｄを有する主面１２ａ、主面１２ａとは反対側に位置する裏面１２ｂ、及び裏面１２ｂに配置された複数の裏面側ランド１２ｆを有するデバイス領域９ｃが複数個形成されたマトリクス基板（第２配線基板１２）９ｂを準備する。なお、図３０に示すように、主面１２ａの第２チップ搭載領域１２ｄには複数の第２ボンディングリード１２ｃが形成されている。ただし、第２配線基板１２の第２ボンディングリード１２ｃの数が、第１配線基板２の第１ボンディングリード２ｃの数より少ないことは言うまでもない。また、図３１及び図３２に示す複数の裏面側ランド１２ｆのそれぞれは複数の第２ボンディングリード１２ｃと電気的に接続されている。   First, as shown in FIGS. 28 to 32, the main surface 12a having the second chip mounting region 12d in FIG. 30, the back surface 12b located on the opposite side of the main surface 12a, and a plurality of back surfaces arranged on the back surface 12b A matrix substrate (second wiring substrate 12) 9b on which a plurality of device regions 9c having side lands 12f are formed is prepared. As shown in FIG. 30, a plurality of second bonding leads 12c are formed in the second chip mounting region 12d of the main surface 12a. However, it goes without saying that the number of second bonding leads 12 c of the second wiring board 12 is smaller than the number of first bonding leads 2 c of the first wiring board 2. Each of the plurality of back surface lands 12f shown in FIGS. 31 and 32 is electrically connected to the plurality of second bonding leads 12c.

その後、ダイボンディングを行う。ここでは、図３３〜図３５に示すように、主面１１ａ、主面１１ａに形成された複数の第２パッド１１ｃ、及び主面１１ａとは反対側に位置する裏面１１ｂを有する複数の不揮発性メモリ１１を、マトリクス基板（第２配線基板１２）９ｂの複数のデバイス領域９ｃのそれぞれの図３０に示す第２チップ搭載領域１２ｄ上に搭載する。その際、図５に示すように、各不揮発性メモリ１１はダイボンド材１６を介して第２配線基板１２上に搭載する。   Thereafter, die bonding is performed. Here, as shown in FIG. 33 to FIG. 35, a plurality of nonvolatiles having a main surface 11a, a plurality of second pads 11c formed on the main surface 11a, and a back surface 11b positioned on the opposite side of the main surface 11a. The memory 11 is mounted on the second chip mounting region 12d shown in FIG. 30 in each of the plurality of device regions 9c of the matrix substrate (second wiring substrate 12) 9b. At that time, as shown in FIG. 5, each nonvolatile memory 11 is mounted on the second wiring substrate 12 via a die bonding material 16.

その後、ワイヤボンディングを行う。ここでは、図３６〜図３８に示すように、不揮発性メモリ１１の複数の第２パッド１１ｃと、第２配線基板１２の複数の第２ボンディングリード１２ｃとを複数のワイヤ１３（例えば、金線）を介してそれぞれ電気的に接続する。   Thereafter, wire bonding is performed. Here, as shown in FIGS. 36 to 38, a plurality of second pads 11c of the nonvolatile memory 11 and a plurality of second bonding leads 12c of the second wiring substrate 12 are connected to a plurality of wires 13 (for example, gold wires). ) Are electrically connected to each other.

その後、樹脂モールディングを行う。ここでは、図３９〜図４１に示すように、複数の不揮発性メモリ１１、複数のワイヤ１３、及び第２配線基板１２の主面１２ａを樹脂で一括して封止する。ここでは、複数のデバイス領域９ｃを一括して樹脂封止して図３６の複数のデバイス領域９ｃを一括して覆う封止体１８を形成する。   Thereafter, resin molding is performed. Here, as shown in FIGS. 39 to 41, the plurality of nonvolatile memories 11, the plurality of wires 13, and the main surface 12a of the second wiring substrate 12 are collectively sealed with resin. Here, a plurality of device regions 9c are collectively sealed with resin to form a sealing body 18 that collectively covers the plurality of device regions 9c in FIG.

その後、ボールマウントを行う。ここでは、図４２〜図４４に示すように、図５の第１配線基板２の主面側ランド２ｅと同ピッチで形成された第２配線基板１２の複数の裏面側ランド１２ｆのそれぞれに複数の第２外部端子である半田ボール１５を形成する。その後、個片化を行って上段側の第２半導体パッケージ１７の組み立て完了となる。   Thereafter, ball mounting is performed. Here, as shown in FIG. 42 to FIG. 44, a plurality of backside lands 12f of the second wiring board 12 formed at the same pitch as the main surface side lands 2e of the first wiring board 2 of FIG. Solder balls 15 as second external terminals are formed. After that, it is separated into pieces and assembly of the second semiconductor package 17 on the upper stage side is completed.

その後、下段側の第１半導体パッケージ７上に上段側の第２半導体パッケージ１７を積層する。   Thereafter, the upper second semiconductor package 17 is stacked on the lower first semiconductor package 7.

詳細には、第２配線基板１２上に不揮発性メモリ１１が搭載され、かつ主面１２ａとは反対側に位置する裏面１２ｂに複数の裏面側ランド１２ｆが配置された第２半導体パッケージ１７の第２配線基板１２を、複数の半田ボール１５を介して第１半導体パッケージ７の第１配線基板２上に搭載する。これにより、第１配線基板２の複数の主面側ランド２ｅと第２配線基板１２の複数の裏面側ランド１２ｆとをそれぞれ半田ボール１５を介して電気的に接続する。   More specifically, the second semiconductor package 17 includes the non-volatile memory 11 mounted on the second wiring board 12 and a plurality of backside lands 12f arranged on the backside 12b located on the side opposite to the main surface 12a. The two wiring boards 12 are mounted on the first wiring board 2 of the first semiconductor package 7 via the plurality of solder balls 15. Thereby, the plurality of main surface side lands 2 e of the first wiring substrate 2 and the plurality of back surface lands 12 f of the second wiring substrate 12 are electrically connected via the solder balls 15, respectively.

その際、予め第２半導体パッケージ１７の第２配線基板１２の裏面側ランド１２ｆに複数の半田ボール１５を設けておき、この複数の半田ボール１５を、第２半導体パッケージ１７に設けられた状態で、第１配線基板２の複数の主面側ランド２ｅ上に配置した後、第１半導体パッケージ７の複数の主面側ランド２ｅと、第２半導体パッケージ１７の複数の裏面側ランド１２ｆとを複数の半田ボール１５を介して電気的に接続する。   At that time, a plurality of solder balls 15 are provided in advance on the rear surface side land 12 f of the second wiring substrate 12 of the second semiconductor package 17, and the plurality of solder balls 15 are provided in the second semiconductor package 17. After arranging on the plurality of main surface side lands 2e of the first wiring substrate 2, a plurality of main surface side lands 2e of the first semiconductor package 7 and a plurality of back surface side lands 12f of the second semiconductor package 17 are provided. The solder balls 15 are electrically connected.

以上により、本実施の形態１のＰＯＰ型半導体装置８の組み立て完了となる。   As described above, the assembly of the POP type semiconductor device 8 of the first embodiment is completed.

なお、上段側の第２半導体パッケージ１７の第２配線基板１２の複数の裏面側ランド１２ｆに形成された複数の半田ボール１５は、必ずしも予め第２配線基板１２に形成されていなくてもよい。つまり、第２配線基板１２を第１配線基板２上に積層する際に、この複数の半田ボール１５を介して搭載（積層）してもよい。   The plurality of solder balls 15 formed on the plurality of back surface lands 12f of the second wiring board 12 of the second semiconductor package 17 on the upper stage side are not necessarily formed on the second wiring board 12 in advance. That is, when the second wiring board 12 is laminated on the first wiring board 2, the second wiring board 12 may be mounted (laminated) via the plurality of solder balls 15.

本実施の形態１のＰＯＰ型半導体装置８及びその製造方法によれば、下段側の第１半導体パッケージ７の第１配線基板２に形成される複数の主面側ランド２ｅを、第１配線基板２の中央部に位置する第１チップ搭載領域２ｄを境にその両側に振り分けて配置しており、これによって、第１封止体４を第１配線基板２の主面２ａの端部まで配置することができる。   According to the POP type semiconductor device 8 and the method of manufacturing the same of the first embodiment, the plurality of main surface side lands 2e formed on the first wiring substrate 2 of the first semiconductor package 7 on the lower stage side are replaced with the first wiring substrate. The first chip mounting area 2d located at the center of the first chip mounting area 2d is distributed and arranged on both sides thereof, whereby the first sealing body 4 is arranged up to the end of the main surface 2a of the first wiring board 2. can do.

したがって、樹脂モールディング時のゲート部を第１配線基板２の主面２ａの端部近傍に配置することができ、樹脂モールディングにおいてスルーモールド方式を採用することができる。   Therefore, the gate part at the time of resin molding can be disposed in the vicinity of the end of the main surface 2a of the first wiring board 2, and a through mold method can be adopted in the resin molding.

その結果、下段側の第１半導体パッケージ７の第１配線基板２上の第１封止体４を第１配線基板２の一方の端部（第２辺２ｎ）から、これに対向する他方の端部（第２辺２ｎ）にまで亘って形成することができる。これにより、第１半導体パッケージ７の剛性を高めることができるため、第１配線基板２の反りに対する強度を高めることができ、ＰＯＰ型半導体装置８の信頼性の向上を図ることができる。   As a result, the first sealing body 4 on the first wiring board 2 of the first semiconductor package 7 on the lower side is moved from one end (second side 2n) of the first wiring board 2 to the other opposite to the first sealing body 4. It can be formed over the end (second side 2n). Thereby, since the rigidity of the first semiconductor package 7 can be increased, the strength against the warp of the first wiring board 2 can be increased, and the reliability of the POP type semiconductor device 8 can be improved.

また、スルーモールド方式を採用することができるため、樹脂成形金型のキャビティ内に残留する空気を、第１封止体４を形成する領域の外側に排出することができる。これにより、第１封止体４の内部にボイドが形成されることを低減でき、ＰＯＰ型半導体装置８の信頼性の向上を図ることができる。   Further, since the through mold method can be adopted, the air remaining in the cavity of the resin mold can be discharged outside the region where the first sealing body 4 is formed. Thereby, it is possible to reduce the formation of voids in the first sealing body 4 and to improve the reliability of the POP type semiconductor device 8.

次に、本実施の形態１の変形例について説明する。   Next, a modification of the first embodiment will be described.

本実施の形態１では、上段側の第２配線基板１２側の組み立てまで完了した第２半導体パッケージ１７を、下段側の第１半導体パッケージ７上に積層する段階まで行うＰＯＰ型半導体装置８について説明したが、下段側の第１半導体パッケージ７の製造を完了した時点でこの第１半導体パッケージ７を出荷してもよい。これにより、製品の用途に応じて、マザーボード上に実装する前に、不揮発性メモリ１１（例えば、ＦＬＡＳＨ）の容量を変更することが容易になる。   In the first embodiment, the POP type semiconductor device 8 is described in which the second semiconductor package 17 that has been completed up to the assembly on the second wiring substrate 12 side on the upper stage side is stacked up on the first semiconductor package 7 on the lower stage side. However, the first semiconductor package 7 may be shipped when the manufacture of the lower first semiconductor package 7 is completed. This makes it easy to change the capacity of the nonvolatile memory 11 (for example, FLASH) before mounting on the mother board depending on the application of the product.

また、本実施の形態１では、上段側の第２配線基板１２上にメモリチップを搭載し、上段側の第２半導体パッケージ１７を製造してから、下段側の第１半導体パッケージ７上に積層する工程について説明したが、下段側の第１半導体パッケージ７を製造してから、予め準備しておいた上段側の第２半導体パッケージ１７を積層してもよい。これにより、上段側の第２半導体パッケージ１７を製造する工程が削減できるため、完成したＰＯＰ型半導体装置８の製造コストを低減することができる。   In the first embodiment, the memory chip is mounted on the second wiring substrate 12 on the upper stage side, the second semiconductor package 17 on the upper stage side is manufactured, and then stacked on the first semiconductor package 7 on the lower stage side. Although the process of performing is described, the first semiconductor package 7 on the lower stage side may be manufactured and then the second semiconductor package 17 on the upper stage side prepared in advance may be stacked. Thereby, since the process of manufacturing the second semiconductor package 17 on the upper stage side can be reduced, the manufacturing cost of the completed POP type semiconductor device 8 can be reduced.

（実施の形態２）
図４５は本発明の実施の形態２の半導体装置における第１半導体パッケージの構造の一例を封止体を透過して示す平面図、図４６は図４５のＢ−Ｂ線に沿って切断した本発明の実施の形態２の半導体装置の構造の一例を示す断面図である。また、図４７は本発明の実施の形態２の半導体装置の第１変形例における第１半導体パッケージの構造の一例を封止体を透過して示す平面図、図４８は図４７のＢ−Ｂ線に沿って切断した本発明の実施の形態２の半導体装置の第１変形例の構造を示す断面図、図４９は図４６に示す半導体装置の回路ブロック構成の一例を示す回路ブロック図である。 (Embodiment 2)
45 is a plan view showing an example of the structure of the first semiconductor package in the semiconductor device according to the second embodiment of the present invention through a sealing body, and FIG. 46 is a view cut along the line BB in FIG. It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 2 of invention. 47 is a plan view showing an example of the structure of the first semiconductor package in the first modification of the semiconductor device according to the second embodiment of the present invention through the sealing body, and FIG. 48 is a cross-sectional view taken along line BB in FIG. FIG. 49 is a circuit block diagram showing an example of the circuit block configuration of the semiconductor device shown in FIG. 46. FIG. 49 is a cross-sectional view showing the structure of the first modification of the semiconductor device according to the second embodiment of the present invention cut along the line. .

図４５及び図４６に示す本実施の形態２の半導体装置は、実施の形態１と同様に、半導体パッケージを多段に積層した構造のＰＯＰ型半導体装置１９であり、下段側の第１半導体パッケージ７上に上段側の第２半導体パッケージ１７を積層したものである。   The semiconductor device of the second embodiment shown in FIGS. 45 and 46 is a POP type semiconductor device 19 having a structure in which semiconductor packages are stacked in multiple stages, as in the first embodiment, and the first semiconductor package 7 on the lower stage side. The second semiconductor package 17 on the upper stage side is laminated on the top.

本実施の形態２のＰＯＰ型半導体装置１９では、下段側の第１半導体パッケージ７に制御系の第１半導体チップとその横にメモリ系の第３半導体チップが搭載されている。上段側の第２半導体パッケージ１７には実施の形態１のＰＯＰ型半導体装置８と同様にメモリ系の第２半導体チップのみが搭載されている。下段側の第１半導体パッケージ７に搭載されたメモリ系の第３半導体チップは、ＳＤＲＡＭ（Synchronous Dynamic Random Access Memory）２１等であり、上段側の第１半導体パッケージ７に搭載された第２半導体チップである不揮発性メモリ１１とは、異なったメモリ機能のメモリ回路を有している。下段側の第１半導体パッケージ７に搭載された第１半導体チップは、実施の形態１と同様にコントローラチップ１である。   In the POP type semiconductor device 19 of the second embodiment, the first semiconductor package 7 on the lower stage side is mounted with the first semiconductor chip for the control system and the third semiconductor chip for the memory system next to it. As in the POP type semiconductor device 8 of the first embodiment, only the second semiconductor chip of the memory system is mounted on the second semiconductor package 17 on the upper stage side. The memory-type third semiconductor chip mounted on the lower first semiconductor package 7 is an SDRAM (Synchronous Dynamic Random Access Memory) 21 or the like, and the second semiconductor chip mounted on the upper first semiconductor package 7. The non-volatile memory 11 is a memory circuit having a different memory function. The first semiconductor chip mounted on the lower first semiconductor package 7 is the controller chip 1 as in the first embodiment.

ＳＤＲＡＭ２１は、例えば、コントローラチップ１のキャッシュメモリとして設けられ、一時的に演算データを格納しておく記録手段であり、図４５に示すように第１配線基板２の第１辺２ｍに沿った方向のコントローラチップ１の隣に搭載されている。ＳＤＲＡＭ２１はその主面２１ａを上方に向け、裏面２１ｂと第１配線基板２の主面２ａとが接合されている。   The SDRAM 21 is, for example, a recording unit that is provided as a cache memory of the controller chip 1 and temporarily stores calculation data. The SDRAM 21 has a direction along the first side 2m of the first wiring board 2 as shown in FIG. It is mounted next to the controller chip 1. The SDRAM 21 has its main surface 21a facing upward, and the back surface 21b and the main surface 2a of the first wiring board 2 are joined.

図４９のＰＯＰ型半導体装置１９の回路ブロック図に示すように、上段側の不揮発性メモリ１１と下段側のＳＤＲＡＭ２１は、両者とも下段側のコントローラチップ１によって制御される。実施の形態１のＰＯＰ型半導体装置８と同様に、不揮発性メモリ１１及びＳＤＲＡＭ２１は、外部機器との信号のやり取りは行わず、コントローラチップ１のみが外部機器と信号のやり取りを行うため、コントローラチップ１が有する第１パッド（第１電極パッド）１ｃの数は、不揮発性メモリ１１が有する図５に示す第２パッド（第２電極パッド）１１ｃの数やＳＤＲＡＭ２１が有する第３パッド（第３電極パッド）２１ｃの数に比べて多い。つまり、ＳＤＲＡＭ２１の第３パッド２１ｃの数も不揮発性メモリ１１と同様に、コントローラチップ１の第１パッド１ｃの数に比べて少ない。   As shown in the circuit block diagram of the POP type semiconductor device 19 in FIG. 49, the upper nonvolatile memory 11 and the lower SDRAM 21 are both controlled by the lower controller chip 1. Like the POP type semiconductor device 8 of the first embodiment, the nonvolatile memory 11 and the SDRAM 21 do not exchange signals with external devices, and only the controller chip 1 exchanges signals with external devices. 1 includes the number of first pads (first electrode pads) 1c included in the non-volatile memory 11 and the number of second pads (second electrode pads) 11c illustrated in FIG. More than the number of pads) 21c. That is, the number of the third pads 21 c of the SDRAM 21 is smaller than the number of the first pads 1 c of the controller chip 1, similarly to the nonvolatile memory 11.

このように本実施の形態２のＰＯＰ型半導体装置１９においても、上段側の第２半導体パッケージ１７に搭載されるメモリチップの種類が１種類のみであるため、上段側の第２半導体パッケージ１７の裏面側ランド１２ｆの数を少なくすることができ、その結果、下段側の第１半導体パッケージ７の主面側ランド２ｅの数を少なくすることができる。   As described above, also in the POP type semiconductor device 19 of the second embodiment, only one type of memory chip is mounted on the upper second semiconductor package 17, so The number of back surface lands 12f can be reduced, and as a result, the number of main surface side lands 2e of the lower first semiconductor package 7 can be reduced.

これにより、図４５に示すように、複数の主面側ランド２ｅを図４６に示す第１封止体４の両側に振り分けて配置することが可能になる。   Thereby, as shown in FIG. 45, it becomes possible to distribute and arrange a plurality of main surface side lands 2e on both sides of the first sealing body 4 shown in FIG.

なお、ＳＤＲＡＭ２１は、コントローラチップ１のキャッシュメモリであり、信号処理の高速化を図るため、コントローラチップ１の近くに配置することが好ましい。したがって、下段側の第１半導体パッケージ７に搭載されている。その際、ＳＤＲＡＭ２１の主面（第３チップ主面）２１ａは、不揮発性メモリ１１の主面１１ａより小さく、かつ第１配線基板２の第１辺２ｍに沿った方向のコントローラチップ１の隣に搭載することで、第１封止体４の幅を広げることなく下段側のコントローラチップ１の近くにＳＤＲＡＭ２１を搭載することができる。これにより、ＰＯＰ型半導体装置１９においても実施の形態１のＰＯＰ型半導体装置８と同様に、第１封止体４をスルーモールド方式で形成することができる。   The SDRAM 21 is a cache memory of the controller chip 1 and is preferably arranged near the controller chip 1 in order to increase the speed of signal processing. Therefore, it is mounted on the lower first semiconductor package 7. At this time, the main surface (third chip main surface) 21a of the SDRAM 21 is smaller than the main surface 11a of the nonvolatile memory 11 and next to the controller chip 1 in the direction along the first side 2m of the first wiring board 2. By mounting, the SDRAM 21 can be mounted near the controller chip 1 on the lower side without increasing the width of the first sealing body 4. Thereby, also in the POP type semiconductor device 19, the 1st sealing body 4 can be formed by a through mold method similarly to the POP type semiconductor device 8 of Embodiment 1. FIG.

また、ＳＤＲＡＭ２１の平面形状（主面２１ａの形状）は、長方形から成り、主面２１ａに形成された複数の第３パッド（第３電極パッド）２１ｃは、図４５に示すように主面２１ａの長辺に沿って配置されている。すなわち、複数の第３パッド２１ｃは、第１配線基板２の第１辺２ｍに沿った方向のＳＤＲＡＭ２１の主面２１ａの中央部（ＳＤＲＡＭ２１の長方形の主面２１ａの幅方向の中央部）に第２辺２ｎに沿った方向に並んで配置されており、所謂センタパッド配置である。その際、前記センタパッド配置は、複数の第３パッド２１ｃが１列から成るものであっても、複数列から成るものであっても何れでもよい。   The planar shape of the SDRAM 21 (the shape of the main surface 21a) is a rectangle, and a plurality of third pads (third electrode pads) 21c formed on the main surface 21a are formed on the main surface 21a as shown in FIG. It is arranged along the long side. That is, the plurality of third pads 21c are arranged at the central portion of the main surface 21a of the SDRAM 21 in the direction along the first side 2m of the first wiring substrate 2 (the central portion in the width direction of the rectangular main surface 21a of the SDRAM 21). They are arranged side by side in the direction along the two sides 2n, which is a so-called center pad arrangement. At this time, the center pad arrangement may be such that the plurality of third pads 21c are composed of one row or plural rows.

さらに、ＳＤＲＡＭ２１の主面２１ａに形成された複数の第３パッド２１ｃが、複数のワイヤ３によって第１配線基板２の主面２ａの複数の第３ボンディングリード（電極）２ｐに電気的に接続されている。   Further, the plurality of third pads 21 c formed on the main surface 21 a of the SDRAM 21 are electrically connected to the plurality of third bonding leads (electrodes) 2 p on the main surface 2 a of the first wiring substrate 2 by the plurality of wires 3. ing.

その際、複数のワイヤ３は、第１配線基板２の第１辺２ｍに沿った方向にワイヤリングされている。すなわち、ＳＤＲＡＭ２１の第３パッド２１ｃと第１配線基板２の第３ボンディングリード２ｐとを電気的に接続する複数のワイヤ３のそれぞれは、ＳＤＲＡＭ２１の短辺に沿って形成されている。   At that time, the plurality of wires 3 are wired in a direction along the first side 2 m of the first wiring board 2. That is, each of the plurality of wires 3 that electrically connect the third pad 21 c of the SDRAM 21 and the third bonding lead 2 p of the first wiring substrate 2 is formed along the short side of the SDRAM 21.

このようにＳＤＲＡＭ２１と接続する複数のワイヤ３をＳＤＲＡＭ２１の短辺（第１配線基板２の第１辺２ｍ）に沿ってワイヤリングすることで、複数のワイヤ３が第１封止体４を形成する際のレジン流動方向１０に沿ってワイヤリングされるため、レジン流れの妨害となることを低減できる。   Thus, the plurality of wires 3 connected to the SDRAM 21 are wired along the short side of the SDRAM 21 (the first side 2m of the first wiring substrate 2), so that the plurality of wires 3 form the first sealing body 4. Since it is wired along the resin flow direction 10 at the time, it is possible to reduce the obstruction of the resin flow.

これにより、ワイヤ剥離やボイドの形成等を低減することができる。   Thereby, wire peeling, formation of a void, etc. can be reduced.

すなわち、ＳＤＲＡＭ２１と接続する複数のワイヤ３は、樹脂モールドの際のレジン流動方向１０に沿ってワイヤリングすることが好ましく、特に、ＳＤＲＡＭ２１がセンタパッド配置の場合には、ワイヤ長が長くなるため、レジン流動方向１０に沿ってワイヤリングすることが、レジン流れの妨害に対してはより有効である。   That is, it is preferable to wire the plurality of wires 3 connected to the SDRAM 21 along the resin flow direction 10 during resin molding. In particular, when the SDRAM 21 has a center pad arrangement, the wire length becomes long. Wiring along the flow direction 10 is more effective against resin flow obstruction.

なお、本実施の形態２のＰＯＰ型半導体装置１９のその他の構造と、ＰＯＰ型半導体装置１９によって得られるその他の効果については、実施の形態１のＰＯＰ型半導体装置８のものと同様であるため、その重複説明は省略する。   The other structure of the POP type semiconductor device 19 of the second embodiment and the other effects obtained by the POP type semiconductor device 19 are the same as those of the POP type semiconductor device 8 of the first embodiment. The duplicate explanation is omitted.

次に、図４７及び図４８を用いて本実施の形態２の変形例について説明する。   Next, a modification of the second embodiment will be described with reference to FIGS.

図４７及び図４８に示すＰＯＰ型半導体装置１９は、下段側の第１半導体パッケージ７の第１配線基板２上に、コントローラチップ１及びＳＤＲＡＭ２１に加えてチップ部品２０が搭載されているものである。   The POP type semiconductor device 19 shown in FIGS. 47 and 48 has a chip component 20 mounted on the first wiring substrate 2 of the first semiconductor package 7 on the lower stage side in addition to the controller chip 1 and the SDRAM 21. .

すなわち、ＰＯＰ型半導体装置１９の下段側の第１半導体パッケージ７においては、コントローラチップ１またはＳＤＲＡＭ２１の隣にチップ部品２０を搭載してもよく、図４８に示すように、コントローラチップ１及びＳＤＲＡＭ２１とその周辺に搭載されたチップ部品２０も第１封止体４によって樹脂封止されている。   That is, in the first semiconductor package 7 on the lower side of the POP type semiconductor device 19, the chip component 20 may be mounted next to the controller chip 1 or the SDRAM 21. As shown in FIG. The chip component 20 mounted on the periphery thereof is also resin-sealed by the first sealing body 4.

なお、チップ部品２０は、例えば、抵抗、コイル（水晶振動子）、コンデンサ（キャパシタ、静電容量）等である。   The chip component 20 is, for example, a resistor, a coil (quartz crystal unit), a capacitor (capacitor, capacitance), or the like.

（実施の形態３）
図５０は本発明の実施の形態３の半導体装置における第１半導体パッケージの構造の一例を封止体を透過して示す平面図、図５１は図５０のＢ−Ｂ線に沿って切断した本発明の実施の形態３の半導体装置の構造の一例を示す断面図である。また、図５２は本発明の実施の形態３の半導体装置の第１変形例における第１半導体パッケージの構造を封止体を透過して示す平面図、図５３は図５２のＢ−Ｂ線に沿って切断した本発明の実施の形態３の半導体装置の第１変形例の構造を示す断面図、図５４は本発明の実施の形態３の半導体装置の第２変形例における第１半導体パッケージの構造を封止体を透過して示す平面図、図５５は図５４のＢ−Ｂ線に沿って切断した本発明の実施の形態３の半導体装置の第２変形例の構造を示す断面図である。さらに、図５６は図５５に示す半導体装置における第２半導体パッケージの構造を封止体を透過して示す平面図、図５７は図５５に示す半導体装置の裏面側の構造の一例を示す底面図である。 (Embodiment 3)
50 is a plan view showing an example of the structure of the first semiconductor package in the semiconductor device according to the third embodiment of the present invention through the sealing body, and FIG. 51 is a view cut along the line BB in FIG. It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 3 of invention. FIG. 52 is a plan view showing the structure of the first semiconductor package in the first modification of the semiconductor device according to the third embodiment of the present invention through the sealing body, and FIG. 53 is taken along the line BB in FIG. FIG. 54 is a cross-sectional view showing the structure of the first modification of the semiconductor device according to the third embodiment of the present invention, cut along, FIG. FIG. 55 is a cross-sectional view showing the structure of a second modification of the semiconductor device according to the third embodiment of the present invention, cut along the line BB in FIG. is there. 56 is a plan view showing the structure of the second semiconductor package in the semiconductor device shown in FIG. 55 through a sealing body, and FIG. 57 is a bottom view showing an example of the structure on the back surface side of the semiconductor device shown in FIG. It is.

図５０及び図５１に示す本実施の形態３の半導体装置は、実施の形態２と同様に、半導体パッケージを多段に積層した構造のＰＯＰ型半導体装置２２であり、下段側の第１半導体パッケージ７上に上段側の第２半導体パッケージ１７を積層したものである。   The semiconductor device according to the third embodiment shown in FIGS. 50 and 51 is a POP type semiconductor device 22 having a structure in which semiconductor packages are stacked in multiple stages, as in the second embodiment, and the first semiconductor package 7 on the lower stage side. The second semiconductor package 17 on the upper stage side is laminated on the top.

本実施の形態３のＰＯＰ型半導体装置２２は、上段側の第２半導体パッケージ１７の第２配線基板１２の実装強度を向上するための補強用ランド（第３ランド）２ｑが第１配線基板２に設けられているものである。   In the POP type semiconductor device 22 according to the third embodiment, the reinforcing land (third land) 2q for improving the mounting strength of the second wiring board 12 of the second semiconductor package 17 on the upper stage side is the first wiring board 2. Is provided.

すなわち、ＰＯＰ型半導体装置２２では、第１半導体パッケージ７に形成された第１封止体４が、コントローラチップ１を封止する第１封止部４ａと、第１辺２ｍに沿った方向の第１封止部４ａの両側に第１封止部４ａと一体で形成された第２封止部４ｂとから成り、第１配線基板２の主面２ａの第２封止部４ｂの第２辺２ｎに沿った方向の両側に第３ランドである補強用ランド２ｑが設けられている。図５０，図５１に示す第１半導体パッケージ７では、第１封止部４ａの周囲４箇所に補強用ランド２ｑが形成されている。４箇所に補強用ランド２ｑが形成され、これら補強用ランド２ｑも半田ボール１５を介して上段側の第２配線基板１２と接続されることで、上段側の第２配線基板１２の実装強度を向上することができる。   That is, in the POP type semiconductor device 22, the first sealing body 4 formed in the first semiconductor package 7 includes the first sealing portion 4 a that seals the controller chip 1 and the direction along the first side 2 m. The second sealing part 4b is formed integrally with the first sealing part 4a on both sides of the first sealing part 4a, and the second sealing part 4b of the main surface 2a of the first wiring board 2 is second. Reinforcing lands 2q that are third lands are provided on both sides in the direction along the side 2n. In the first semiconductor package 7 shown in FIGS. 50 and 51, reinforcing lands 2q are formed at four locations around the first sealing portion 4a. Reinforcing lands 2q are formed at four locations, and these reinforcing lands 2q are also connected to the second wiring board 12 on the upper stage side via the solder balls 15, thereby increasing the mounting strength of the second wiring board 12 on the upper stage side. Can be improved.

なお、補強用ランド２ｑは、信号用の伝達経路となる主面側ランド２ｅと第２封止部４ｂとの間に位置している。   The reinforcing land 2q is located between the main surface side land 2e serving as a signal transmission path and the second sealing portion 4b.

また、ＰＯＰ型半導体装置２２では、補強用ランド２ｑを回避するために、第２封止部４ｂの第２辺２ｎに沿った方向の幅は、第１封止部４ａの同方向の幅より狭く形成されている。   Moreover, in the POP type semiconductor device 22, in order to avoid the reinforcing land 2q, the width in the direction along the second side 2n of the second sealing portion 4b is larger than the width in the same direction of the first sealing portion 4a. It is narrowly formed.

すなわち、補強用ランド２ｑを回避するために、コントローラチップ１の周囲に形成された第２封止部４ｂの第２辺２ｎに沿った方向の幅は、コントローラチップ１を封止する第１封止部４ａの同方向の幅より狭くなっている。   That is, in order to avoid the reinforcing land 2q, the width in the direction along the second side 2n of the second sealing portion 4b formed around the controller chip 1 is the first sealing for sealing the controller chip 1. The stop portion 4a is narrower than the width in the same direction.

ただし、図５１に示すように、第２封止部４ｂの厚さは、第１封止部４ａの厚さより厚くなっている。   However, as shown in FIG. 51, the thickness of the second sealing portion 4b is thicker than the thickness of the first sealing portion 4a.

つまり、補強用ランド２ｑを回避した分、第１封止部４ａの外側の第２封止部４ｂは第１封止部４ａより幅が狭いが、高さは第１封止部４ａより高い。   That is, the second sealing portion 4b outside the first sealing portion 4a is narrower than the first sealing portion 4a, but the height is higher than the first sealing portion 4a, as much as the reinforcing land 2q is avoided. .

これにより、第１封止部４ａと第２封止部４ｂとで、樹脂モールディング工程での樹脂供給時の樹脂の流速を変えることなく安定した速度で樹脂を流すことができる。   Accordingly, the first sealing portion 4a and the second sealing portion 4b can cause the resin to flow at a stable speed without changing the flow rate of the resin when the resin is supplied in the resin molding process.

本実施の形態３のＰＯＰ型半導体装置２２のその他の構造と、ＰＯＰ型半導体装置２２によって得られるその他の効果については、実施の形態２のＰＯＰ型半導体装置１９のものと同様であるため、その重複説明は省略する。   The other structure of the POP type semiconductor device 22 of the third embodiment and the other effects obtained by the POP type semiconductor device 22 are the same as those of the POP type semiconductor device 19 of the second embodiment. A duplicate description is omitted.

次に、本実施の形態３の変形例について説明する。   Next, a modification of the third embodiment will be described.

図５２及び図５３に示す本実施の形態３の第１変形例は、第２封止部４ｂによって、第１半導体パッケージ７の第１配線基板２の主面２ａ上に搭載されたチップ部品２０を封止している構造を示している。   The first modification of the third embodiment shown in FIGS. 52 and 53 is the chip component 20 mounted on the main surface 2a of the first wiring substrate 2 of the first semiconductor package 7 by the second sealing portion 4b. The structure which has sealed is shown.

すなわち、チップ部品２０は、コントローラチップ１やＳＤＲＡＭ２１より厚さ（実装高さ）が厚い（高い）場合が多く、高さが高いチップ部品２０であっても第２封止部４ｂによって封止することができる。   In other words, the chip component 20 is often thicker (higher) than the controller chip 1 or the SDRAM 21, and even the chip component 20 having a high height is sealed by the second sealing portion 4b. be able to.

次に、図５４〜図５７に示す本実施の形態３の第２変形例について説明する。   Next, a second modification of the third embodiment shown in FIGS. 54 to 57 will be described.

前記第１変形例で説明したように、第２封止部４ｂは第１封止部４ａより厚さが厚い。言い換えると、第１封止部４ａの厚さは第２封止部４ｂの厚さよりも薄くなっている。   As described in the first modification, the second sealing portion 4b is thicker than the first sealing portion 4a. In other words, the thickness of the first sealing portion 4a is thinner than the thickness of the second sealing portion 4b.

すなわち、第１封止部４ａと第２封止部４ｂから成る第１封止体４の中央付近に相当する第１封止部４ａの高さは、その外側の第２封止部４ｂより低い。   That is, the height of the first sealing portion 4a corresponding to the vicinity of the center of the first sealing body 4 including the first sealing portion 4a and the second sealing portion 4b is higher than that of the second sealing portion 4b on the outer side. Low.

そこで、図５６に示す第２配線基板１２の平面方向の大きさが、図５４に示す第１配線基板２の平面方向の大きさより小さい場合に、図５５に示すように第２配線基板１２の裏面１２ｂは、第１封止部４ａより高く、かつ第２封止部４ｂより低い位置に配置されている。   Therefore, when the size of the second wiring board 12 shown in FIG. 56 is smaller than the size of the first wiring board 2 shown in FIG. 54 in the planar direction, the second wiring board 12 of FIG. The back surface 12b is arranged at a position higher than the first sealing portion 4a and lower than the second sealing portion 4b.

つまり、上段側の第２配線基板１２の外形寸法が、下段側の第１配線基板２の外形寸法よりも小さい場合（図５６に示すように、第２チップ搭載領域１２ｄのサイズが第２配線基板１２の主面２ａのサイズとほぼ同じ場合）、図５５に示すように、第１封止部４ａの厚さを第２封止部４ｂの厚さよりも薄くして凹状の段差部４ｃを形成しておくことで、凹状の段差部４ｃに第２配線基板１２を配置することができ、完成したＰＯＰ型半導体装置２２の実装高さを低減することができる。   That is, when the outer dimension of the second wiring board 12 on the upper stage side is smaller than the outer dimension of the first wiring board 2 on the lower stage side (as shown in FIG. 56, the size of the second chip mounting area 12d is the second wiring board). As shown in FIG. 55, the thickness of the first sealing portion 4a is made thinner than the thickness of the second sealing portion 4b to form a concave stepped portion 4c. By forming it, the second wiring board 12 can be disposed in the concave stepped portion 4c, and the mounting height of the completed POP type semiconductor device 22 can be reduced.

また、本実施の形態３においては、補強用ランド２ｑを設けない場合であっても（補強用ランド２ｑの有無に係わらず）、第２封止部４ｂの厚さを第１封止部４ａの厚さよりも厚くすることで、高さが高いチップ部品２０でも第２封止部４ｂによって封止することができる。   In the third embodiment, even if the reinforcing land 2q is not provided (regardless of the presence or absence of the reinforcing land 2q), the thickness of the second sealing portion 4b is set to the first sealing portion 4a. By making the thickness thicker than this, even the chip component 20 having a high height can be sealed by the second sealing portion 4b.

（実施の形態４）
図５８は本発明の実施の形態４の半導体装置の第１半導体パッケージの組み立てにおける樹脂モールディング後の構造を示す拡大部分平面図、図５９は図５８のＡ−Ａ線に沿って切断した本発明の実施の形態４の半導体装置の構造を示す断面図である。 (Embodiment 4)
58 is an enlarged partial plan view showing the structure after resin molding in the assembly of the first semiconductor package of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 59 is the present invention cut along the line AA in FIG. It is sectional drawing which shows the structure of the semiconductor device of this Embodiment 4.

図５８及び図５９に示す本実施の形態４の半導体装置は、実施の形態３と同様に、半導体パッケージを多段に積層した構造のＰＯＰ型半導体装置２３であり、下段側の第１半導体パッケージ７上に上段側の第２半導体パッケージ１７を積層したものである。   The semiconductor device of the fourth embodiment shown in FIGS. 58 and 59 is a POP type semiconductor device 23 having a structure in which semiconductor packages are stacked in multiple stages, as in the third embodiment, and the first semiconductor package 7 on the lower stage side. The second semiconductor package 17 on the upper stage side is laminated on the top.

本実施の形態４のＰＯＰ型半導体装置２３は、下段側の第１半導体パッケージ７の第１配線基板２の強度を向上するための第３封止部４ｄが形成されているものである。   The POP type semiconductor device 23 of the fourth embodiment is formed with a third sealing portion 4d for improving the strength of the first wiring board 2 of the first semiconductor package 7 on the lower stage side.

すなわち、下段側の第１半導体パッケージ７において、第１配線基板２の主面２ａ上の複数の主面側ランド２ｅ列の外側に、第１辺２ｍに沿って第３封止部４ｄが形成されており、上段側の第２半導体パッケージ１７の第２配線基板１２の裏面１２ｂの端部が第３封止部４ｄによって支持されている。   That is, in the first semiconductor package 7 on the lower stage side, the third sealing portion 4d is formed along the first side 2m on the outside of the plurality of main surface side lands 2e on the main surface 2a of the first wiring board 2. The end of the back surface 12b of the second wiring substrate 12 of the second semiconductor package 17 on the upper stage side is supported by the third sealing portion 4d.

すなわち、第１半導体パッケージ７の第１配線基板２の主面２ａ上の複数の主面側ランド２ｅ列それぞれの外側に、前記主面側ランド２ｅ列に沿って細長い第３封止部４ｄが形成されており、上段側の第２配線基板１２の裏面１２ｂの端部が第３封止部４ｄによって支持されている。   That is, on the outer side of each of the plurality of main surface side lands 2e on the main surface 2a of the first wiring board 2 of the first semiconductor package 7, the third sealing portion 4d that is elongated along the main surface side land 2e row is provided. The end of the back surface 12b of the second wiring board 12 on the upper stage side is supported by the third sealing portion 4d.

これにより、下段側の第１配線基板２の強度を向上させることができる。   Thereby, the intensity | strength of the 1st wiring board 2 of the lower stage can be improved.

なお、下段側の第１配線基板２に図５３に示すようなチップ部品２０を搭載する場合、第３封止部４ｄによってチップ部品２０を封止してもよい。   When the chip component 20 as shown in FIG. 53 is mounted on the first wiring board 2 on the lower side, the chip component 20 may be sealed by the third sealing portion 4d.

また、第３封止部４ｄの厚さを、コントローラチップ１を封止する第１封止体４（第１封止部４ａ、第２封止部４ｂ）の厚さよりも厚くする。言い換えると、コントローラチップ１を封止する第１封止体４の厚さを、第３封止部４ｄの厚さより薄くして、第１封止体４と第２配線基板１２の間に隙間２４を形成しておくことで、下段側の第１配線基板２が凸状に反った場合でも、第１封止体４がその上方の第２配線基板１２を押し上げることを防ぐことができる。   Further, the thickness of the third sealing portion 4d is made thicker than the thickness of the first sealing body 4 (the first sealing portion 4a and the second sealing portion 4b) that seals the controller chip 1. In other words, the thickness of the first sealing body 4 that seals the controller chip 1 is made thinner than the thickness of the third sealing portion 4d, so that there is a gap between the first sealing body 4 and the second wiring board 12. By forming 24, the first sealing body 4 can be prevented from pushing up the second wiring board 12 thereabove even when the first wiring board 2 on the lower stage side warps in a convex shape.

また、上段側の第２配線基板１２が第３封止部４ｄによって支持されているため、上段側からの応力に対応することができ、第１半導体パッケージ７にクラックが形成されることを防止できる。さらに、上段側の第２半導体パッケージ１７が第３封止部４ｄによって支持されているため、半田ボール１５の潰れを低減することができる。   Further, since the second wiring board 12 on the upper stage side is supported by the third sealing portion 4d, it is possible to cope with the stress from the upper stage side and prevent the first semiconductor package 7 from being cracked. it can. Furthermore, since the second semiconductor package 17 on the upper stage side is supported by the third sealing portion 4d, the collapse of the solder balls 15 can be reduced.

これにより、半田ボール１５間のショートを防ぐことができる。   Thereby, a short circuit between the solder balls 15 can be prevented.

また、半田ボール１５が潰れることを低減できるため、予め、半田ボール１５の径を小さくすることができる。すなわち、下段側の第１配線基板２と上段側の第２配線基板１２の距離を短くすることができ、半田ボール１５の大きさを小さくするとともに、ボールの取り付けピッチを小さくして半田ボール１５の設置数を増やすことができる。   Moreover, since it can reduce that the solder ball 15 is crushed, the diameter of the solder ball 15 can be reduced in advance. That is, the distance between the lower first wiring board 2 and the upper second wiring board 12 can be shortened, the solder balls 15 can be reduced in size, and the ball mounting pitch can be reduced. The number of installations can be increased.

本実施の形態４のＰＯＰ型半導体装置２３のその他の構造と、ＰＯＰ型半導体装置２３によって得られるその他の効果については、実施の形態３のＰＯＰ型半導体装置２２のものと同様であるため、その重複説明は省略する。   The other structure of the POP type semiconductor device 23 of the fourth embodiment and the other effects obtained by the POP type semiconductor device 23 are the same as those of the POP type semiconductor device 22 of the third embodiment. A duplicate description is omitted.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

例えば、前記実施の形態１〜４では、上段側の第２半導体パッケージ１７に搭載される第２半導体チップがメモリチップ（不揮発性メモリ１１）であり、このメモリチップが１つ搭載されている場合について説明したが、上段側の第２半導体パッケージ１７においても複数のメモリチップを積層して搭載してもよい。その際、積層するメモリチップの種類を１種類にすることにより、端子を共用して使用することができ、端子数を増やすことなく複数のメモリチップを積層することができる。   For example, in the first to fourth embodiments, the second semiconductor chip mounted on the second semiconductor package 17 on the upper stage is a memory chip (nonvolatile memory 11), and one memory chip is mounted. As described above, a plurality of memory chips may be stacked and mounted on the second semiconductor package 17 on the upper stage side. At that time, by using one type of memory chip to be stacked, the terminals can be shared and used, and a plurality of memory chips can be stacked without increasing the number of terminals.

また、下段側の第１半導体パッケージ７と上段側の第２半導体パッケージ１７の平面方向の大きさは、同じであっても、異なっていてもどちらでもよい。   Further, the size in the planar direction of the first semiconductor package 7 on the lower stage side and the second semiconductor package 17 on the upper stage side may be the same or different.

本発明は、複数の半導体チップを有する電子装置に好適である。   The present invention is suitable for an electronic device having a plurality of semiconductor chips.

本発明の実施の形態１の半導体装置の構造の一例を示す平面図である。It is a top view which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. 図１に示す半導体装置の裏面側の構造の一例を示す底面図である。FIG. 2 is a bottom view illustrating an example of a structure on a back surface side of the semiconductor device illustrated in FIG. 1. 図２のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図２のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図３のＡ部の構造の一例を示す拡大部分断面図である。FIG. 4 is an enlarged partial cross-sectional view showing an example of the structure of part A in FIG. 3. 図１に示す半導体装置の第１半導体パッケージの構造の一例を示す平面図である。FIG. 2 is a plan view illustrating an example of a structure of a first semiconductor package of the semiconductor device illustrated in FIG. 1. 図６に示す第１半導体パッケージの構造を封止体を透過して示す平面図である。FIG. 7 is a plan view showing the structure of the first semiconductor package shown in FIG. 6 through a sealing body. 図６に示す第１半導体パッケージの裏面側の構造を示す底面図である。FIG. 7 is a bottom view showing the structure on the back surface side of the first semiconductor package shown in FIG. 6. 図１に示す半導体装置の第２半導体パッケージの構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the 2nd semiconductor package of the semiconductor device shown in FIG. 図９に示す第２半導体パッケージの裏面側の構造を示す底面図である。FIG. 10 is a bottom view showing the structure on the back surface side of the second semiconductor package shown in FIG. 9. 図１に示す半導体装置の回路ブロック構成の一例を示す回路ブロック図である。FIG. 2 is a circuit block diagram illustrating an example of a circuit block configuration of the semiconductor device illustrated in FIG. 1. 図１に示す半導体装置の第１半導体パッケージの組み立てで用いられる配線基板の構造の一例を示す平面図である。FIG. 2 is a plan view showing an example of a structure of a wiring board used in assembling a first semiconductor package of the semiconductor device shown in FIG. 1. 図１２に示す配線基板の裏面側の構造の一例を示す裏面図である。FIG. 13 is a back view showing an example of the structure on the back side of the wiring board shown in FIG. 12. 図１２のＡ部の構造を示す拡大部分平面図である。FIG. 13 is an enlarged partial plan view showing the structure of part A in FIG. 12. 図１４のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図１４のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図６に示す第１半導体パッケージの組み立てにおけるダイボンディング後の構造の一例を示す部分拡大平面図である。FIG. 7 is a partially enlarged plan view showing an example of a structure after die bonding in the assembly of the first semiconductor package shown in FIG. 6. 図１７のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図１７のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図６に示す第１半導体パッケージの組み立てにおけるワイヤボンディング後の構造の一例を示す部分拡大平面図である。FIG. 7 is a partially enlarged plan view showing an example of a structure after wire bonding in the assembly of the first semiconductor package shown in FIG. 6. 図２０のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. 図２０のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図６に示す第１半導体パッケージの組み立てにおける樹脂モールディング後の構造の一例を示す部分拡大平面図である。FIG. 7 is a partially enlarged plan view showing an example of a structure after resin molding in the assembly of the first semiconductor package shown in FIG. 6. 図２３のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図２３のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図１３のＡ部におけるボールマウント後の構造の一例を示す裏面図である。It is a back view which shows an example of the structure after the ball mount in the A section of FIG. 図２６のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. 図１に示す半導体装置の第２半導体パッケージの組み立てで用いられる配線基板の構造の一例を示す平面図である。It is a top view which shows an example of the structure of the wiring board used by the assembly of the 2nd semiconductor package of the semiconductor device shown in FIG. 図２８に示す配線基板の裏面側の構造の一例を示す裏面図である。FIG. 29 is a back view showing an example of the structure on the back side of the wiring board shown in FIG. 28. 図２８のＡ部の構造を示す拡大部分平面図である。FIG. 29 is an enlarged partial plan view showing the structure of part A in FIG. 28. 図３０のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図３０のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図９に示す第２半導体パッケージの組み立てにおけるダイボンディング後の構造の一例を示す部分拡大平面図である。FIG. 10 is a partially enlarged plan view showing an example of a structure after die bonding in the assembly of the second semiconductor package shown in FIG. 9. 図３３のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図３３のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図９に示す第２半導体パッケージの組み立てにおけるワイヤボンディング後の構造の一例を示す部分拡大平面図である。FIG. 10 is a partially enlarged plan view showing an example of a structure after wire bonding in the assembly of the second semiconductor package shown in FIG. 9. 図３６のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. 図３６のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図９に示す第１半導体パッケージの組み立てにおける樹脂モールディング後の構造の一例を示す部分拡大平面図である。FIG. 10 is a partially enlarged plan view showing an example of a structure after resin molding in the assembly of the first semiconductor package shown in FIG. 9. 図３９のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図３９のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 図２９のＡ部におけるボールマウント後の構造の一例を示す裏面図である。FIG. 30 is a back view showing an example of a structure after ball mounting in the A part of FIG. 29. 図４２のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. 図４２のＢ−Ｂ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. 本発明の実施の形態２の半導体装置における第１半導体パッケージの構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the 1st semiconductor package in the semiconductor device of Embodiment 2 of this invention. 図４５のＢ−Ｂ線に沿って切断した本発明の実施の形態２の半導体装置の構造の一例を示す断面図である。FIG. 46 is a cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention cut along the line BB in FIG. 45. 本発明の実施の形態２の半導体装置の第１変形例における第１半導体パッケージの構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the 1st semiconductor package in the 1st modification of the semiconductor device of Embodiment 2 of this invention through a sealing body. 図４７のＢ−Ｂ線に沿って切断した本発明の実施の形態２の半導体装置の第１変形例の構造を示す断面図である。FIG. 48 is a cross-sectional view showing a structure of a first modification example of the semiconductor device according to the second embodiment of the present invention, cut along line BB in FIG. 47; 図４６に示す半導体装置の回路ブロック構成の一例を示す回路ブロック図である。47 is a circuit block diagram showing an example of a circuit block configuration of the semiconductor device shown in FIG. 46. FIG. 本発明の実施の形態３の半導体装置における第１半導体パッケージの構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the 1st semiconductor package in the semiconductor device of Embodiment 3 of this invention. 図５０のＢ−Ｂ線に沿って切断した本発明の実施の形態３の半導体装置の構造の一例を示す断面図である。FIG. 52 is a cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment of the present invention cut along the line BB in FIG. 50. 本発明の実施の形態３の半導体装置の第１変形例における第１半導体パッケージの構造を封止体を透過して示す平面図である。It is a top view which permeate | transmits the sealing body and shows the structure of the 1st semiconductor package in the 1st modification of the semiconductor device of Embodiment 3 of this invention. 図５２のＢ−Ｂ線に沿って切断した本発明の実施の形態３の半導体装置の第１変形例の構造を示す断面図である。FIG. 53 is a cross sectional view showing the structure of the first modification example of the semiconductor device according to the third embodiment of the present invention, cut along the line BB in FIG. 52; 本発明の実施の形態３の半導体装置の第２変形例における第１半導体パッケージの構造を封止体を透過して示す平面図である。It is a top view which permeate | transmits the sealing body and shows the structure of the 1st semiconductor package in the 2nd modification of the semiconductor device of Embodiment 3 of this invention. 図５４のＢ−Ｂ線に沿って切断した本発明の実施の形態３の半導体装置の第２変形例の構造を示す断面図である。FIG. 55 is a cross-sectional view showing a structure of a second modification example of the semiconductor device according to the third embodiment of the present invention cut along the line BB in FIG. 54. 図５５に示す半導体装置における第２半導体パッケージの構造を封止体を透過して示す平面図である。FIG. 56 is a plan view showing a structure of a second semiconductor package in the semiconductor device shown in FIG. 55 through a sealing body. 図５５に示す半導体装置の裏面側の構造の一例を示す底面図である。FIG. 56 is a bottom view showing an example of the structure on the back surface side of the semiconductor device shown in FIG. 55; 本発明の実施の形態４の半導体装置の第１半導体パッケージの組み立てにおける樹脂モールディング後の構造の一例を示す拡大部分平面図である。It is an enlarged partial top view which shows an example of the structure after the resin molding in the assembly of the 1st semiconductor package of the semiconductor device of Embodiment 4 of this invention. 図５８のＡ−Ａ線に沿って切断した本発明の実施の形態４の半導体装置の構造の一例を示す断面図である。FIG. 59 is a cross-sectional view showing an example of the structure of the semiconductor device according to the fourth embodiment of the present invention cut along line AA in FIG. 58;

符号の説明Explanation of symbols

１ コントローラチップ（第１半導体チップ）
１ａ 主面（第１チップ主面）
１ｂ 裏面（第１チップ裏面）
１ｃ 第１パッド（第１電極パッド）
２ 第１配線基板
２ａ 主面（第１基板主面）
２ｂ 裏面（第１基板裏面）
２ｃ 第１ボンディングリード
２ｄ 第１チップ搭載領域
２ｅ 主面側ランド（第１基板主面側ランド）
２ｆ 裏面側ランド（第１基板裏面側ランド）
２ｇ コア材
２ｈ ソルダレジスト膜
２ｉ 配線部
２ｊ スルーホール配線
２ｋ モールド領域
２ｍ 第１辺
２ｎ 第２辺
２ｐ 第３ボンディングリード
２ｑ 補強用ランド（第３ランド）
３ ワイヤ（第１導電性部材）
４ 第１封止体
４ａ 第１封止部
４ｂ 第２封止部
４ｃ 段差部
４ｄ 第３封止部
５ 半田ボール（第１外部端子）
６ ダイボンド材
７ 第１半導体パッケージ
８ ＰＯＰ型半導体装置
９ マトリクス基板（第１配線基板）
９ａ デバイス領域
９ｂ マトリクス基板（第２配線基板）
９ｃ デバイス領域
９ｄ ゲート部
１０ レジン流動方向
１１ 不揮発性メモリ（第２半導体チップ）
１１ａ 主面（第２チップ主面）
１１ｂ 裏面（第２チップ裏面）
１１ｃ 第２パッド（第２電極パッド）
１２ 第２配線基板
１２ａ 主面（第２基板主面）
１２ｂ 裏面（第２基板裏面）
１２ｃ 第２ボンディングリード
１２ｄ 第２チップ搭載領域
１２ｆ 裏面側ランド（第２基板裏面側ランド）
１２ｇ コア材
１２ｈ ソルダレジスト膜
１２ｉ 配線部
１２ｊ スルーホール配線
１３ ワイヤ（第２導電性部材）
１４ 第２封止体
１５ 半田ボール（第２外部端子）
１６ ダイボンド材
１７ 第２半導体パッケージ
１８ 封止体
１９ ＰＯＰ型半導体装置
２０ チップ部品
２１ ＳＤＲＡＭ（第３半導体チップ）
２１ａ 主面（第３チップ主面）
２１ｂ 裏面
２１ｃ 第３パッド（第３電極パッド）
２２ ＰＯＰ型半導体装置
２３ ＰＯＰ型半導体装置
２４ 隙間 1 Controller chip (first semiconductor chip)
1a Main surface (first chip main surface)
1b Back side (first chip back side)
1c First pad (first electrode pad)
2 1st wiring board 2a principal surface (first substrate principal surface)
2b Back side (back side of first substrate)
2c First bonding lead 2d First chip mounting area 2e Main surface side land (first substrate main surface side land)
2f Back side land (1st board back side land)
2g Core material 2h Solder resist film 2i Wiring part 2j Through-hole wiring 2k Mold area 2m First side 2n Second side 2p Third bonding lead 2q Reinforcing land (third land)
3 Wire (first conductive member)
4 1st sealing body 4a 1st sealing part 4b 2nd sealing part 4c Step part 4d 3rd sealing part 5 Solder ball (1st external terminal)
6 Die bond material 7 First semiconductor package 8 POP type semiconductor device 9 Matrix substrate (first wiring substrate)
9a Device region 9b Matrix substrate (second wiring substrate)
9c Device region 9d Gate portion 10 Resin flow direction 11 Non-volatile memory (second semiconductor chip)
11a Main surface (second chip main surface)
11b Back (second chip back)
11c 2nd pad (2nd electrode pad)
12 Main surface of second wiring substrate 12a (second substrate main surface)
12b Back surface (second substrate back surface)
12c Second bonding lead 12d Second chip mounting area 12f Back side land (second substrate back side land)
12g Core material 12h Solder resist film 12i Wiring part 12j Through-hole wiring 13 Wire (second conductive member)
14 Second encapsulant 15 Solder ball (second external terminal)
16 Die Bond Material 17 Second Semiconductor Package 18 Sealing Body 19 POP Type Semiconductor Device 20 Chip Component 21 SDRAM (Third Semiconductor Chip)
21a Main surface (third chip main surface)
21b Back surface 21c Third pad (third electrode pad)
22 POP type semiconductor device 23 POP type semiconductor device 24 Crevice

Claims (16)

複数の第１ボンディングリードが形成された第１チップ搭載領域を有する第１基板主面、前記複数の第１ボンディングリードのそれぞれと電気的に接続され、前記第１基板主面において前記第１チップ搭載領域の周囲に配置された複数の第１基板主面側ランド、前記第１基板主面とは反対側に位置する第１基板裏面、及び前記複数の第１ボンディングリードのそれぞれと電気的に接続され、前記第１基板裏面に配置された複数の第１基板裏面側ランドを有する第１配線基板と、
第１チップ主面、前記第１チップ主面に形成された複数の第１電極パッド、及び前記第１チップ主面とは反対側に位置する第１チップ裏面を有し、前記第１配線基板の前記第１チップ搭載領域上に搭載された第１半導体チップと、
前記第１半導体チップの前記複数の第１電極パッドと前記第１配線基板の前記複数の第１ボンディングリードとをそれぞれ電気的に接続する複数の第１導電性部材と、
前記複数の第１基板主面側ランドのそれぞれを露出するように、前記第１半導体チップ、前記複数の第１導電性部材及び前記第１配線基板の前記第１基板主面を封止する第１封止体と、
前記第１配線基板の前記複数の第１基板裏面側ランドのそれぞれに形成された複数の第１外部端子と、
複数の第２ボンディングリードが形成された第２チップ搭載領域を有する第２基板主面、前記第２基板主面とは反対側に位置する第２基板裏面、及び前記複数の第２ボンディングリードのそれぞれと電気的に接続され、前記第２基板裏面に配置された複数の第２基板裏面側ランドを有する第２配線基板と、
第２チップ主面、前記第２チップ主面に形成された複数の第２電極パッド、及び前記第２チップ主面とは反対側に位置する第２チップ裏面を有し、前記第２配線基板の前記第２チップ搭載領域上に搭載された第２半導体チップと、
前記第２半導体チップの前記複数の第２電極パッドと前記第２配線基板の前記複数の第２ボンディングリードとをそれぞれ電気的に接続する複数の第２導電性部材と、
前記第２半導体チップ、前記複数の第２導電性部材及び前記第２基板主面を封止する第２封止体と、
前記第２配線基板の前記複数の第２基板裏面側ランドのそれぞれに形成され、前記複数の第２基板裏面側ランドと前記複数の第１基板主面側ランドとをそれぞれ電気的に接続する複数の第２外部端子と、
を含み、
前記第１配線基板の前記第１基板主面の平面形状は、一対の第１辺と、前記第１辺と交差する一対の第２辺とを有する四角形から成り、
前記第１封止体は、平面視で、前記第１配線基板の前記第２辺と平行な第１辺を有し、前記第１封止体の前記第１辺と前記第１配線基板の前記第２辺の一部が重なり、前記第１配線基板の一方の前記第２辺の中央部から他方の前記第２辺の中央部に向かって形成されており、
前記複数の第１基板主面側ランドは、前記第１封止体と前記配線基板の前記第１辺との間に配置されていることを特徴とする半導体装置。 A first substrate main surface having a first chip mounting area on which a plurality of first bonding leads are formed, and electrically connected to each of the plurality of first bonding leads, and the first chip on the first substrate main surface. Each of the plurality of first substrate main surface side lands disposed around the mounting region, the first substrate back surface located on the opposite side of the first substrate main surface, and the plurality of first bonding leads A first wiring substrate connected and having a plurality of first substrate back side lands disposed on the back side of the first substrate;
A first chip substrate having a first chip main surface, a plurality of first electrode pads formed on the first chip main surface, and a first chip back surface located on the opposite side of the first chip main surface; A first semiconductor chip mounted on the first chip mounting region;
A plurality of first conductive members that electrically connect the plurality of first electrode pads of the first semiconductor chip and the plurality of first bonding leads of the first wiring substrate;
First sealing the first substrate main surface of the first semiconductor chip, the plurality of first conductive members, and the first wiring substrate so as to expose each of the plurality of first substrate main surface side lands. 1 sealing body;
A plurality of first external terminals formed on each of the plurality of first substrate backside lands of the first wiring board;
A second substrate main surface having a second chip mounting region on which a plurality of second bonding leads are formed, a second substrate back surface located on the opposite side of the second substrate main surface, and the plurality of second bonding leads. A second wiring board electrically connected to each of the plurality of second wiring boards having a plurality of second board back side lands disposed on the back side of the second board;
A second chip substrate having a second chip main surface, a plurality of second electrode pads formed on the second chip main surface, and a second chip back surface located on the opposite side of the second chip main surface; A second semiconductor chip mounted on the second chip mounting region;
A plurality of second conductive members that electrically connect the plurality of second electrode pads of the second semiconductor chip and the plurality of second bonding leads of the second wiring board, respectively;
A second sealing body for sealing the second semiconductor chip, the plurality of second conductive members, and the second substrate main surface;
A plurality of second substrate back surface lands formed on each of the plurality of second substrate back surface lands, and electrically connecting the plurality of second substrate back surface lands and the plurality of first substrate main surface lands, respectively. A second external terminal of
Including
The planar shape of the first substrate main surface of the first wiring board is a quadrangle having a pair of first sides and a pair of second sides intersecting the first side,
The first sealing body has a first side parallel to the second side of the first wiring board in a plan view, and the first side of the first sealing body and the first wiring board A part of the second side overlaps, and is formed from a central part of one of the second sides of the first wiring substrate toward a central part of the other second side;
The plurality of first substrate main surface side lands are arranged between the first sealing body and the first side of the wiring substrate. 請求項１記載の半導体装置において、前記第１半導体チップは制御回路を有した半導体チップであり、前記第２半導体チップはメモリ回路を有した半導体チップであり、前記第２半導体チップは、前記第１半導体チップによって制御されることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the first semiconductor chip is a semiconductor chip having a control circuit, the second semiconductor chip is a semiconductor chip having a memory circuit, and the second semiconductor chip is the first semiconductor chip. A semiconductor device controlled by one semiconductor chip. 請求項２記載の半導体装置において、前記第１半導体チップが有する前記複数の第１電極パッドの数は、前記第２半導体チップが有する前記複数の第２電極パッドの数より多いことを特徴とする半導体装置。   3. The semiconductor device according to claim 2, wherein the number of the plurality of first electrode pads included in the first semiconductor chip is greater than the number of the plurality of second electrode pads included in the second semiconductor chip. Semiconductor device. 請求項１記載の半導体装置において、前記第１配線基板の前記第１基板主面上に、前記第２半導体チップのメモリ回路と異なったメモリ機能のメモリ回路を有する第３半導体チップが、前記第１辺に沿った方向の前記第１半導体チップの隣に搭載されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a third semiconductor chip having a memory circuit having a memory function different from that of the memory circuit of the second semiconductor chip is provided on the first substrate main surface of the first wiring substrate. A semiconductor device mounted next to the first semiconductor chip in a direction along one side. 請求項４記載の半導体装置において、前記第３半導体チップが有する複数の第３電極パッドの数は、前記第１半導体チップが有する前記複数の第１電極パッドの数より少ないことを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein the number of the plurality of third electrode pads included in the third semiconductor chip is smaller than the number of the plurality of first electrode pads included in the first semiconductor chip. apparatus. 請求項５記載の半導体装置において、前記第３半導体チップは、前記複数の第３電極パッドが複数のワイヤによって前記第１配線基板の前記第１基板主面の複数の第３ボンディングリードに電気的に接続されており、前記複数のワイヤは、前記第１辺に沿った方向にワイヤリングされていることを特徴とする半導体装置。   6. The semiconductor device according to claim 5, wherein in the third semiconductor chip, the plurality of third electrode pads are electrically connected to the plurality of third bonding leads on the first substrate main surface of the first wiring substrate by a plurality of wires. And the plurality of wires are wired in a direction along the first side. 請求項６記載の半導体装置において、前記第３半導体チップの前記複数の第３電極パッドは、前記第１辺に沿った方向の前記第３半導体チップの第３チップ主面の中央部に並んで配置されたセンタパッド配置であることを特徴とする半導体装置。   The semiconductor device according to claim 6, wherein the plurality of third electrode pads of the third semiconductor chip are arranged in a central portion of a third chip main surface of the third semiconductor chip in a direction along the first side. A semiconductor device having a center pad arrangement. 請求項１記載の半導体装置において、前記第１封止体は、前記第１半導体チップを封止する第１封止部と、前記第１辺に沿った方向の前記第１封止部の両側に前記第１封止部と一体で形成された第２封止部とから成り、前記第１配線基板の前記第１基板主面の前記第２封止部の前記第２辺に沿った方向の両側に第３ランドが設けられていることを特徴とする半導体装置。   The semiconductor device according to claim 1, wherein the first sealing body includes a first sealing portion that seals the first semiconductor chip, and both sides of the first sealing portion in a direction along the first side. And a second sealing portion formed integrally with the first sealing portion, and a direction along the second side of the second sealing portion of the first substrate main surface of the first wiring board. A semiconductor device, wherein third lands are provided on both sides of the semiconductor device. 請求項８記載の半導体装置において、前記第２封止部の前記第２辺に沿った方向の幅は、前記第１封止部の同方向の幅より狭いことを特徴とする半導体装置。   9. The semiconductor device according to claim 8, wherein a width of the second sealing portion in a direction along the second side is narrower than a width of the first sealing portion in the same direction. 請求項９記載の半導体装置において、前記第２封止部の厚さは、前記第１封止部の厚さより厚いことを特徴とする半導体装置。   10. The semiconductor device according to claim 9, wherein the thickness of the second sealing portion is thicker than the thickness of the first sealing portion. 請求項１０記載の半導体装置において、前記第２封止部は、前記第１配線基板の前記第１基板主面上に搭載されたチップ部品を封止していることを特徴とする半導体装置。   11. The semiconductor device according to claim 10, wherein the second sealing portion seals a chip component mounted on the first substrate main surface of the first wiring board. 請求項１０記載の半導体装置において、前記第２配線基板の平面方向の大きさが前記第１配線基板の平面方向の大きさより小さく、前記第２配線基板の前記第２基板裏面は、前記第１封止部より高く、かつ前記第２封止部より低い位置に配置されていることを特徴とする半導体装置。   11. The semiconductor device according to claim 10, wherein a size of the second wiring substrate in a planar direction is smaller than a size of the first wiring substrate in a planar direction, and the second substrate back surface of the second wiring substrate is the first substrate. A semiconductor device, wherein the semiconductor device is disposed at a position higher than a sealing portion and lower than the second sealing portion. 請求項１記載の半導体装置において、前記第１配線基板の前記第１基板主面上の前記複数の第１基板主面側ランド列の外側に、前記第１辺に沿って第３封止部が形成されており、前記第２配線基板の前記第２基板裏面の端部が前記第３封止部によって支持されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a third sealing portion is provided along the first side outside the plurality of first substrate main surface side land rows on the first substrate main surface of the first wiring substrate. The semiconductor device is characterized in that an end of the second substrate back surface of the second wiring substrate is supported by the third sealing portion. 請求項１３記載の半導体装置において、前記第３封止部の厚さは、前記第１封止部及び前記第２封止部の厚さより厚いことを特徴とする半導体装置。   14. The semiconductor device according to claim 13, wherein the thickness of the third sealing portion is thicker than the thickness of the first sealing portion and the second sealing portion. （ａ）複数の第１ボンディングリードが形成された第１チップ搭載領域を有する第１基板主面、前記複数の第１ボンディングリードのそれぞれと電気的に接続され、前記第１基板主面において前記第１チップ搭載領域の周囲に配置された複数の第１基板主面側ランド、前記第１基板主面とは反対側に位置する第１基板裏面、及び前記複数の第１ボンディングリードのそれぞれと電気的に接続され、前記第１基板裏面に配置された複数の第１基板裏面側ランドを有するデバイス形成領域が複数個形成された第１配線基板を準備する工程；
（ｂ）第１チップ主面、前記第１チップ主面に形成された複数の第１電極パッド、及び前記第１チップ主面とは反対側に位置する第１チップ裏面を有する複数の第１半導体チップを、前記第１配線基板の前記複数のデバイス形成領域のそれぞれの前記第１チップ搭載領域上に搭載する工程；
（ｃ）前記第１半導体チップの前記複数の第１電極パッドと前記第１配線基板の前記複数の第１ボンディングリードとを複数の第１導電性部材を介してそれぞれ電気的に接続する工程；
（ｄ）前記複数の第１基板主面側ランドのそれぞれを露出するように、前記複数の第１半導体チップ、前記複数の第１導電性部材及び前記第１配線基板の前記第１基板主面を樹脂で一括して封止する工程；
（ｅ）前記第１配線基板の前記複数の第１基板裏面側ランドのそれぞれに複数の第１外部端子を形成する工程；
（ｆ）第２基板主面上に第２半導体チップが搭載され、前記第２基板主面とは反対側に位置する第２基板裏面に複数の第２基板裏面側ランドが配置された第２配線基板を、複数の第２外部端子を介して前記第１配線基板上に搭載し、前記複数の第１基板主面側ランドと前記複数の第２基板裏面側ランドとをそれぞれ電気的に接続する工程；
を含み、
前記第１配線基板の前記第１基板主面の平面形状は、一対の第１辺と、前記第１辺と交差する一対の第２辺とを有する四角形から成り、
前記複数の第１基板主面側ランドは、前記樹脂が供給される領域と前記配線基板の前記第１辺との間に配置されており、
前記（ｄ）工程では、前記第１配線基板の一方の前記第２辺の中央部から他方の前記第２辺の中央部に向かって前記樹脂を供給し、封止体を形成することを特徴とする半導体装置の製造方法。 (A) a first substrate main surface having a first chip mounting area on which a plurality of first bonding leads are formed, and electrically connected to each of the plurality of first bonding leads, A plurality of first substrate main surface side lands arranged around the first chip mounting region, a first substrate back surface located on the opposite side of the first substrate main surface, and the plurality of first bonding leads, respectively. Preparing a first wiring board electrically connected and having a plurality of device forming regions each having a plurality of first substrate back side lands arranged on the back side of the first substrate;
(B) A plurality of first chips having a first chip main surface, a plurality of first electrode pads formed on the first chip main surface, and a first chip back surface located on the opposite side of the first chip main surface. Mounting a semiconductor chip on the first chip mounting region of each of the plurality of device forming regions of the first wiring board;
(C) electrically connecting the plurality of first electrode pads of the first semiconductor chip and the plurality of first bonding leads of the first wiring substrate via a plurality of first conductive members;
(D) The first substrate main surface of the plurality of first semiconductor chips, the plurality of first conductive members, and the first wiring substrate so as to expose each of the plurality of first substrate main surface side lands. A step of collectively sealing with a resin;
(E) forming a plurality of first external terminals on each of the plurality of first substrate backside lands of the first wiring board;
(F) A second semiconductor chip is mounted on the second substrate main surface, and a plurality of second substrate back surface lands are arranged on the second substrate back surface located on the opposite side of the second substrate main surface. A wiring board is mounted on the first wiring board via a plurality of second external terminals, and the plurality of first board main surface side lands and the plurality of second board back surface side lands are electrically connected to each other. The step of:
Including
The planar shape of the first substrate main surface of the first wiring board is a quadrangle having a pair of first sides and a pair of second sides intersecting the first side,
The plurality of first substrate main surface side lands are arranged between a region to which the resin is supplied and the first side of the wiring substrate,
In the step (d), the resin is supplied from the central part of one of the second sides of the first wiring board toward the central part of the other second side to form a sealing body. A method for manufacturing a semiconductor device. 請求項１５記載の半導体装置の製造方法において、前記（ｆ）工程で、予め前記第２基板裏面側ランドに設けられた前記複数の第２外部端子を、前記第１配線基板の前記複数の第１基板主面側ランド上に配置した後、前記複数の第１基板主面側ランドと前記複数の第２基板裏面側ランドとを前記複数の第２外部端子を介して電気的に接続することを特徴とする半導体装置の製造方法。   16. The method of manufacturing a semiconductor device according to claim 15, wherein in the step (f), the plurality of second external terminals provided in advance on the second substrate rear surface side land are connected to the plurality of second terminals of the first wiring substrate. After disposing on one substrate main surface side land, the plurality of first substrate main surface side lands and the plurality of second substrate back surface side lands are electrically connected via the plurality of second external terminals. A method of manufacturing a semiconductor device.
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