JP5259369B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5259369B2 JP5259369B2 JP2008319938A JP2008319938A JP5259369B2 JP 5259369 B2 JP5259369 B2 JP 5259369B2 JP 2008319938 A JP2008319938 A JP 2008319938A JP 2008319938 A JP2008319938 A JP 2008319938A JP 5259369 B2 JP5259369 B2 JP 5259369B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- main surface
- chip
- semiconductor device
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 332
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000007789 sealing Methods 0.000 claims abstract description 153
- 239000000758 substrate Substances 0.000 claims abstract description 137
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000015654 memory Effects 0.000 claims description 53
- 239000011347 resin Substances 0.000 claims description 49
- 229920005989 resin Polymers 0.000 claims description 49
- 230000006386 memory function Effects 0.000 claims description 2
- 238000000465 moulding Methods 0.000 abstract description 19
- 229910000679 solder Inorganic materials 0.000 description 32
- 230000004048 modification Effects 0.000 description 19
- 238000012986 modification Methods 0.000 description 19
- 230000003014 reinforcing effect Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000012466 permeate Substances 0.000 description 6
- 239000011162 core material Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001151 other effect Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1076—Shape of the containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は本発明の実施の形態1の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の裏面側の構造の一例を示す底面図、図3は図2のA−A線に沿って切断した構造の一例を示す断面図、図4は図2のB−B線に沿って切断した構造の一例を示す断面図、図5は図3のA部の構造の一例を示す拡大部分断面図である。また、図6は図1に示す半導体装置の第1半導体パッケージの構造の一例を示す平面図、図7は図6に示す第1半導体パッケージの構造を封止体を透過して示す平面図、図8は図6に示す第1半導体パッケージの裏面側の構造を示す底面図、図9は図1に示す半導体装置の第2半導体パッケージの構造の一例を封止体を透過して示す平面図、図10は図9に示す第2半導体パッケージの裏面側の構造を示す底面図である。さらに、図11は図1に示す半導体装置の回路ブロック構成の一例を示す回路ブロック図である。
図45は本発明の実施の形態2の半導体装置における第1半導体パッケージの構造の一例を封止体を透過して示す平面図、図46は図45のB−B線に沿って切断した本発明の実施の形態2の半導体装置の構造の一例を示す断面図である。また、図47は本発明の実施の形態2の半導体装置の第1変形例における第1半導体パッケージの構造の一例を封止体を透過して示す平面図、図48は図47のB−B線に沿って切断した本発明の実施の形態2の半導体装置の第1変形例の構造を示す断面図、図49は図46に示す半導体装置の回路ブロック構成の一例を示す回路ブロック図である。
図50は本発明の実施の形態3の半導体装置における第1半導体パッケージの構造の一例を封止体を透過して示す平面図、図51は図50のB−B線に沿って切断した本発明の実施の形態3の半導体装置の構造の一例を示す断面図である。また、図52は本発明の実施の形態3の半導体装置の第1変形例における第1半導体パッケージの構造を封止体を透過して示す平面図、図53は図52のB−B線に沿って切断した本発明の実施の形態3の半導体装置の第1変形例の構造を示す断面図、図54は本発明の実施の形態3の半導体装置の第2変形例における第1半導体パッケージの構造を封止体を透過して示す平面図、図55は図54のB−B線に沿って切断した本発明の実施の形態3の半導体装置の第2変形例の構造を示す断面図である。さらに、図56は図55に示す半導体装置における第2半導体パッケージの構造を封止体を透過して示す平面図、図57は図55に示す半導体装置の裏面側の構造の一例を示す底面図である。
図58は本発明の実施の形態4の半導体装置の第1半導体パッケージの組み立てにおける樹脂モールディング後の構造を示す拡大部分平面図、図59は図58のA−A線に沿って切断した本発明の実施の形態4の半導体装置の構造を示す断面図である。
1a 主面(第1チップ主面)
1b 裏面(第1チップ裏面)
1c 第1パッド(第1電極パッド)
2 第1配線基板
2a 主面(第1基板主面)
2b 裏面(第1基板裏面)
2c 第1ボンディングリード
2d 第1チップ搭載領域
2e 主面側ランド(第1基板主面側ランド)
2f 裏面側ランド(第1基板裏面側ランド)
2g コア材
2h ソルダレジスト膜
2i 配線部
2j スルーホール配線
2k モールド領域
2m 第1辺
2n 第2辺
2p 第3ボンディングリード
2q 補強用ランド(第3ランド)
3 ワイヤ(第1導電性部材)
4 第1封止体
4a 第1封止部
4b 第2封止部
4c 段差部
4d 第3封止部
5 半田ボール(第1外部端子)
6 ダイボンド材
7 第1半導体パッケージ
8 POP型半導体装置
9 マトリクス基板(第1配線基板)
9a デバイス領域
9b マトリクス基板(第2配線基板)
9c デバイス領域
9d ゲート部
10 レジン流動方向
11 不揮発性メモリ(第2半導体チップ)
11a 主面(第2チップ主面)
11b 裏面(第2チップ裏面)
11c 第2パッド(第2電極パッド)
12 第2配線基板
12a 主面(第2基板主面)
12b 裏面(第2基板裏面)
12c 第2ボンディングリード
12d 第2チップ搭載領域
12f 裏面側ランド(第2基板裏面側ランド)
12g コア材
12h ソルダレジスト膜
12i 配線部
12j スルーホール配線
13 ワイヤ(第2導電性部材)
14 第2封止体
15 半田ボール(第2外部端子)
16 ダイボンド材
17 第2半導体パッケージ
18 封止体
19 POP型半導体装置
20 チップ部品
21 SDRAM(第3半導体チップ)
21a 主面(第3チップ主面)
21b 裏面
21c 第3パッド(第3電極パッド)
22 POP型半導体装置
23 POP型半導体装置
24 隙間
Claims (16)
- 複数の第1ボンディングリードが形成された第1チップ搭載領域を有する第1基板主面、前記複数の第1ボンディングリードのそれぞれと電気的に接続され、前記第1基板主面において前記第1チップ搭載領域の周囲に配置された複数の第1基板主面側ランド、前記第1基板主面とは反対側に位置する第1基板裏面、及び前記複数の第1ボンディングリードのそれぞれと電気的に接続され、前記第1基板裏面に配置された複数の第1基板裏面側ランドを有する第1配線基板と、
第1チップ主面、前記第1チップ主面に形成された複数の第1電極パッド、及び前記第1チップ主面とは反対側に位置する第1チップ裏面を有し、前記第1配線基板の前記第1チップ搭載領域上に搭載された第1半導体チップと、
前記第1半導体チップの前記複数の第1電極パッドと前記第1配線基板の前記複数の第1ボンディングリードとをそれぞれ電気的に接続する複数の第1導電性部材と、
前記複数の第1基板主面側ランドのそれぞれを露出するように、前記第1半導体チップ、前記複数の第1導電性部材及び前記第1配線基板の前記第1基板主面を封止する第1封止体と、
前記第1配線基板の前記複数の第1基板裏面側ランドのそれぞれに形成された複数の第1外部端子と、
複数の第2ボンディングリードが形成された第2チップ搭載領域を有する第2基板主面、前記第2基板主面とは反対側に位置する第2基板裏面、及び前記複数の第2ボンディングリードのそれぞれと電気的に接続され、前記第2基板裏面に配置された複数の第2基板裏面側ランドを有する第2配線基板と、
第2チップ主面、前記第2チップ主面に形成された複数の第2電極パッド、及び前記第2チップ主面とは反対側に位置する第2チップ裏面を有し、前記第2配線基板の前記第2チップ搭載領域上に搭載された第2半導体チップと、
前記第2半導体チップの前記複数の第2電極パッドと前記第2配線基板の前記複数の第2ボンディングリードとをそれぞれ電気的に接続する複数の第2導電性部材と、
前記第2半導体チップ、前記複数の第2導電性部材及び前記第2基板主面を封止する第2封止体と、
前記第2配線基板の前記複数の第2基板裏面側ランドのそれぞれに形成され、前記複数の第2基板裏面側ランドと前記複数の第1基板主面側ランドとをそれぞれ電気的に接続する複数の第2外部端子と、
を含み、
前記第1配線基板の前記第1基板主面の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺とを有する四角形から成り、
前記第1封止体は、平面視で、前記第1配線基板の前記第2辺と平行な第1辺を有し、前記第1封止体の前記第1辺と前記第1配線基板の前記第2辺の一部が重なり、前記第1配線基板の一方の前記第2辺の中央部から他方の前記第2辺の中央部に向かって形成されており、
前記複数の第1基板主面側ランドは、前記第1封止体と前記配線基板の前記第1辺との間に配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記第1半導体チップは制御回路を有した半導体チップであり、前記第2半導体チップはメモリ回路を有した半導体チップであり、前記第2半導体チップは、前記第1半導体チップによって制御されることを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記第1半導体チップが有する前記複数の第1電極パッドの数は、前記第2半導体チップが有する前記複数の第2電極パッドの数より多いことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1配線基板の前記第1基板主面上に、前記第2半導体チップのメモリ回路と異なったメモリ機能のメモリ回路を有する第3半導体チップが、前記第1辺に沿った方向の前記第1半導体チップの隣に搭載されていることを特徴とする半導体装置。
- 請求項4記載の半導体装置において、前記第3半導体チップが有する複数の第3電極パッドの数は、前記第1半導体チップが有する前記複数の第1電極パッドの数より少ないことを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記第3半導体チップは、前記複数の第3電極パッドが複数のワイヤによって前記第1配線基板の前記第1基板主面の複数の第3ボンディングリードに電気的に接続されており、前記複数のワイヤは、前記第1辺に沿った方向にワイヤリングされていることを特徴とする半導体装置。
- 請求項6記載の半導体装置において、前記第3半導体チップの前記複数の第3電極パッドは、前記第1辺に沿った方向の前記第3半導体チップの第3チップ主面の中央部に並んで配置されたセンタパッド配置であることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1封止体は、前記第1半導体チップを封止する第1封止部と、前記第1辺に沿った方向の前記第1封止部の両側に前記第1封止部と一体で形成された第2封止部とから成り、前記第1配線基板の前記第1基板主面の前記第2封止部の前記第2辺に沿った方向の両側に第3ランドが設けられていることを特徴とする半導体装置。
- 請求項8記載の半導体装置において、前記第2封止部の前記第2辺に沿った方向の幅は、前記第1封止部の同方向の幅より狭いことを特徴とする半導体装置。
- 請求項9記載の半導体装置において、前記第2封止部の厚さは、前記第1封止部の厚さより厚いことを特徴とする半導体装置。
- 請求項10記載の半導体装置において、前記第2封止部は、前記第1配線基板の前記第1基板主面上に搭載されたチップ部品を封止していることを特徴とする半導体装置。
- 請求項10記載の半導体装置において、前記第2配線基板の平面方向の大きさが前記第1配線基板の平面方向の大きさより小さく、前記第2配線基板の前記第2基板裏面は、前記第1封止部より高く、かつ前記第2封止部より低い位置に配置されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1配線基板の前記第1基板主面上の前記複数の第1基板主面側ランド列の外側に、前記第1辺に沿って第3封止部が形成されており、前記第2配線基板の前記第2基板裏面の端部が前記第3封止部によって支持されていることを特徴とする半導体装置。
- 請求項13記載の半導体装置において、前記第3封止部の厚さは、前記第1封止部及び前記第2封止部の厚さより厚いことを特徴とする半導体装置。
- (a)複数の第1ボンディングリードが形成された第1チップ搭載領域を有する第1基板主面、前記複数の第1ボンディングリードのそれぞれと電気的に接続され、前記第1基板主面において前記第1チップ搭載領域の周囲に配置された複数の第1基板主面側ランド、前記第1基板主面とは反対側に位置する第1基板裏面、及び前記複数の第1ボンディングリードのそれぞれと電気的に接続され、前記第1基板裏面に配置された複数の第1基板裏面側ランドを有するデバイス形成領域が複数個形成された第1配線基板を準備する工程;
(b)第1チップ主面、前記第1チップ主面に形成された複数の第1電極パッド、及び前記第1チップ主面とは反対側に位置する第1チップ裏面を有する複数の第1半導体チップを、前記第1配線基板の前記複数のデバイス形成領域のそれぞれの前記第1チップ搭載領域上に搭載する工程;
(c)前記第1半導体チップの前記複数の第1電極パッドと前記第1配線基板の前記複数の第1ボンディングリードとを複数の第1導電性部材を介してそれぞれ電気的に接続する工程;
(d)前記複数の第1基板主面側ランドのそれぞれを露出するように、前記複数の第1半導体チップ、前記複数の第1導電性部材及び前記第1配線基板の前記第1基板主面を樹脂で一括して封止する工程;
(e)前記第1配線基板の前記複数の第1基板裏面側ランドのそれぞれに複数の第1外部端子を形成する工程;
(f)第2基板主面上に第2半導体チップが搭載され、前記第2基板主面とは反対側に位置する第2基板裏面に複数の第2基板裏面側ランドが配置された第2配線基板を、複数の第2外部端子を介して前記第1配線基板上に搭載し、前記複数の第1基板主面側ランドと前記複数の第2基板裏面側ランドとをそれぞれ電気的に接続する工程;
を含み、
前記第1配線基板の前記第1基板主面の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺とを有する四角形から成り、
前記複数の第1基板主面側ランドは、前記樹脂が供給される領域と前記配線基板の前記第1辺との間に配置されており、
前記(d)工程では、前記第1配線基板の一方の前記第2辺の中央部から他方の前記第2辺の中央部に向かって前記樹脂を供給し、封止体を形成することを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、前記(f)工程で、予め前記第2基板裏面側ランドに設けられた前記複数の第2外部端子を、前記第1配線基板の前記複数の第1基板主面側ランド上に配置した後、前記複数の第1基板主面側ランドと前記複数の第2基板裏面側ランドとを前記複数の第2外部端子を介して電気的に接続することを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008319938A JP5259369B2 (ja) | 2008-12-16 | 2008-12-16 | 半導体装置及びその製造方法 |
US12/606,504 US8648453B2 (en) | 2008-12-16 | 2009-10-27 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008319938A JP5259369B2 (ja) | 2008-12-16 | 2008-12-16 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010147090A JP2010147090A (ja) | 2010-07-01 |
JP5259369B2 true JP5259369B2 (ja) | 2013-08-07 |
Family
ID=42239534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008319938A Expired - Fee Related JP5259369B2 (ja) | 2008-12-16 | 2008-12-16 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8648453B2 (ja) |
JP (1) | JP5259369B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011150416A (ja) * | 2010-01-19 | 2011-08-04 | Toshiba Corp | 半導体メモリ装置 |
JP5666211B2 (ja) * | 2010-09-01 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 配線基板及び半導体装置の製造方法 |
KR101712043B1 (ko) * | 2010-10-14 | 2017-03-03 | 삼성전자주식회사 | 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법 |
JP2017022241A (ja) * | 2015-07-09 | 2017-01-26 | 株式会社東芝 | 半導体装置及び電子機器 |
CN113488505B (zh) | 2019-04-30 | 2022-09-30 | 长江存储科技有限责任公司 | 具有三维相变存储器的三维存储设备 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3871853B2 (ja) * | 2000-05-26 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置及びその動作方法 |
US6400033B1 (en) * | 2000-06-01 | 2002-06-04 | Amkor Technology, Inc. | Reinforcing solder connections of electronic devices |
JP4512545B2 (ja) * | 2005-10-27 | 2010-07-28 | パナソニック株式会社 | 積層型半導体モジュール |
JP2007123454A (ja) * | 2005-10-27 | 2007-05-17 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP4650269B2 (ja) * | 2006-01-05 | 2011-03-16 | 日立電線株式会社 | 積層型半導体装置の製造方法 |
TWI317993B (en) * | 2006-08-18 | 2009-12-01 | Advanced Semiconductor Eng | Stackable semiconductor package |
JP4574602B2 (ja) * | 2006-09-11 | 2010-11-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2008166527A (ja) * | 2006-12-28 | 2008-07-17 | Spansion Llc | 半導体装置およびその製造方法 |
US7982297B1 (en) * | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
KR101409839B1 (ko) * | 2007-05-23 | 2014-06-26 | 삼성전자주식회사 | 반도체 패키지 |
JP2009094434A (ja) * | 2007-10-12 | 2009-04-30 | Elpida Memory Inc | 半導体装置およびその製造方法 |
-
2008
- 2008-12-16 JP JP2008319938A patent/JP5259369B2/ja not_active Expired - Fee Related
-
2009
- 2009-10-27 US US12/606,504 patent/US8648453B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20100148350A1 (en) | 2010-06-17 |
US8648453B2 (en) | 2014-02-11 |
JP2010147090A (ja) | 2010-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5840479B2 (ja) | 半導体装置およびその製造方法 | |
KR100441532B1 (ko) | 반도체장치 | |
US7847413B2 (en) | Semiconductor device and method of manufacturing the same | |
US8159057B2 (en) | Semiconductor device and manufacturing method therefor | |
US6385049B1 (en) | Multi-board BGA package | |
JP5707902B2 (ja) | 半導体装置及びその製造方法 | |
US6750080B2 (en) | Semiconductor device and process for manufacturing the same | |
US7859118B2 (en) | Multi-substrate region-based package and method for fabricating the same | |
US6300685B1 (en) | Semiconductor package | |
JP5259369B2 (ja) | 半導体装置及びその製造方法 | |
US20040245622A1 (en) | Semiconductor device | |
JP2008103685A (ja) | 半導体装置及びその製造方法 | |
US7777308B2 (en) | Integrated circuit packages including sinuous lead frames | |
JP2011249582A (ja) | 半導体装置 | |
KR100587081B1 (ko) | 개선된 열방출 특성을 갖는 반도체 패키지 | |
JP2011003764A (ja) | 半導体装置及びその製造方法 | |
JP2014204082A (ja) | 半導体装置の製造方法 | |
JP3226244B2 (ja) | 樹脂封止型半導体装置 | |
JP2011222901A (ja) | 半導体装置 | |
JP4278568B2 (ja) | 半導体装置 | |
JP2005150771A (ja) | 配線基板、半導体装置およびパッケージスタック半導体装置 | |
JP2011061055A (ja) | 半導体装置の製造方法 | |
JP2007095964A (ja) | 半導体装置の製造方法 | |
JP2005142284A (ja) | 半導体装置 | |
US8399967B2 (en) | Package structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100528 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111031 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120622 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120626 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120824 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130402 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130424 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160502 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5259369 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |