JP4574602B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize inexpensively a memory in which storage capacity is large and a data holding current is less. <P>SOLUTION: The semiconductor device has a first semiconductor chip (CHIP1) in which a flash memory is formed, a second semiconductor chip (CHIP2) in which a static random access memory is formed, a third semiconductor chip (CHIP3) having a plurality of memory banks and including a dynamic random access memory performing read/write by a command synchronizing with a clock, and a cover in which the first to the third semiconductor chips are included in it, wherein the cover has a plurality of first electrodes for connecting electrically to the first to the third semiconductor chips, and a second electrodes for connected to the plurality of the first electrodes and connecting electrically to the outside of the cover. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a composite memory semiconductor device including a DRAM, and further relates to a refresh method for the DRAM.

  The list of documents referred to in this specification is as follows, and the documents are referred to by document numbers. [Reference 1]: LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet ([Search April 21, 2000], Internet <URL: http://www.sharpsma.com/index.html>), [Reference 2]: Japanese Patent Application Laid-Open No. 11-219984, [Document 3]: Japanese Patent Application Laid-Open No. 5-996616 (corresponding European Patent Publication No. 566,306, October 20, 1993), [Reference 4]: -305680, [Document 5]: JP-A-11-204721, [Document 6]: JP-A-10-11348.

  [Document 1] describes a composite semiconductor memory in which a flash memory and an SRAM are integrally sealed in a BGA type package with a stack chip. In the flash memory and the SRAM, the address input terminal and the data input / output terminal are made common to the input / output electrodes of the FBGA type package, but each control terminal is independent.

  [Document 2] describes a composite semiconductor memory in which a flash memory and an SRAM are integrally sealed in a BGA type package. In the flash memory, signal pads are face-down bonded to the circuit board of the BGA package via solder bumps. In the SRAM mounted on the flash memory, signal pads are connected to the substrate by wire bonding.

  FIG. 17 of [Document 3] describes a composite semiconductor memory in which a flash memory chip and a DRAM chip are integrally sealed in a lead frame type package. FIG. 1 shows a flash memory and a DRAM in which address input terminals, data input / output terminals, and control terminals are input / output in common with respect to input / output electrodes of a package.

  In [Document 4], an SRAM chip is mounted on a die pad, a flash memory chip connected to the SRAM chip via a bump electrode, and a microcomputer chip are mounted, and these chips form a lead terminal type package. An integrally sealed semiconductor device is described.

  FIG. 15 of [Document 5] describes a semiconductor device that is integrally sealed in a lead frame type package in which two smaller chips are mounted on the back surface of one large chip via an insulating plate. Has been. As a combination of chips that can be mounted, there are a flash memory chip, a DRAM chip, and an application specific IC (ASIC), and it is described that a memory-logic mixed LSI is realized in one package.

  [Document 6] is a technology that has two DRAM blocks, stores the same data in duplicate, shifts the refresh timing between the two DRAM blocks, and avoids collision between external access and DRAM refresh. Is described. This control is performed by a DRAM controller, and this DRAM controller generates physically independent address signals and control signals for two DRAM blocks.

LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet ([Search April 21, 2000], Internet <URL: http://www.sharpsma.com/index.html>) Japanese Patent Laid-Open No. 11-219984 Japanese Patent Laid-Open No. 5-299616 (corresponding European Patent Publication No. 566,306, October 20, 1993) JP-A-8-305680 Japanese Patent Laid-Open No. 11-204721 Japanese Patent Laid-Open No. 10-11348

  Prior to the present application, the inventors of the present application examined a mobile phone and a composite memory in which a flash memory and an SRAM used for the mobile phone were mounted in one package. In addition to the OS (operation system) of the mobile phone system, the flash memory stores communication and application programs. On the other hand, the telephone number, address book, ringtone, etc. are stored in the SRAM, and a work area temporarily used when executing the application is secured.

  In order to hold data to be stored, such as a telephone number and an address book, a power source for holding data is connected to the SRAM even when the power of the mobile phone is turned off. In order to retain data over a long period of time, it is desirable that the data retention current of the SRAM be small. However, it is expected that the work area used by the application will increase as the functions added to the mobile phone (distribution of music, games, etc.) increase, and an SRAM with a larger storage capacity will be required. In particular, recent mobile phones have been remarkably advanced, and it has been found that it will become increasingly difficult to cope with the increased capacity of SRAM. That is, there are the following problems in increasing the capacity of SRAM. The problem with large-capacity SRAMs is that the data retention current increases as the storage capacity increases, and the data retention current increases due to the increase in gate leakage current. This is because if a microfabrication is introduced to realize a large-capacity SRAM and the oxide insulating film of the MOS transistor is thinned, a tunnel current flows from the gate to the substrate and the data holding current increases.

  Accordingly, one of the objects of the present invention is to realize a memory having a large storage capacity and a small data holding current.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

    Representative means of the present invention are as follows. One encapsulated flash memory, a static random access memory (SRAM), and a dynamic random access memory (DRAM) that is composed of a plurality of memory banks and that reads / writes by a command synchronized with a clock And an electrode for connecting the semiconductor chip to the sealing body and an electrode for connecting the sealing body and the outside of the sealing body are provided.

  At this time, in order to conceal the refresh of the DRAM from outside the semiconductor device, a memory controller is connected to the DRAM including two or more banks in one chip to control the memory access to the DRAM. When memory access is performed by the memory controller during the first period, the first bank is accessed, and when memory access is performed during the second period, the second bank is accessed. .

  Further, a first memory block having a plurality of memory banks having the same memory capacity by using a dynamic random access memory (DRAM) which is constituted by a plurality of memory banks and performs reading / writing by a command synchronized with a clock. And the second memory block, the memory is accessed alternately in the first period and the second period. In the first period, a read / write command for the DRAM is executed for the first memory block, and the second memory block is executed with priority on refresh. In the second period, it is preferable that a read / write command for the DRAM is executed for the second memory block, and the first memory block is executed with priority on refresh.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the effects obtained by the present invention are as follows. First, by controlling access to the DRAM by the controller, a large-capacity memory that does not need to be refreshed from the outside is realized. Secondly, a memory module with a small data holding current is realized by setting a data holding area and a work area and performing power control respectively. Thirdly, a memory module with a small mounting area can be provided by mounting a plurality of semiconductor chips on one sealing body.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor).

<Example 1>
FIG. 1 shows a first embodiment of a memory module as an example of a semiconductor integrated circuit device to which the present invention is applied. This memory module is composed of three chips. Each chip will be described below.

  First, CHIP1 (FLASH) is a nonvolatile memory. As the nonvolatile memory, ROM (read only memory), EEPROM (electrically erasable and programmable ROM), flash memory, or the like can be used. In this embodiment, a flash memory will be described as an example. In CHIP2 (SRAM + CTL_LOGIC), a static random access memory (SRAM) and a control circuit (CTL_LOGIC) are integrated. The control circuit controls the SRAM and CHIP3 integrated in CHIP2. CHIP3 (DRAM) is a dynamic random access memory (DRAM). There are various types of DRAM such as EDO, SDRAM, and DDR due to differences in internal configuration and interface. Although any DRAM can be used for this memory module, this embodiment will be described using SDRAM as an example.

  This memory module has external addresses (A0 to A20) and command signals (S- / CE1, S-CE2, S- / OE, S- / WE, S- / LB, S- / UB, F- / WE , F- / RP, F- / WP, F-RDY / BUSY, F- / CE, F- / OE). Power is supplied through S-VCC, S-VSS, F-VCC, F-VSS, L-VCC, and L-VSS, and I / O0 to I / O15 are used for data input / output. The address signal line and the data input / output line are commonly connected to CHIP1 (FLASH) and CHIP2 (SRAM). CHIP2 is the clock (D-CLK), address (D-A0 to D-A13), command (D-CKE, D- / CS, D- / RAS, D- / CAS, D-) required for CHIP3 operation. / WE, D-DQMU / DQML), DRAM data (D-DQ0 to D-DQ15), power supply (D-VCC, D-VSS, D-VCCQ, D-VSSQ). One of the features of this memory node and the external availability node is that signal terminals for DRAM interface are not directly visible. Accordingly, the BGA (ball grid array) type package of the present invention will be described with reference to FIG. 16 and the like in the later embodiment. As a terminal used as an external terminal in this package, a signal terminal for controlling the DRAM is usually used It is not provided. As a result, the user can enjoy the merit of increasing the storage capacity since the presence of DRAM is refreshed from the outside. Of course, when the number of signal terminals of the BGA type package is very large and there is a margin, the control terminals of the DRAM may be led out in parallel mainly for the purpose of testing at the time of manufacture by the manufacturer. By doing so, the manufacturer can quickly perform defect analysis and the like. Of course, this function is not normally open to the user.

  Here, each command signal will be briefly described. S- / CE1 and S-CE2 input to CHIP2 are chip enable signals, S- / OE is output enable signals, S- / WE is write enable signals, S- / LB is lower byte selection signals, S- / UB is an upper byte selection signal. F- / WE input to CHIP1 is a write enable signal, F- / RP is a reset / deep power down signal, F- / WP is a write protect signal, F-RDY / BUSY is a ready / busy output signal, F- / The / CE chip enable signal, F- / OE, is an output enable signal and is used to control the flash memory.

  This memory module can access flash memory, SRAM, and DRAM using common address lines (A0 to A20) and data input / output lines (I / O0 to I / O15).

  When accessing the flash memory (CHIP1), in addition to the address lines (A0 to A20), command signals F- / WE, F- / RP, F- / WP, F-RDY / BUSY, F- / CE, F- Activate the required signal in / OE. When accessing SRAM (CHIP2) or DRAM (CHIP3), in addition to the address lines (A0 to A20), command signals S- / CE1, S-CE2, S- / OE, S- / WE, S- / LB, Activate the necessary signals in S- / UB. Any access is performed by a so-called SRAM interface method.

  Access to the SRAM and access to the DRAM are distinguished by the input address value. The control circuit (CTL_LOGIC) determines the access destination based on the input address value. The range of addresses for accessing SRAM and the range of addresses for accessing DRAM are determined by setting values in registers provided in the control circuit (CTL_LOGIC) in advance.

  When accessing the DRAM, the control circuit (CTL_LOGIC) generates address signals and command signals necessary for accessing the DRAM, and accesses the DRAM. In the case of read access, the read data from the DRAM is once read from the DRAM data I / O (D-DQ0 to D-DQ15) to the control circuit (CTL_LOGIC) and then the data input / output line (I / O) of the memory module. O0 to I / O15). In the case of write access, the write data is input from the data input / output lines (I / O0 to I / O15) of the memory module, and then input to the DRAM through the DRAM data I / O (D-DQ0 to D-DQ15). .

  Power to the DRAM is supplied from L-VCC and L-VSS, and connected to D-VCC, D-VSS, D-VCCQ, and D-VSSQ through a control circuit (CTL_LOGIC). The power supply to the DRAM is controlled by the command signal PS and can be cut off as necessary. It is necessary to initialize the DRAM when powering off the disconnected DRAM. The control circuit (CTL_LOGIC) performs signal generation and timing control necessary for DRAM initialization.

  Further, when refreshing the DRAM, the control circuit (CTL_LOGIC) can periodically perform a refresh command. In general, the refresh characteristics of DRAM deteriorate at high temperatures, but DRAM can be used in a wider temperature range by providing a thermometer in the control circuit (CTL_LOGIC) and reducing the refresh command input interval at high temperatures.

  In addition, the control circuit (CTL_LOGIC) holds one data at two different addresses in the DRAM and adjusts the refresh timing so that the access is not restricted by the refresh operation from the outside of the memory module. So as to conceal the refresh.

  According to the embodiment described above, a large-capacity memory module using an inexpensive general-purpose DRAM can be realized while following the SRAM interface method. Although the DRAM is used in the memory module according to the present invention, the refresh necessary for the DRAM is executed inside the module, so that it can be used without considering the refresh like the SRAM. Also, by changing the refresh interval executed inside the module depending on the temperature, it is possible to extend the operating temperature range of the DRAM, and a large-capacity memory module with a wide operating temperature range can be realized.

  In addition, the DRAM refresh can be hidden from the outside of the memory module by adjusting the data retention duplex and refresh timing in the DRAM. Therefore, when accessing this memory module, adjust the timing in consideration of the refresh. There is no need. Therefore, since it can be used in the same manner as a memory module using only a conventional SRAM, a large-capacity memory module can be used without changing the conventional system.

  Another object of the present invention is to realize a memory module with a small data holding current. For this purpose, it is only necessary to cut off the power supplied to the DRAM and retain only the data stored in the SRAM. By storing only the data to be retained in the SRAM and stopping the power supply to the memory where the data that does not need to be retained is stored, it is possible to retain only the necessary data with the minimum data retention current. is there.

  FIG. 2 shows CHIP2 (SRAM + CTL_LOGIC). CHIP2 (SRAM + CTL_LOGIC) is composed of an SRAM and a control circuit (CTL_LOGIC), and the integrated SRAM is an asynchronous SRAM that is generally used conventionally. The control circuit (CTL_LOGIC) is the part other than the SRAM of CHIP2 and is shown as the area surrounded by the broken line in Fig. 2, AS, MMU, ATD, DTD, FIFO, R / W BUFFER, A_CONT, INT, TMP, Consists of RC, PM, CLK_GEN, and COM_GEN.

  When an address is input from the outside, the memory management unit MMU converts the input address according to a set value and selects a memory to be accessed. When SRAM is selected, a command signal is sent to the SRAM by the access switch (AS), and the SRAM is accessed. The address transition detector circuit (ATD) detects a change in the address signal and the command signal and outputs a pulse. The data transition detector circuit (DTD) detects changes in the data signal and the command signal and outputs a pulse. R / W BUFFER temporarily holds data for DRAM read / write. The first-in first-out memory FIFO is a first-in first-out buffer circuit that temporarily holds data written to the DRAM and its address. The initialization circuit INT initializes the DRAM when power supply to the DRAM is started. The temperature measurement module (TMP) detects the temperature and outputs a signal corresponding to the detected temperature to RC and A_CONT. RC is a refresh counter that generates an address to be refreshed in accordance with the DRAM refresh interval. Also, the refresh interval is changed according to the temperature by the output signal of the temperature measurement module (TMP). The power module (PM) supplies power to the CHIP2 control circuit (CTL_LOGIC) and DRAM and controls power. The clock generator (CLK_GEN) generates a clock and supplies it to the DRAM and the control circuit (CTL_LOGIC). The command generator (COM_GEN) generates commands necessary for accessing DRAM. The access controller (A_CONT) controls the overall operation of CHIP2 (SRAM + CTL_LOGIC) and generates an address for accessing the DRAM.

  In order to perform memory access to CHIP2 (SRAM + CTL_LOGIC), an interface is used in the conventional asynchronous SRAM method. When an address (A0 to A21) is input to CHIP2 (SRAM + CTL_LOGIC) from the outside, the address value is first converted by the MMU. The conversion pattern is determined by the value previously input to the register in the MMU. Whether the access destination is SRAM or DRAM is determined by the converted address.

  When accessing the SRAM, the MMU sends the converted address to the SRAM and at the same time instructs the address access switch (AS) to transfer the command. The address access switch (AS) transfers the command to the SRAM, and access to the SRAM is started. In subsequent operations, access to a so-called asynchronous SRAM is performed.

  The operation of each block of the control circuit in the case of performing read access to the DRAM will be described below. First, an address input from the outside and converted by the MMU and a command detected by the ATD are sent to A_CONT. A_CONT judges execution of access to DRAM from the address and command sent, and instructs COM_GEN to issue a command to DRAM. A_CONT converts the address received from the MMU for DRAM and outputs it to DRAM. COM_GEN issues a command to the DRAM in synchronization with the clock generated by CLK_GEN. The DRAM receiving the command and address outputs data, and the output data is transferred to I / O0 to I / O15 via the R / W BUFFER, and the read access is completed.

  When performing write access to the DRAM, an address input from the outside and converted by the MMU, a command detected by the ATD, and a command and data detected by the DTD are sent to the A_CONT. A_CONT judges execution of access to DRAM from the address and command sent, and instructs COM_GEN to issue a command to DRAM. A_CONT converts the address received from the MMU for DRAM and outputs it to DRAM. COM_GEN issues a command to the DRAM in synchronization with the clock generated by CLK_GEN. Data to be written is input from I / O0 to I / O15, temporarily held in the R / W BUFFER, and then sent to the DRAM for writing. In addition, the data and address written in this way are also held in the FIFO, and are also written into another bank of the DRAM later.

  The power supplied to the DRAM is controlled by a power module (PM). In some cases, a device in which a memory module is mounted may want to reduce current consumption according to the operating state. In such a case, for example, the power module can stop the refresh performed by the refresh counter in accordance with the command signal PS to reduce the power required for refreshing the DRAM. In order to further reduce power consumption, the power supplied to the DRAM may be cut off in the memory module. In this case, the power module stops power supply to the D-VCC supplied to the DRAM according to the command signal PS output from the device.

  In addition, if it is desired to further reduce power consumption, the power module may stop supplying power to the portion of CHIP2 (SRAM + CTL_LOGIC) involved in memory access to the DRAM according to the command signal PS. In this state, for example, in CHIP2 (SRAM + CTL_LOGIC), in addition to the SRAM, it is possible to connect the power supply only to the MMU and AS to be in the operating state, and to set the mode in which only the SRAM is accessed.

  Further, it is possible to set the operation state in which only the SRAM data is held by the command PS. In such a case, the power supply other than the power supply (S-VCC, S-VSS) connected to the SRAM is disconnected and access to the memory is prohibited. In this state, the memory module holds the data stored in the SRAM.

  In order to restart the DRAM once the power supply is stopped and the operation is stopped, it is necessary to initialize the DRAM in addition to restarting the power supply. Although the initialization method is general, in this memory module, the initial circuit (INT) instructs the access controller (A_CONT) the initialization procedure and the initialization is executed.

  Note that even if DRAM refresh is stopped, DRAM initialization is required to operate the DRAM again, but the initial circuit (INT) also instructs the access controller (A_CONT) the initialization procedure. Initialization is performed.

  The refresh counter RC outputs a refresh address according to the DRAM refresh interval, and requests the access controller to execute refresh. The access controller issues a refresh command and refreshes the DRAM in accordance with a request from the refresh counter while accessing and arbitrating the DRAM from the outside.

  When the memory module is used at a high temperature, it is necessary to refresh frequently by shortening the DRAM refresh interval. In such a case, the temperature measurement module (TMP) detects the temperature and notifies the refresh counter and the access controller. When the temperature becomes high, the refresh counter changes the refresh interval short and outputs a refresh address.

  A clock (D-CLK) required for DRAM operation is generated by a clock generator (CLK_GEN). The clock generator supplies a clock to each block in the control circuit in addition to the DRAM. When the DRAM operates in synchronization with the clock, the command generator (COM_GEN) issues a command in synchronization with the clock.

  Power consumption can be reduced by stopping the refresh of DRAM. When the DRAM power is shut off and only the SRAM is accessed, it is possible to operate with lower power with a small storage capacity. In this case, the power supply to the control circuit necessary for accessing the DRAM can also be stopped, and the operation can be performed with lower power. Furthermore, a data holding mode with lower power consumption can be realized by supplying power only to the SRAM and holding only the data stored in the SRAM. Even when the power is reapplied to the DRAM, the initialization of the DRAM can be performed by the control circuit, so there is no need to execute the initialization procedure for the module from the outside. Therefore, a memory module that easily reduces power consumption can be realized.

  FIG. 3 shows an example of a memory map converted by the MMU. Although not particularly limited in the present embodiment, an example of a memory module having a nonvolatile memory storage area of 32 Mb, an SRAM data holding area of 2 Mb, and a DRAM storage area of 32 Mb will be described. Addresses A0 to A20 input from the outside are shared by the flash memory (CHIP1) and CHIP2. For selection of the access destination, signals S-CS and F-CS for chip selection are used. When F-CS becomes active, CHIP1 is selected and accessed, and when S-CS becomes active, CHIP2 is selected and accessed. F-CS is a general term for command signals F- / WE, F- / RP, F- / WP, F-RDY / BUSY, F- / CE, F- / OE used for CHIP1 access. Is a generic term for command signals S- / CE1, S-CE2, S- / OE, S- / WE, S- / LB, and S- / UB used for CHIP2 access. When CHIP2 is selected as the access destination, the MMU selects the memory to be accessed according to the address.

  In the example of the memory map shown in FIG. 3A, the SRAM area is set in a concentrated manner in a part of the address space. The SRAM address space overlaps the DRAM address space, and access to the overlapped address space is performed on the SRAM. DRAM in the same address space becomes a shadow area and is not accessed.

  On the other hand, in the example of the memory map shown in FIG. 3B, the SRAM areas are set in a distributed manner in a plurality of address spaces. Again, the SRAM address space overlaps the DRAM address space, and access to the overlapped address space is made to the SRAM. In this example, the SRAM area is set in units of 512Kb, but this is aligned with the FLASH memory write / erase unit, so that the address space management unit is aligned with the FLASH memory so that it can be handled easily by the OS and programs. It is.

  In this way, the MMU can allocate the SRAM area and DRAM area to the specified address space. In particular, when it is desired to reduce the data holding current, an address space for storing data to be held may be allocated to the SRAM area and power supply to the DRAM may be stopped. By this method, a memory module with a small data holding current can be realized.

  FIG. 4 shows another example of the memory map converted by the MMU.

  In the example of the memory map shown in FIG. 4A, the SRAM area is set in a concentrated manner in a part of the address space. The difference from the example of the memory map shown in FIG. 3A is that there is no overlap between the SRAM address space and the DRAM address space. Since there is no shadow area in DRAM, the DRAM memory space can be used effectively. Similarly in FIG. 4B, the SRAM address space and the DRAM address space do not overlap with the example of the memory map shown in FIG. 3B. Since there is no shadow area in DRAM, the DRAM memory space can be used effectively. When the memory map shown in FIGS. 4A and 4B is performed, the address space increases by about 2 Mb. In order to cope with this, an address line A21 may be added. As described above, in the memory maps shown in FIGS. 4A and 4B, the storage area of the DRAM can be used more effectively.

  FIG. 5 shows a configuration example and operation waveforms of the ATD circuit. The address transition detection circuit (ATD) detects a change in the value of the address signal line and generates a pulse. The symbols D1 and D2 used in the circuit drawings represent delay elements for generating a delay, respectively. When a change occurs in the address line (A0 to AN), the ATD outputs a pulse (/ φA0 to / φAN) having a width obtained by adding the delays of the delay element D1 and the delay element D2. Further, taking into account the operation variation of each address line, it is detected that the address value appearing on the address line has changed by generating a signal / φATD obtained by adding these pulses. As shown in FIG. 2, not only an address line but also a command signal is connected to the ATD to detect that a new command has been input. The configuration of the data transition detection circuit (DTD) is the same as that of the ATD. The DTD recognizes the write data and the write command by detecting the change in the data line and the command signal for writing.

  In this way, the SRAM interface signal that changes asynchronously by ATD and DTD is detected and the operation of the memory module is started. With these circuits, a memory module that operates with an asynchronous SRAM interface can be realized. In order to detect and detect signals that change asynchronously, it is also possible to use a memory device that operates synchronously inside the memory module.

  FIG. 6 shows how the DRAM is operated in a time-sharing manner in order to conceal the DRAM refresh. Here, a DRAM in which one chip is composed of four banks will be described as an example. Divide the four banks BANK-A0, BANK-A1, BANK-B0, BANK-B1 into two groups BANK-A0, BANK-A1 and BANK-B0, BANK-B1, and map the two groups to the same address space To do. That is, memory cells specified by one address exist in two groups, and data is stored twice as redundant.

  Fig. 6 (A) shows the operation at 75 ° C or lower, which is the normal operating temperature range of DRAM. Usually, a DRAM memory cell needs to be refreshed once every 64 ms, but the 64 ms is divided into 8 periods every 8 ms, and the BANK-A0, A1 group and the BANK-B0, B1 group are operated alternately. The WORK period displayed as WORK in the drawing represents the period during which the bank group operates, and the BANK-A0 and A1 groups operate during the first WORK period.

  When read access to the DRAM is performed, reading is performed from the set of BANK-A0 and A1 during the WORK period. When write access is performed, data is written to the BANK-A0 and A1 pairs during the WORK period, and the data and address to be written are temporarily stored in the FIFO. The stored data is also written to the set of BANK-B0 and B1 in the period T2. The period T2 will be described later. While BANK-A0 and A1 are in the WORK period, BANK-B0 and B1 are in the REF period. During the REF period, refresh is performed in a half area of the bank of the bank BANK-B0 and B1. The REF period is divided into a T1 period in which refresh is performed continuously and a T2 period in which writing performed during the REF period is written back from the FIFO.

  If the time required for refreshing is 70 ns per time, the time required for refreshing is 0.144 ms for 70 ns X 2048 times. Therefore, the T2 period is 7.856 ns (8 ms-0.144 ms). Here, it is assumed that the memory module is accessed once in 75 ns. If all accesses performed during the REF period are write accesses, the maximum number is 106667 times (8 ms / 75 ns). The time required to write this data to the DRAM is 7.47 ms (106667 times x 70 ns), which is less than the T2 period (7.856 ms), so that the write access performed during the REF period is T2 even if refresh is performed in the T1 period. All can be written back in time.

  Refresh can also be performed simultaneously in two banks during the REF period. In this case, since the number of refreshes executed in one bank in the T1 period is 1024, which is half, the T1 period can be reduced to half. If the T1 period is shortened, the memory capacity of the FIFO can be reduced, and a high-speed memory can be realized by shortening the interval of external access.

  FIG. 6B shows a case where the DRAM refresh interval is halved. In general, DRAM refresh characteristics deteriorate at high temperatures. Therefore, for example, at a high temperature of 75 ° C. or higher, data can be held by shortening the refresh interval as shown in the figure. In this embodiment, the temperature is detected by the temperature detection circuit TMP, and the refresh interval is changed by the refresh counter and the access control circuit (A_CONT).

  In this example, the refresh interval of 64 ms is reduced to half of 32 ns, and one WORK period and REF period are 4 ms each. Similarly, if all accesses performed during the REF period are write accesses, the maximum number is 53334 (4 ms / 75 ns). The time required to write this data to the DRAM is 3.74 ms (53334 times 70 ns), which is less than the T2 period (3.856 ms), so write access performed during the REF period can be refreshed during the T1 period. All can be written back within T2.

  In this way, DRAM refresh can be hidden. According to the present embodiment, the general-purpose DRAM can be used while concealing its refresh and handled in the same manner as the asynchronous SRAM. Therefore, a large-capacity memory module that can be accessed by the asynchronous SRAM interface can be realized. Even when the DRAM is used even at a high temperature, it can be realized simply by shortening the refresh interval as in this embodiment. In this embodiment, the operation unit of the DRAM is every two banks, but may be changed according to the configuration of the memory module or the memory chip. In addition, the refresh interval of 64 ms is divided into 8 periods to be the WORK period and the REF period. However, if the data is further divided, the storage capacity of the FIFO holding data and addresses can be reduced. On the other hand, if the number of divisions is large, the number of switching between the WORK period and the REF period can be reduced, so that the control circuit associated with the switching can be easily configured.

  FIG. 7 is a flowchart for explaining access to CHIP3 (DRAM). In STEP1, the address is input and the operation starts. In STEP2, the type of access is determined from the command. Subsequent operations differ depending on the type of access. If the access is read, go to STEP3. In STEP3, data is read from the bank during the WORK period, and the operation ends. If the access is write, go to STEP4 and STEP5. In STEP4, writing is performed in the bank during the WORK period. On the other hand, in STEP5, the data and address to be written are held in the FIFO. Here, when the bank in the REF period shifts from the T1 period to the T2 period, the process proceeds to STEP 6 and the data held in the FIFO is written into the bank in the REF period.

  Since the influence of refresh can be eliminated by reading and writing to the DRAM in this manner, a memory module of an asynchronous SRAM interface can be configured using a large capacity DRAM.

  FIG. 8 is a flowchart for explaining the operation of the bank during the REF period of CHIP3 (DRAM). SETP1 to STEP3 is the T1 period, and STEP4 to STEP6 is the T2 period. The REF period starts in STEP1 and the refresh is executed intensively in STEP2. In STEP 3, the number of refreshes is managed. When the refresh of the determined area is completed, the process proceeds to STEP 4, and the data stored in the FIFO is written to the bank. If it is determined in STEP 5 that writing of data held in the FIFO has been completed, the process proceeds to STEP 6 and write access can be accepted. However, the write access may be executed after waiting for data input to the FIFO in the state of STEP4.

  As described above, if the bank in the REF period is operated, the refresh operation and the execution of the write access can be made compatible within the REF period. As a result, the influence of refresh can be eliminated, so that a memory module with an asynchronous SRAM interface can be configured using a large capacity DRAM.

  FIG. 9 shows a state in which priorities are assigned to access to the DRAM. The operation of the DRAM according to the present invention can be explained based on the concept that the access to the bank during the REF period is executed with priority.

  FIG. 9 (A) schematically shows the priority order. As shown in this figure, only BANK-A0 and A1 during the WORK period are accessed only from the outside (3). This is preferentially executed for BANK-B0 and B1 during the REF period. On the other hand, in BANK-B0 and B1 during the REF period, refresh (1), writing of data held in the FIFO (2), and external write access (3) are performed. These executions are prioritized by the access control circuit (A_CONT) and executed with the priorities (1), (2), and (3).

  FIG. 9B shows how these accesses are executed according to priority. Here, BANK-A0 and A1 are in the WORK period, and BANK-B0 and B1 are in the REF period. In BANK-A0 and A1, only external access (3) is executed. On the other hand, BANK-B0 and B1 are just changing from the T1 period to the T2 period, the refresh (1) executed in the T1 period is completed, and then the T2 period is transferred to write the data held in the FIFO ( 2) is executed. In addition, while external access is performed in 75 ns, internal operations are performed in 70 ns, so that data processing held in the FIFO proceeds faster than external access.

  As described above, if the bank during the WORK period and the REF period is operated, the bank during the WORK period is externally connected while executing the refresh operation and the writing of the data held in the FIFO to the bank during the REF period. Access can be performed. Since the influence of refresh can be eliminated by this operation method, a memory module of an asynchronous SRAM interface can be configured using a large capacity DRAM.

  FIG. 10 is a configuration example of CHIP1 (FLASH) in the present embodiment. X-address buffer X-ADB, X-decoder X-DEC, Memory array MA, Y-address buffer Y-ADB, Y-decoder Y-DEC, Y-gate (column switch) & sense amplifier circuit Y-GATE / SENS AMP., Status / It consists of ID holding register STATUS / ID REG, multiplexer MULTIPLEXER, data I / O buffer I / O BUF, write and erase control circuit WSM, command user interface CUI for command decoding and execution . The operation of CHIP1 is the same as that of a FLASH memory generally used conventionally. This CHIP1 (FLASH) can constitute the memory module of this embodiment.

  FIG. 11 shows a configuration example of the SRAM in the present embodiment. It consists of an X decoder X-DEC, a memory array MA, a Y gate Y-GATE, a Y decoder Y-DEC, an input data control circuit D_CTL, a control circuit CONTROL LOGIC, and an input / output buffer for each signal line. This SRAM is a general so-called asynchronous SRAM. The memory module according to this embodiment can be configured by this SRAM.

  FIG. 12 shows a configuration example of the DRAM in this embodiment. X-address buffer X-ADB, refresh counter REF. COUNTER, X-decoder X-DEC, memory array MA, Y-address buffer Y-ADB, Y-address counter Y-AD COUNTER, Y-decoder Y-DEC, memory array MA, sense amplifier Circuit & Y gate (column switch) SENS AMP. & I / O BUS, input data buffer circuit INPUT BUFFER, output data buffer circuit OUTPUT BUFFER, control circuit & timing generation circuit CONTROL LOGIC & TG DRAM is a general-purpose SDRAM that has been used conventionally. Although it is not particularly limited, specifically, it includes four memory banks that can operate independently, and the address input terminals and data input / output terminals for them are shared and used in a time-sharing manner for each bank. The memory module according to this embodiment can be configured by this DRAM.

  FIG. 13 shows an example of operation waveforms of the memory module of the present invention. A0 to A20, S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE are signals that are input to the memory module, and are so-called asynchronous SRAM interface signals. . The data input / output signals I / O0 to I / O15 are represented as DIN and DOUT by dividing the data input and output, respectively. MMU, ATD, and DTD represent output signals of the MMU circuit, ATD circuit, and DTD circuit, respectively. D-CLK is a clock supplied to DRAM, D-COM is a generic name for command signals supplied to DRAM, D-A0 to D-A15 are DRAM address lines, D-DQ0 to D-DQ15 are DRAM I / O O line.

  First, read access that is performed first will be described. When the addresses A0 to A20 are input, the MMU circuit outputs the converted address. The ATD circuit detects changes in addresses A0 to A20 and commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE). When confirmed, a pulse is output. In response to this pulse, a bank active command A is issued to the DRAM, and the DRAM is brought into a bank active state. Next, the control circuit issues a read command R triggered by the falling edge of the S- / OE signal. Data read from the DRAM is output to D-DQ0 to D-DQ15, and is output to I / O0 to I / O15 once through the R / W BUFFER.

  In the next cycle, an example of write access is shown. In the case of write access, the bank active command A is issued in response to the fall of the ATD signal as in the case of read access. After that, the DTD circuit detects changes in I / O0 to I / O15 and commands (S- / CE1, S-CE2, S- / LB, S- / UB, S- / OE, S- / WE). A pulse is output and the write command is executed in response to this pulse. Since the data to be written is determined at the rise of S- / WE indicating the end of the write access, the write command is continuously issued until S- / WE rises. This is to cope with a case where the data to be written changes after the start of the write cycle. In the operation example shown in FIG. 13, two write commands are issued in succession, and then the write is completed and a precharge command is issued in accordance with the rising edge of the S- / WE signal.

  According to the embodiment described above, a large-capacity memory module using an inexpensive general-purpose DRAM can be realized while following the SRAM interface method. Although the DRAM is used in the control circuit (CTL_LOGIC) according to the present invention, the refresh necessary for the DRAM is executed by the control circuit (CTL_LOGIC), so that it can be used without considering the refresh like the SRAM. In addition, the DRAM refresh can be hidden from the outside of the memory module by adjusting the data retention duplex and refresh timing in the DRAM. Therefore, when accessing this memory module, adjust the timing in consideration of the refresh. There is no need. Therefore, since it can be used in the same manner as a memory module using only a conventional SRAM, a large-capacity memory module can be used without changing the conventional system.

<Example 2>
FIG. 14 shows another embodiment of CHIP2 constituting the memory module in the present invention.

  CHIP2 (CTL_LOGIC) in the present embodiment is composed of a control circuit (CTL_LOGIC), and is composed of ATD, DTD, FIFO, R / W BUFFER, A_CONT, INT, TMP, RC, PM, CLK_GEN, and COM_GEN. It differs from CHIP2 shown in FIG. 2 in that SRAM, access switch AS, and MMU are not incorporated. Therefore, all accesses are performed on the DRAM. The operation will be described below.

  The address transition detector circuit (ATD) detects a change in the address signal and the command signal and outputs a pulse. The data transition detector circuit (DTD) detects changes in the data signal and the command signal and outputs a pulse. R / W BUFFER temporarily holds data for DRAM read / write. The FIFO is a first-in first-out buffer circuit that temporarily holds data written to the DRAM and its address. INT initializes DRAM when power supply to DRAM is started. The temperature measurement module (TMP) detects the temperature and outputs a signal corresponding to the detected temperature to RC and A_CONT. RC is a refresh counter that generates an address to be refreshed in accordance with the DRAM refresh interval. Also, the refresh interval is changed according to the temperature by the output signal of the temperature measurement module (TMP). The power module (PM) supplies power to the CHIP2 control circuit (CTL_LOGIC) and DRAM and controls power. The clock generator (CLK_GEN) generates a clock and supplies it to the DRAM and the control circuit (CTL_LOGIC). The command generator (COM_GEN) generates commands necessary for accessing DRAM. The access controller (A_CONT) controls the overall operation of CHIP2 (CTL_LOGIC) and generates an address for accessing the DRAM.

  CHIP2 (CTL_LOGIC) is interfaced by asynchronous SRAM. When a signal is sent from the outside by the asynchronous SRAM method, CHIP2 converts this and accesses the DRAM. CHIP2 controls data input / output and refresh operations.

  The operation of each block of the control circuit in the case of performing read access to the DRAM will be described below. First, the address input from the outside and the command detected by ATD are sent to A_CONT. A_CONT judges execution of access to DRAM from the address and command sent, and instructs COM_GEN to issue a command to DRAM. A_CONT converts the received address for DRAM and outputs it to DRAM. COM_GEN issues a command to the DRAM in synchronization with the clock generated by CLK_GEN. The DRAM receiving the command and address outputs data, and the output data is transferred to I / O0 to I / O15 via the R / W BUFFER, and the read access is completed.

  When performing write access to DRAM, an address input from the outside, a command detected by ATD, and a command and data detected by DTD are sent to A_CONT. A_CONT judges execution of access to DRAM from the address and command sent, and instructs COM_GEN to issue a command to DRAM. Again, A_CONT converts the received address for DRAM and outputs it to DRAM. COM_GEN issues a command to the DRAM in synchronization with the clock generated by CLK_GEN. Data to be written is input from I / O0 to I / O15, temporarily held in the R / W BUFFER, and then sent to the DRAM for writing. In addition, the written data and address are also held in the FIFO, and are later written into another bank of the DRAM. The operations other than accessing the memory are the same as those described in the first embodiment.

  According to the embodiment described above, since the CHIP 2 can be configured with a smaller area without incorporating the SRAM, the access switch AS and the MMU, a large-capacity memory module can be realized at low cost. In addition, since the DRAM can be accessed without the operation of the access switch AS and MMU, a high-speed large-capacity memory module can be realized. The other effects of the present embodiment are the same as those already described in the first embodiment.

<Example 3>
FIG. 15 shows a third embodiment of CHIP2 and CHIP3 constituting the memory module in the present invention. CHIP4 (DRAM + CTL_LOGIC) in this embodiment is composed of a control circuit (CTL_LOGIC) and DRAM, and ATD, DTD, FIFO, R / W BUFFER, A_CONT, INT, TMP, RC, PM, CLK_GEN, COM_GEN, and DRAM are integrated on one chip. The DRAM is embedded in the CHIP2 shown in FIG. The operation will be described below.

  The address transition detector circuit (ATD) detects a change in the address signal and the command signal and outputs a pulse. The data transition detector circuit (DTD) detects changes in the data signal and the command signal and outputs a pulse. R / W BUFFER temporarily holds data for DRAM read / write. The FIFO is a first-in first-out buffer circuit that temporarily holds data written to the DRAM and its address. The initial circuit (INT) initializes the DRAM when power supply to the DRAM is started. The temperature measurement module (TMP) detects the temperature and outputs a signal corresponding to the detected temperature to the refresh counter (RC) and the access controller (A_CONT). The refresh counter generates an address for refreshing in accordance with the DRAM refresh interval. Also, the refresh interval is changed according to the temperature by the output signal of the temperature measurement module (TMP). The power module (PM) supplies power to the control circuit (CTL_LOGIC) of the CHIP4 and DRAM and controls the power. The clock generator (CLK_GEN) generates a clock and supplies it to the DRAM and the control circuit (CTL_LOGIC). The command generator (COM_GEN) generates commands necessary for accessing DRAM. The access controller (A_CONT) controls the overall operation of CHIP4 (DRAM + CTL_LOGIC) and generates an address for accessing the DRAM. To perform memory access to CHIP4 (DRAM + CTL_LOGIC), an interface is used in the so-called asynchronous SRAM method. When a signal is sent from the outside by the asynchronous SRAM method, the control circuit converts this and accesses the DRAM.

  The operation of each block of the control circuit in the case of performing read access to the DRAM will be described below. First, an address input from the outside is sent to A_CONT. The address change and command signal are detected by ATD, and ATD outputs a pulse to A_CONT. A_CONT judges execution of access to DRAM from the address and command sent, and instructs COM_GEN to issue a command to DRAM. A_CONT converts the received address for DRAM and outputs it to DRAM. COM_GEN issues a command to the DRAM in synchronization with the clock generated by CLK_GEN. The DRAM receiving the command and address outputs data, and the output data is transferred to I / O0 to I / O15 via the R / W BUFFER, and the read access is completed.

  Next, a case where write access to the DRAM is performed will be described. The address input from the outside, the command detected by ATD, and the command and data detected by DTD are sent to A_CONT. A_CONT judges execution of access to DRAM from the address and command sent, and instructs COM_GEN to issue a command to DRAM. A_CONT converts the received address for DRAM and outputs it to DRAM. COM_GEN issues a command to the DRAM in synchronization with the clock generated by CLK_GEN. Data to be written is input from I / O0 to I / O15, temporarily held in the R / W BUFFER, and then sent to the DRAM for writing. In addition, the data and address written in this way are also held in the FIFO, and are also written into another bank of the DRAM later.

  The power supplied to the DRAM is controlled by a power module (PM). In some cases, a device in which a memory module is mounted may want to reduce current consumption according to the operating state. In such a case, the power module can stop the refresh performed by the refresh counter in accordance with the command signal PS to reduce the power required for refreshing the DRAM.

  In order to further reduce the power consumption, the power supplied to the DRAM inside the CHIP4 may be cut off. In this case, the power module stops power supply to the D-VCC supplied to the DRAM according to the command signal PS output from the device.

  In addition, if it is desired to further reduce power consumption, the power module may stop supplying power to the portion of CHIP4 (DRAM + CTL_LOGIC) involved in memory access to the DRAM according to the command signal PS. In this state, for example, a power supply can be connected to only ATD in CHIP4 (DRAM + CTL_LOGIC) to enter a standby state. Other operations are the same as those described in the first embodiment.

  According to the embodiment described above, a large-capacity memory module using DRAM can be realized while following the SRAM interface method. The effects of the present invention include the following in addition to those already described in the first embodiment.

  According to the present embodiment, it is possible to reduce the number of parts of the memory module, simplify the module assembly process, and reduce the cost. Furthermore, in addition to being used as a memory module, this embodiment can be used alone as a large capacity SRAM. By using inexpensive DRAM while following the SRAM interface method, a large capacity SRAM compatible chip can be realized in a smaller area.

<Example 4>
FIG. 16 shows a fourth embodiment of the memory module according to the present invention. FIG. 16A shows a top view and FIG. 16B shows a cross-sectional view. In this memory module, CHIP1 (FLASH) and CHIP3 (DRAM) are mounted on a board (for example, a printed circuit board PCB made of a glass epoxy board) mounted on a device by a ball grid array (BGA). Although not particularly limited, the CHIP3 uses a general-purpose DRAM bare chip in which signal and power supply pad rows are arranged in a row at the center of a so-called chip. CHIP2 (SRAM + CTL_LOGIC) is further mounted on the upper surface of CHIP1 (FLASH). CHIP1 and the bonding pad on the substrate are connected by a bonding wire (PATH1), and CHIP2 and the bonding pad on the substrate are connected by a bonding wire (PATH2). CHIP3 is connected to the bonding pad on the substrate by a bonding wire (PATH3), and is also connected to CHIP2 by a bonding wire (PATH4). The upper surface of the substrate on which the chip is mounted is molded with a resin resin as a sealing material to protect each chip and connection wiring. Further, a metal, ceramic, or resin cover (COVER) may be used from above.

  In the embodiment according to the present invention, since CHIP2 can be mounted on CHIP1, a memory module having a small mounting area can be configured. Further, since the chips can be arranged close to each other, the interchip wiring length can be shortened. By unifying the wiring between chips and the wiring between each chip and the substrate by a bonding wire system, a memory module can be manufactured with a small number of processes. Further, by directly connecting the chips with bonding wires, the number of bonding pads and bonding wires on the substrate can be reduced, and the memory module can be manufactured with a small number of processes. Since a general-purpose DRAM bare chip mass-produced in large quantities can be used, a memory module can be stably supplied at low cost. When a resin cover is used, a stronger memory module can be configured. When a ceramic or metal cover is used, a memory module excellent in heat dissipation and shielding effect can be configured in addition to strength.

  FIG. 17 is a modification of the memory module of FIG. 16 according to the present invention. FIG. 17A shows a top view and FIG. 17B shows a cross-sectional view. In this example, a ball grid array (BGA) is used for mounting and wiring on the base of CHIP3 (DRAM). This method of connecting the semiconductor chip with the circuit formation surface down through metal bumps typified by solder bumps is also called face down. This mounting method eliminates the need for bonding between CHIP3 and the substrate and between CHIP2 and reduces the number of bonding wires, thereby reducing the number of assembly steps and realizing a more reliable memory module.

  FIG. 18 shows a modification of the memory module in FIG. 16 according to the present invention. 18A shows a top view and FIG. 18B shows a cross-sectional view. In this example, a ball grid array (BGA) is used for mounting and wiring on the base of CHIP1 (FLASH). Furthermore, PATH5 is used for wiring between CHIP2 mounted on CHIP1 and the board, and PATH6 is used for wiring between CHIP2 and CHIP3. This mounting method eliminates the need for bonding between CHIP1 and the substrate and reduces the number of wirings, thereby reducing the number of assembly steps and realizing a more reliable memory module. In addition, since there is no wiring from CHIP1 to the board, wiring PATH5 from CHIP2 to the board with a large height difference can be easily performed with a low wiring density. Similarly, PATH6 has a lower wiring density, and the height difference is alleviated because of the wiring to the upper surface of CHIP3, so that bonding can be performed easily.

  FIG. 19 shows a modification of the memory module in FIG. 16 according to the present invention. FIG. 19A shows a top view and FIG. 19B shows a cross-sectional view. In this example, a ball grid array is used to mount CHIP1 and CHIP3 on the base. Since bonding wiring only needs to be performed between CHIP2 and the substrate, a highly reliable memory module can be realized by reducing the number of wirings. Also, since there is no wiring from CHIP1 to the substrate, PATH5, which is the wiring from CHIP2, can reduce the wiring density and facilitate the bonding process.

  FIG. 20 shows a modification of the memory module in FIG. 16 according to the present invention. 20A shows a top view and FIG. 20B shows a cross-sectional view. In this example, CHIP1 is mounted on CHIP3 mounted on the base with a ball grid array, and further CHIP2 is mounted thereon. The wiring between CHIP2 and CHIP1 mounted on the top is performed by PATH7. PATH8 is used for wiring between CHIP2 and the board. Since three chips can be stacked by this mounting method, the mounting area of the memory module can be reduced. The connection between CHIP2 and the board can be connected by relaying signals using wiring PATH5 and wiring PATH7 in addition to wiring PATH8. In particular, when the method of relaying and wiring is used for signal wiring commonly used for CHIP1 and CHIP2, the number of wirings can be reduced, so that the bonding process can be simplified.

  FIG. 21 is a modification of the memory module of FIG. 16 according to the present invention. FIG. 21A shows a top view and FIG. 21B shows a cross-sectional view. In this example, CHIP3 is mounted on the base by a ball grid array, and further CHIP1 and CHIP2 are mounted thereon. PATH9 is used for wiring between CHIP1 and CHIP2. Further, PATH10 is used for wiring from a bonding pad placed on the center side of the module on CHIP1 and CHIP2 to the board.

  This mounting method is effective in reducing the mounting area of the module, particularly when the area of CHIP3 is large. Since CHIP3 is connected by BGA, the wiring density can be reduced by bonding, so the wiring process can be simplified. Further, CHIP1 and CHIP2 mounted on the same CHIP3 can easily align the height of the bonding pads, and the wiring PATH9 between CHIP1 and CHIP2 can be easily performed, so that the wiring process can be performed easily. Wiring PATH10 enables wiring between the wiring pads arranged on the center side of the module on CHIP1 and CHIP2 and the board. Further, by arranging CHIP1 and CHIP2 on the same surface of CHIP3, the height of the module becomes uniform, so that a stronger sealing body can be obtained.

  FIG. 22 shows a modification of the memory module in FIG. 16 according to the present invention. 22A shows a top view, and FIG. 22B shows a cross-sectional view. In this example, CHIP1 is mounted on the base by a ball grid array, and further CHIP2 and CHIP3 are mounted thereon. Wiring between LOC-format CHIP3 and CHIP2 can be performed by wiring PATH11. This mounting method is particularly effective in reducing the module mounting area when the area of CHIP1 is large. Since CHIP1 is connected by BGA, the wiring density can be reduced by bonding, so the wiring process can be simplified. Further, CHIP3 and CHIP2 mounted on the same CHIP1 can easily align the height of the bonding pad, and the wiring PATH11 between the LOC-type CHIP3 and CHIP2 can be easily performed. Wiring between the wiring pad arranged on the center side of the module on CHIP2 and CHIP3 can be performed by wiring PATH11. Further, by arranging CHIP1 and CHIP2 on the same surface of CHIP3, the height of the module becomes uniform, so that a stronger sealing body can be obtained.

  FIG. 23 shows a fourth embodiment of the memory module according to the present invention. FIG. 23A shows a top view and FIG. 23B shows a cross-sectional view. In this example, CHIP1 is first mounted on the board, and further CHIP2 and CHIP3 are mounted on it. Wiring between CHIP1 and CHIP2 can be performed by wiring PATH12.

  This mounting method is particularly effective in reducing the module mounting area when the area of CHIP1 is large. All wiring is standardized for bonding, which simplifies the board manufacturing process. In addition, CHIP3 and CHIP2 mounted on the same CHIP1 are easy to align the height of the bonding pad, and wiring between CHIP3 and CHIP2 can be performed easily. Wiring between CHIP1 and CHIP2 can be performed by wiring PATH12. In particular, when used for signal wiring commonly used for CHIP1 and CHIP2, the number of wirings can be reduced as compared with the case where each wiring is connected from the substrate, thereby simplifying the bonding process. Further, by arranging CHIP1 and CHIP2 on the same surface of CHIP3, the height of the module becomes uniform, so that a stronger sealing body can be obtained.

It is a block diagram of the memory module to which this invention is applied. FIG. 2 is a block diagram showing an example of CHIP2 in FIG. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. It is explanatory drawing which shows an example of the address map of the memory module to which this invention is applied. 3 is a configuration example of an ATD circuit or a DTD circuit in FIG. It is explanatory drawing which shows an example of the refresh system of DRAM. It is a flowchart which shows the flow of a process at the time of accessing DRAM. 6 is a flowchart showing a flow of operations in a DRAM bank during a REF period. It is explanatory drawing explaining a mode that performing access to DRAM and refreshing simultaneously. It is a block diagram which shows one structural example of flash memory. It is a block diagram which shows one structural example of SRAM. It is a block diagram which shows one structural example of DRAM. It is an example of the timing chart of the memory module to which this invention is applied. FIG. 2 is a block diagram showing a configuration example of CHIP2 in FIG. 1 is an example of an asynchronous SRAM interface type large capacity memory using DRAM according to the present invention; It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention. It is an example of the mounting form of the memory module by this invention.

Explanation of symbols

CHIP1… Non-volatile memory
CHIP2 ... Semiconductor chip with integrated control circuit (CTL_LOGIC) or static random access memory (SRAM) and control circuit (CTL_LOGIC)
CHIP3… Dynamic random access memory (DRAM)
CHIP4: A semiconductor chip with integrated dynamic random access memory (DRAM) and control circuit (CTL_LOGIC)
A0 to A20 ... Address signal
S- / CE1 ... CHIP2 chip enable signal
S-CE2 ... CHIP2 chip enable signal
S- / E ... CHIP2 output enable signal
S- / WE ... CHIP2 write enable signal
S- / LB ... CHIP2 lower byte selection signal
S- / UB ... CHIP2 upper byte selection signal
F- / WE ... CHIP1 write enable signal
F- / RP ... CHIP1 reset / deep power down signal
F- / WP ... CHIP1 write protect signal
F-RDY / BUSY… CHIP1 ready / busy output signal
F- / CE ... CHIP1 chip enable signal
F- / OE ... CHIP1 output enable signal
F-VCC ... CHIP1 power supply
F-VSS ... CHIP1 ground
S-VCC ... CHIP2 power supply
S-VSS ... CHIP2 ground
L-VCC ... CHIP2 power supply
L-VSS ... CHIP2 ground
PS ... Power control signal
I / O0 to I / O15: Data input / output
D-CLK ... CHIP3 clock
D-A0 to D-A13… CHIP3 address signal
D-CKE ... CHIP3 clock enable signal
D- / CS ... CHIP3 chip select signal
D- / RAS ... CHIP3 row address strobe signal
D- / CAS ... CHIP3 column address strobe signal
D- / WE ... CHIP3 write enable signal
D-DQMU / DQML ... CHIP3 input / output mask signal
D-DQ0 to D-DQ15 ... CHIP3 data input / output
D-VCC ... CHIP3 power supply
D-VSS ... CHIP3 ground
D-VCCQ ... CHIP3 I / O power supply
D-VSSQ ... CHIP3 I / O ground
AS ... Access switch circuit
SRAM ... Static random access memory
ATD… Ad Restaurant Detection Detector
DTD ... Data transition detector
MMU… Memory management unit
FIFO ... First in first out (memory)
R / W BUFFER Read / write buffer
INT ... Initialization circuit, TMP ... Temperature measurement module
RC ... Refresh counter
PM ... Power management module
A_CONT access controller
CLK_GEN: Clock generator
COM_GEN ... Command generator
S-CS: A collective term for SRAM chip select signals
F-CS: Generic term for chip select signals for nonvolatile memory
SHADOW ... Shadow area
/ ΦA0… Address change detection signal by ATD circuit
/ ΦAN ATD circuit address change detection signal
/ΦATD...ATD circuit output signal
D1 Delay element
D2 Delay element
WORK ... work period
REF ... Refresh period
PCB: Printed circuit board
COVER… Module sealing cover
PATH1: Bonding wiring connecting PCB and CHIP1
PATH2: Bonding wiring that connects PCB and CHIP2 mounted on CHIP1
PATH3: Bonding wiring connecting PCB and CHIP3
PATH4: Bonding wiring that connects CHIP3 and CHIP2 mounted on CHIP1
PATH5: Bonding wiring that connects PCB and CHIP2 mounted on CHIP1 arranged by BGA
PATH6: Bonding wiring that connects CHIP3 and CHIP2 mounted on CHIP1 arranged by BGA
PATH7: Bonding wiring that connects CHIP1 mounted on CHIP3 placed by BGA and CHIP2 mounted on it
PATH8: Bonding wiring that connects PCB and CHIP2 mounted on CHIP1 mounted on CHIP3 placed by BGA
PATH9: Bonding wiring that connects CHIP1 to CHIP1 mounted on CHIP3 placed by BGA
PATH10: Bonding wiring that connects the bonding pad placed on the center side of the module and PCB in CHIP2 mounted on CHIP3 placed by BGA
PATH11: Bonding wiring that connects CHIP3 to CHIP2 mounted on CHIP1 placed by BGA, with CHIP3 being a LOC-type bonding pad layout
PATH12: Bonding wiring that connects CHIP1 and CHIP2 mounted on CHIP1

Claims (1)

A first semiconductor chip on which a flash memory is formed;
A second semiconductor chip on which a static random access memory is formed;
A third semiconductor chip including a dynamic random access memory having a plurality of memory banks and performing read / write by a command synchronized with a clock;
A sealing body in which the first to third semiconductor chips are included;
The sealing body includes a plurality of first electrodes for electrical connection with the first to third semiconductor chips, and an electrical connection to the outside of the sealing body connected to the plurality of first electrodes. A plurality of second electrodes for performing
The plurality of second electrodes include a plurality of address signal terminals provided in common to the flash memory and the static random access memory, and a plurality of first control signal terminals for access control of the flash memory. A plurality of second control signal terminals for access control of the static random access memory, and a plurality of power supply terminals for the first to third semiconductor chips,
The third semiconductor chip includes a first node for inputting a command signal, a second node for inputting an address signal, and a third node for inputting / outputting data, which are provided for the dynamic random access memory. Nodes, and
The second semiconductor chip further includes a memory controller including a fourth node for outputting a command signal for the memory, a fifth node for outputting an address for the memory, and a sixth node,
  The semiconductor device according to claim 1, wherein the first to third nodes and the fourth to sixth nodes are connected via a predetermined one of the plurality of first electrodes on the first main surface.

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