JP4278568B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4278568B2
JP4278568B2 JP2004163908A JP2004163908A JP4278568B2 JP 4278568 B2 JP4278568 B2 JP 4278568B2 JP 2004163908 A JP2004163908 A JP 2004163908A JP 2004163908 A JP2004163908 A JP 2004163908A JP 4278568 B2 JP4278568 B2 JP 4278568B2
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semiconductor
semiconductor chip
chip
circuit board
semiconductor device
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JP2005347428A (en
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元昭 佐藤
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
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Description

本発明は、複数の半導体チップをパッケージに搭載してなる半導体装置に関するものである。   The present invention relates to a semiconductor device in which a plurality of semiconductor chips are mounted on a package.

現在、標準化した表面実装型の半導体パッケージの技術は、銅（Ｃｕ）合金または鉄−ニッケル（Ｆｅ−Ｎｉ）系合金のリードフレームのダイパッド部分に半導体チップがダイボンディングにより搭載され、半導体チップのボンディングパッド（電極パッド）とリードフレームのリード部の先端とが金（Ａｕ）線等の金属細線でワイヤーボンディングされ、所定の形状を有する金型にて樹脂モールドされてパッケージ体が構成されるものである。   At present, the standardized surface mount semiconductor package technology is that a semiconductor chip is mounted on a die pad portion of a lead frame of a copper (Cu) alloy or an iron-nickel (Fe—Ni) alloy by die bonding, and bonding of the semiconductor chip is performed. A package body is formed by wire bonding a pad (electrode pad) and a tip of a lead portion of a lead frame with a metal wire such as a gold (Au) wire, and resin molding with a mold having a predetermined shape. is there.

以下、従来の表面実装型の半導体装置について図５を参照しながら説明する。
図５（ａ）は従来の半導体装置における要部の構成を示す断面図である。
図５（ａ）に示すように、従来の半導体装置は、リードフレームのダイパッド２の部分に半導体チップ３が接着剤４を介してダイボンディングにより搭載され、半導体チップ３のボンディングパッド（図示せず）とリードフレームのインナーリード部１ａの先端とが金属細線（金線）５でワイヤーボンディングされて電気的接続がなされた状態で、所定の形状を有する金型にて封止樹脂６でモールドされる。そして、樹脂の硬化後は、金型から取り出された半導体装置のリードフレームのアウターリード部１ｂが、リードフォーミング金型にて所定のリード形状に加工されたものである。 A conventional surface mount type semiconductor device will be described below with reference to FIG.
FIG. 5A is a cross-sectional view showing a configuration of a main part in a conventional semiconductor device.
As shown in FIG. 5A, in the conventional semiconductor device, a semiconductor chip 3 is mounted on a die pad 2 portion of a lead frame by die bonding through an adhesive 4, and a bonding pad (not shown) of the semiconductor chip 3 is mounted. ) And the tip of the inner lead portion 1a of the lead frame are wire-bonded with a thin metal wire (gold wire) 5 and electrically connected, and then molded with a sealing resin 6 in a mold having a predetermined shape. The After the resin is cured, the outer lead portion 1b of the lead frame of the semiconductor device taken out from the mold is processed into a predetermined lead shape by a lead forming mold.

なお、半導体装置が完成した後は、電気的接続あるいは信号検査，信頼性試験が行われ、良品判定された製品は梱包出荷される。
近年、ＬＳＩの発達はメモリ／ロジック混載あるいはアナログ／デジタル混載が急速に進行しているが、市場のコスト競争力はさらに進み、今や、単に１チップ化してチップ拡散プロセスにより混載化することは、市場競争に勝つ条件ではなくなってきている。 After the semiconductor device is completed, electrical connection, signal inspection, and reliability test are performed, and products that are determined to be non-defective are packaged and shipped.
In recent years, LSI / memory / analog / analog / digital mixed development has progressed rapidly, but the cost competitiveness of the market has further advanced, and now it is simply integrated into a single chip by a chip diffusion process. It is no longer a condition for winning market competition.

そこで、最適なチップを選択し、複数の半導体チップを１パッケージ化する方が、混載により１チップ化するよりは、利益を上げる可能性が出てきた。その例としてマルチチップタイプの半導体装置がある。   Therefore, there is a possibility that selecting an optimal chip and packaging a plurality of semiconductor chips into one package may increase profits compared to a single chip by mixed mounting. An example is a multi-chip type semiconductor device.

図５（ｂ）は従来の半導体チップを積層したマルチチップタイプの半導体装置における要部の構成を示す断面図であり、図５（ｃ）は従来の半導体チップを並べたマルチチップタイプの半導体装置における要部の構成を示す断面図である。   FIG. 5B is a cross-sectional view showing a configuration of a main part in a multi-chip type semiconductor device in which conventional semiconductor chips are stacked, and FIG. 5C is a multi-chip type semiconductor device in which conventional semiconductor chips are arranged. It is sectional drawing which shows the structure of the principal part in.

図５（ｂ），図５（ｃ）に示すように、マルチチップタイプの半導体装置は、リードフレームのダイパッド主面上に、第１の半導体チップ３ａ，第２の半導体チップ３ｂと言った２つ以上の半導体チップが、接着ペースト４ａ，接着シート４ｂなどによりダイボンディングされた後、金属細線により各インナーリード部とのワイヤーボンドし、封止樹脂による外囲のモールドがなされて２チップ以上を１パッケージとしていた（例えば、特許文献１参照）。
特開２００２−０６６５９８号公報 As shown in FIG. 5B and FIG. 5C, the multi-chip type semiconductor device is referred to as a first semiconductor chip 3a and a second semiconductor chip 3b on the die pad main surface of the lead frame. After two or more semiconductor chips are die-bonded with an adhesive paste 4a, an adhesive sheet 4b, etc., wire bonding with each inner lead portion is performed with a thin metal wire, and an outer mold is formed by a sealing resin, so that two or more chips are formed. One package was used (see, for example, Patent Document 1).
Japanese Patent Application Laid-Open No. 2002-065598

しかしながら、前記従来の半導体装置において、特にマルチチップタイプの半導体装置では、あえて複数の半導体チップを搭載するため、マルチチップの配置位置やチップサイズの組み合わせにより半導体チップ間の内部接続ワイヤーやリードフレームとの接続ワイヤーが高密度化し、特に、複数のダイパッドを並列に備えて複数の半導体チップを搭載する場合に、搭載する半導体チップや回路基板の搭載領域を確保するために、ダイパッドの間隔を広げる必要があり、実装面積が大きくなると言う問題点があった。また、ワイヤー配線領域に制限が生じるため、電源供給やバス配線の等長配線等が困難になると言う問題点があった。また、内部配線が複雑化するため、信号ピン配置設計に制約を余儀なくされる場合があった。   However, in the conventional semiconductor device, particularly in a multi-chip type semiconductor device, since a plurality of semiconductor chips are intentionally mounted, an internal connection wire between the semiconductor chips, a lead frame, and the like depending on a combination position of the multi-chip and a chip size. In order to secure a mounting area for mounting semiconductor chips and circuit boards, especially when mounting multiple semiconductor chips with multiple die pads in parallel, it is necessary to widen the space between the die pads. There is a problem that the mounting area becomes large. In addition, since the wire wiring area is limited, there is a problem that it becomes difficult to supply power, to provide equal length wiring for bus wiring, and the like. Further, since the internal wiring becomes complicated, there are cases where restrictions are imposed on the signal pin layout design.

本発明は、前記従来の課題を解決するために、半導体チップや回路基板の搭載領域を縮小すると共に、信号や電源のワイヤー配線の自由度を向上することを目的とする。   In order to solve the above-described conventional problems, an object of the present invention is to reduce the mounting area of a semiconductor chip and a circuit board and improve the degree of freedom of signal and power supply wire wiring.

上記目的を達成するために本発明の半導体装置は、複数の半導体チップを搭載する半導体装置であって、前記半導体装置の電極となるリードフレームと、前記複数の半導体チップおよびリードフレームを互いに電気的に接続するワイヤー配線と、前記リードフレームに保持されその搭載面の垂直方向に段差を設け前記複数の半導体チップを搭載する複数のダイパッドとを有し、前記段差が前記半導体チップの厚みより大きく、前記複数の半導体チップの一部を互いにオーバーラップさせて前記ダイパッドに搭載可能であり、前記半導体チップの内の１または２以上の半導体チップがワイヤー配線用電極をチップ中央部に備えることを特徴とする。 The semi conductor device of the present invention in order to achieve the above object, a semiconductor device mounting a plurality of semiconductor chips, the electrical lead frame serving as an electrode of the semiconductor device, the plurality of semiconductor chips and lead frames to each other a wire wiring connected, have a plurality of die pads for mounting the plurality of semiconductor chips provided with a step in the vertical direction of the held to a lead frame mounting surface thereof, the step is greater than a thickness of the semiconductor chip , wherein the plurality of part of the semiconductor chip to be overlapped with each other may be mounted on the die pad, one or more semiconductor chips of said semiconductor chip to Rukoto an electrode wire wiring chip central portion Features .

また、複数の半導体チップを搭載する半導体装置であって、前記半導体装置の電極となるリードフレームと、前記半導体チップの内の１または２以上の半導体チップと積層させる１または２以上の回路基板と、前記複数の半導体チップおよびリードフレームならびに前記１または２以上の回路基板を互いに電気的に接続するワイヤー配線と、前記リードフレームに保持されその搭載面の垂直方向に前記半導体チップと前記回路基板を積層した厚みより大きな段差を設け前記複数の半導体チップを搭載する複数のダイパッドとを有し、前記複数の半導体チップまたは前記回路基板の一部を互いにオーバーラップさせて前記ダイパッドに搭載可能であり、前記半導体チップの内の１または２以上の半導体チップがワイヤー配線用電極をチップ中央部に備え、前記回路基板上に電源供給用のワイヤー配線用電極を有することを特徴とする。 In addition, a semiconductor device having a plurality of semiconductor chips, a lead frame serving as an electrode of the semiconductor device, and one or more circuit boards laminated with one or more semiconductor chips of the semiconductor chip; A plurality of semiconductor chips, a lead frame, and a wire wiring that electrically connects the one or more circuit boards to each other; and the semiconductor chip and the circuit board that are held by the lead frame in a direction perpendicular to a mounting surface thereof. A plurality of die pads on which the plurality of semiconductor chips are mounted by providing a step larger than the laminated thickness, and a part of the plurality of semiconductor chips or the circuit board may be overlapped with each other and mounted on the die pad; One or more of the semiconductor chips have a wire wiring electrode at the center of the chip. To comprise, it is characterized by having a wire wiring electrodes for supplying power to said circuit board.

また、前記ワイヤー配線は互いに電気的に独立し、平面的にはクロスすることを特徴とする。 In addition, the wire wirings are electrically independent from each other and cross in plan view.

以上により、半導体チップや回路基板の搭載領域を確保すると共に、信号や電源のワイヤー配線の自由度を向上することができる。   As described above, the mounting area of the semiconductor chip and the circuit board can be secured, and the degree of freedom of signal and power supply wire wiring can be improved.

本発明の半導体装置によると、複数のダイパッドに搭載面の垂直方向に一定以上の段差を設けることにより、複数の半導体チップ間や回路基板とにも段差を設けることができ、さらにオーバーラップさせて搭載することができるため、配線の自由度を向上させると共に半導体チップや回路基板の搭載領域を縮小することができる。   According to the semiconductor device of the present invention, by providing a plurality of die pads with a certain level or more in the vertical direction of the mounting surface, it is possible to provide a level difference between the plurality of semiconductor chips and the circuit board, and further overlap. Since it can be mounted, the degree of freedom of wiring can be improved and the mounting area of the semiconductor chip and circuit board can be reduced.

また、半導体チップのワイヤー配線用電極をチップの中央部に設けることにより、配線領域をチップの中央部に集中することができ、半導体チップや回路基板をオーバーラップさせる領域をより多く取ることができ、半導体チップや回路基板の搭載領域を縮小することができる。   Also, by providing the wire wiring electrode of the semiconductor chip at the center of the chip, the wiring area can be concentrated at the center of the chip, and more areas for overlapping the semiconductor chip and the circuit board can be taken. The mounting area of the semiconductor chip and the circuit board can be reduced.

また、回路基板の半導体チップ搭載領域に電源領域およびＧＮＤ領域を設けることにより、半導体チップに電源およびＧＮＤの供給を容易に行うことができ、配線の自由度を向上させることができる。
また、回路基板上に形成した電源領域およびＧＮＤ領域上に半導体チップを搭載する事によっても、信号配線と半導体チップへの電源およびＧＮＤの供給が容易となり、配線の自由度を向上させることができる。 Further, by providing the power supply region and the GND region in the semiconductor chip mounting region of the circuit board, the power and GND can be easily supplied to the semiconductor chip, and the degree of freedom of wiring can be improved.
Also, by mounting the semiconductor chip on the power supply area and the GND area formed on the circuit board, the power supply and the GND can be easily supplied to the signal wiring and the semiconductor chip, and the degree of freedom of the wiring can be improved. .

また、段差のある異なる半導体チップ間や回路基板とのワイヤー配線と上段チップからリードへのワイヤー配線を互いに接触しないようにクロスさせることが段差により容易となり、配線の自由度を向上させることができる。   In addition, it is easy to cross the wire wiring between different semiconductor chips with a step or between the circuit board and the wire wiring from the upper chip to the lead so as not to contact each other, and the degree of freedom of wiring can be improved. .

複数の半導体チップを搭載する半導体装置において、半導体チップを搭載するダイパッドを搭載面に垂直方向に所定の段差を設ける。下段のダイパッドに単独の半導体チップや積層された複数の半導体チップ、あるいは積層された回路基板と半導体チップを搭載したとしても、ダイパッドにこのような段差を設けることにより、搭載した半導体チップや回路基板をオーバーラップさせることができるので、半導体チップや回路基板の搭載領域を縮小することができると共に断面上のワイヤー配線空間の自由度を向上させることができる。   In a semiconductor device on which a plurality of semiconductor chips are mounted, a predetermined step is provided in a direction perpendicular to the mounting surface of the die pad on which the semiconductor chip is mounted. Even if a single semiconductor chip, a plurality of stacked semiconductor chips, or a stacked circuit board and a semiconductor chip are mounted on the lower die pad, by providing such a step on the die pad, the mounted semiconductor chip or circuit board Therefore, the mounting area of the semiconductor chip and the circuit board can be reduced, and the degree of freedom of the wire wiring space on the cross section can be improved.

以下、本発明の半導体装置における実施の形態について図面を参照しながら説明する。なお、以下の説明において、図５（ａ）、図５（ｂ）、図５（ｃ）にて説明した部材に対応する部材には同一符号を付し、説明を省略する。
（実施の形態１）
図１（ａ）は本発明の実施の形態１における半導体装置の構成を説明するための断面図であり、マルチチップ型と積層チップ型の複合半導体装置を例示している。 Hereinafter, embodiments of the semiconductor device of the present invention will be described with reference to the drawings. In the following description, members corresponding to those described in FIGS. 5A, 5B, and 5C are denoted by the same reference numerals, and description thereof is omitted.
(Embodiment 1)
FIG. 1A is a cross-sectional view for explaining the configuration of the semiconductor device according to the first embodiment of the present invention, and illustrates a multi-chip type and a laminated chip type composite semiconductor device.

図１（ａ）において、実施の形態１の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ａの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ｂの表面側に第２の半導体チップ３ｂが接着ペースト４ａでダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａと第２の半導体チップ３ｂとが電気的に接続され、第１の半導体チップ３ａ、第２の半導体チップ３ｂとリードフレームの各インナーリード部１ａとが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。   1A, the semiconductor device according to the first embodiment has a die pad 2a and a die pad 2b provided with a step in a direction perpendicular to the mounting surface, and a first semiconductor chip on the surface side of the die pad 2a in the lead frame. 3a is bonded with an adhesive paste 4a, and the second semiconductor chip 3b is die-bonded with the adhesive paste 4a on the surface side of the die pad 2b, and the first semiconductor chip 3a and the first semiconductor chip 3a are bonded to each other by a thin metal wire (gold wire) 5. The second semiconductor chip 3b is electrically connected, and the first semiconductor chip 3a, the second semiconductor chip 3b and each inner lead portion 1a of the lead frame are electrically connected, and are surrounded by the sealing resin 6. Thus, two chips are packaged into one package.

実施の形態１では、マルチチップ構成の半導体装置において、半導体チップを並べて搭載する際に用いるダイパッドに対して、第１の半導体チップ３ａにおけるダイパッド２ａと第２の半導体チップ３ｂにおけるダイパッド２ａとに段差を持たせチップ表面の高さに段差を持たせる。これによって、第２の半導体チップ３ｂが第１の半導体チップ３ａより低く位置する事により第１の半導体チップ３ａから第２の半導体チップ３ｂをまたぐ形で配線する金属細線（金線）５と第２の半導体チップ３ｂ表面との空間領域が大きく取れる事になり、平行して段差のないダイパッド及びチップ表面をもつマルチチップ型半導体装置よりも金属細線（金線）５の配線自由度を向上させ封止によるワイヤー変形等によるチップとワイヤー接触を防止することができる。
（実施の形態２）
図１（ｂ）は本発明の実施の形態２における半導体装置の構成を説明するための断面図であり、マルチチップ型と積層チップ型の複合半導体装置を例示している。 In the first embodiment, in a semiconductor device having a multi-chip configuration, there is a step difference between the die pad 2a in the first semiconductor chip 3a and the die pad 2a in the second semiconductor chip 3b with respect to the die pad used when the semiconductor chips are mounted side by side. Provide a step in the height of the chip surface. As a result, the second semiconductor chip 3b is positioned lower than the first semiconductor chip 3a, so that the thin metal wire (gold wire) 5 and the second semiconductor chip 3b are wired so as to straddle the second semiconductor chip 3b from the first semiconductor chip 3a. The space area with the surface of the second semiconductor chip 3b can be increased, and the degree of freedom of wiring of the fine metal wire (gold wire) 5 is improved as compared with the multi-chip type semiconductor device having the die pad and the chip surface which are parallel and have no step. Chip and wire contact due to wire deformation caused by sealing can be prevented.
(Embodiment 2)
FIG. 1B is a cross-sectional view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention, and illustrates a multi-chip type and a laminated chip type composite semiconductor device.

図１（ｂ）において、実施の形態２の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ａの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ｂの表面側に回路基板３ｃが接着ペースト４ａで接着され、さらに、回路基板３ｃ上に第２の半導体チップ３ｂが、その底面側で接着シート４ｂを介してダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａと回路基板３ｃが電気的に接続され、さらに第２の半導体チップ３ｂと回路基板３ｃが電気的に接続され、第１の半導体チップ３ａ、第２の半導体チップ３ｂ、回路基板３ｃとリードフレームの各インナーリード部１ａとが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。   1B, the semiconductor device of the second embodiment has a die pad 2a and a die pad 2b provided with a step in the direction perpendicular to the mounting surface, and a first semiconductor chip on the surface side of the die pad 2a in the lead frame. 3a is bonded with the adhesive paste 4a, the circuit board 3c is bonded with the adhesive paste 4a on the surface side of the die pad 2b, and the second semiconductor chip 3b is further bonded on the circuit board 3c with the adhesive sheet 4b on the bottom surface side. The first semiconductor chip 3a and the circuit board 3c are electrically connected by a thin metal wire (gold wire) 5, and the second semiconductor chip 3b and the circuit board 3c are further electrically connected. The first semiconductor chip 3a, the second semiconductor chip 3b, the circuit board 3c and each inner lead portion 1a of the lead frame are electrically connected. Is, the mold of the outer circumference is one package 2 chips made by the sealing resin 6.

実施の形態１では、マルチチップ構成の半導体装置において、半導体チップを並べて搭載する際に用いるダイパッドに対して、第１の半導体チップ３ａにおける裏面のチップエッジと回路基板３ｃのチップ表面エッジが接触しないでオーバーラップできるように、ダイパッド２ａとダイパッド２ｂに回路基板３ｃの厚さより大きい段差を持たせる。これによって、ダイパッド２ａとダイパッド２ｂ間の間隔が必要なくなり、平行して段差のないダイパッドをもつマルチチップ型半導体装置よりもチップ間を詰める事が可能となり、半導体チップや回路基板の搭載領域を縮小することができると共に配線の自由度を向上させることができる。
（実施の形態３）
図１（ｃ）は本発明の実施の形態３における半導体装置の構成を説明するための断面図であり、マルチチップ型と積層チップ型の複合半導体装置を例示している。 In the first embodiment, in the multi-chip semiconductor device, the chip edge on the back surface of the first semiconductor chip 3a and the chip surface edge of the circuit board 3c do not contact the die pad used when mounting the semiconductor chips side by side. The die pad 2a and the die pad 2b are provided with a step larger than the thickness of the circuit board 3c so that they can be overlapped with each other. This eliminates the need for a space between the die pad 2a and the die pad 2b, and allows for more space between the chips than a multi-chip type semiconductor device having a die pad that is parallel and has no step, thereby reducing the mounting area of the semiconductor chip and circuit board. And the degree of freedom of wiring can be improved.
(Embodiment 3)
FIG. 1C is a cross-sectional view for explaining the configuration of the semiconductor device according to the third embodiment of the present invention, and illustrates a multi-chip type and a laminated chip type composite semiconductor device.

図１（ｃ）において、実施の形態３の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ｂの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ａの表面側に第２の半導体チップ３ｂが接着ペースト４ａで接着され、さらに、回路基板３ｃが接着シート４ｂを介してダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａが回路基板３ｃの中央部に形成された上部電極に電気的に接続され、さらに、第２の半導体チップ３ｂが回路基板３ｃの上部電極に電気的に接続され、第１の半導体チップ３ａ、第２の半導体チップ３ｂ、回路基板３ｃとリードフレームの各インナーリード部１ａとが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。   In FIG. 1C, the semiconductor device of the third embodiment has a die pad 2a and a die pad 2b provided with a step in a direction perpendicular to the mounting surface, and the first semiconductor chip on the surface side of the die pad 2b in the lead frame. 3a is bonded with an adhesive paste 4a, a second semiconductor chip 3b is bonded to the surface of the die pad 2a with an adhesive paste 4a, and a circuit board 3c is die-bonded via an adhesive sheet 4b. The first semiconductor chip 3a is electrically connected to the upper electrode formed in the central portion of the circuit board 3c by the thin wire (gold wire) 5, and further, the second semiconductor chip 3b is electrically connected to the upper electrode of the circuit board 3c. The first semiconductor chip 3a, the second semiconductor chip 3b, the circuit board 3c, and the inner lead portions 1a of the lead frame are electrically connected. Is connected, the mold of the outer circumference is one package 2 chip is made by the sealing resin 6.

このように、実施の形態３では、第１の半導体チップ３ａにおける裏面のチップエッジと第２の半導体チップ３ｂや回路基板３ｃの表面エッジが接触しないでオーバーラップできるようにダイパッド２ａとダイパッド２ｂが第２の半導体チップ３ｂもしくは回路基板３ｃを足した厚さより大きい段差を持つ。このように、ダイパッド２ａ，ダイパッド２ｂ間の段差を第２の半導体チップ３ｂもしくは回路基板３ｃを足した厚さより大きくすることにより、第１の半導体チップ３ａ，第２の半導体チップ３ｂ，回路基板３ｃをオーバーラップして配置できるので、平行して段差のないダイパッドをもつマルチチップ型半導体装置よりもチップ間を詰める事が可能となり、半導体チップや回路基板の搭載領域を縮小することができると共に配線の自由度を向上させることができる。この時、回路基板３ｃは上部中央に電極を設けることにより、段差を回路基板３ｃと第２の半導体チップ３間のワイヤー配線を考慮したぶんだけ大きくすることにより、実施の形態２の場合よりさらにオーバーラップすることができ、半導体チップや回路基板の搭載領域を縮小することができると言う効果をより大きくすることができる。
（実施の形態４）
図１（ｄ）は本発明の実施の形態４における半導体装置の構成を説明するための断面図であり、マルチチップ型の半導体装置を例示している。 Thus, in the third embodiment, the die pad 2a and the die pad 2b are arranged so that the chip edge on the back surface of the first semiconductor chip 3a and the surface edge of the second semiconductor chip 3b or the circuit board 3c can be overlapped without contacting each other. There is a step larger than the thickness obtained by adding the second semiconductor chip 3b or the circuit board 3c. Thus, by making the step between the die pad 2a and the die pad 2b larger than the thickness of the second semiconductor chip 3b or the circuit board 3c, the first semiconductor chip 3a, the second semiconductor chip 3b, and the circuit board 3c. Can be placed in an overlapping manner, making it possible to close the space between chips more than a multi-chip type semiconductor device having a die pad that is parallel and flat, and can reduce the mounting area of the semiconductor chip and circuit board and wiring The degree of freedom can be improved. At this time, the circuit board 3c is provided with an electrode in the upper center, and the level difference is increased by considering the wire wiring between the circuit board 3c and the second semiconductor chip 3, thereby further increasing the case of the second embodiment. The effect that it can overlap and the mounting area | region of a semiconductor chip or a circuit board can be reduced can be enlarged more.
(Embodiment 4)
FIG. 1D is a cross-sectional view for explaining the configuration of the semiconductor device according to the fourth embodiment of the present invention, and exemplifies a multichip type semiconductor device.

図１（ｄ）において、実施の形態４の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ｂの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ａの表面側にワイヤー配線用電極をチップ内部に集中させた第２の半導体チップ３ｂが接着ペースト４ａで接着ダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａ、第２の半導体チップ３ｂとリードフレームの各インナーリード部１ａが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。   In FIG. 1D, the semiconductor device of the fourth embodiment has a die pad 2a and a die pad 2b provided with a step in the direction perpendicular to the mounting surface, and the first semiconductor chip on the surface side of the die pad 2b in the lead frame. 3a is bonded with an adhesive paste 4a, and a second semiconductor chip 3b in which wire wiring electrodes are concentrated inside the chip on the surface side of the die pad 2a is bonded and bonded with the adhesive paste 4a. The first semiconductor chip 3a, the second semiconductor chip 3b, and the inner lead portions 1a of the lead frame are electrically connected to each other by the wire 5), and the outer resin is molded with the sealing resin 6 so that the two chips are packaged in one package. It has become.

実施の形態４では、第２の半導体チップ３ｂのワイヤー配線用電極をチップ中央部に集中させて、かつ、第１の半導体チップ３ａの裏面と第２の半導体チップ３ｂの表面が接触しないでオーバーラップできるようにダイパッド２ａとダイパッド２ｂが第２の半導体チップ３ｂの厚さより大きい段差を持ち、第１の半導体チップ３ａと第２の半導体チップ３ｂをオーバーラップさせて配置した状態で、第１の半導体チップ３ａと第２の半導体チップ３ｂのチップ内部に集中させた電極をワイヤー配線することにより、第２の半導体チップ３ｂのワイヤー配線用電極をチップ周辺に設ける場合よりもオーバーラップする領域を大きくすることができ、半導体チップや回路基板の搭載領域を縮小することができる。   In the fourth embodiment, the wire wiring electrodes of the second semiconductor chip 3b are concentrated at the center of the chip, and the back surface of the first semiconductor chip 3a and the surface of the second semiconductor chip 3b are not in contact with each other. In a state where the die pad 2a and the die pad 2b have a step larger than the thickness of the second semiconductor chip 3b so that they can be wrapped and the first semiconductor chip 3a and the second semiconductor chip 3b are overlapped, By wire-wiring the electrodes concentrated inside the semiconductor chip 3a and the second semiconductor chip 3b, the overlapping area is made larger than when the wire-wiring electrodes of the second semiconductor chip 3b are provided around the chip. The mounting area of the semiconductor chip and the circuit board can be reduced.

（実施の形態５）
図２（ａ）は本発明の実施の形態５における半導体装置の構成を説明するための断面図であり、マルチチップ型と積層チップ型の複合半導体装置を例示している。図２（ｂ）は本発明の実施の形態５における回路基板の構成を説明するための平面図，図２（ｃ）は本発明の実施の形態５における回路基板の構成を説明するための断面図である。 (Embodiment 5)
FIG. 2A is a cross-sectional view for explaining the configuration of the semiconductor device according to the fifth embodiment of the present invention, and illustrates a multi-chip type and a laminated chip type composite semiconductor device. FIG. 2B is a plan view for explaining the configuration of the circuit board in the fifth embodiment of the present invention, and FIG. 2C is a cross section for explaining the configuration of the circuit board in the fifth embodiment of the present invention. FIG.

図２（ａ），図２（ｂ），図２（ｃ）において、実施の形態５の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ａの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ｂの表面側に回路基板３ｃが接着ペースト４ａで接着され、さらに、回路基板３ｃ上に第２の半導体チップ３ｂが、その底面側で接着シート４ｂを介してダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａと回路基板３ｃが電気的に接続され、さらに、第２の半導体チップ３ｂと回路基板３ｃが電気的に接続され、第１の半導体チップ３ａ、第２の半導体チップ３ｂ、回路基板３ｃとリードフレームの各インナーリード部１ａとが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。   2A, 2B, and 2C, the semiconductor device of the fifth embodiment includes a die pad 2a and a die pad 2b that are provided with a step in a direction perpendicular to the mounting surface, and a lead frame. The first semiconductor chip 3a is bonded to the surface side of the die pad 2a with the adhesive paste 4a, the circuit board 3c is bonded to the surface side of the die pad 2b with the adhesive paste 4a, and the second semiconductor chip is further mounted on the circuit board 3c. 3b is a structure in which the bottom surface side is die-bonded via an adhesive sheet 4b, and the first semiconductor chip 3a and the circuit board 3c are electrically connected by a metal thin wire (gold wire) 5; The semiconductor chip 3b and the circuit board 3c are electrically connected, and the first semiconductor chip 3a, the second semiconductor chip 3b, the circuit board 3c, and each inner frame of the lead frame are connected. And de unit 1a are electrically connected, the mold of the outer circumference is one package 2 chip is made by the sealing resin 6.

実施の形態５では、電源、ＧＮＤを供給するためのパッドを有したワイヤー配線可能な領域を持ち、さらに、回路基板３ｃ上に２層以上の信号用の配線層３ｃ−１とは独立した電源、ＧＮＤ３ｃ−３用の導電層を持つことで、第２の半導体チップ３ｂへ安定したインピーダンス成分での電源、ＧＮＤ供給や、第１の半導体チップ３ａへの中間バス配線が可能となり、ロングワイヤーを出来るだけ避けてインピーダンスの不整合を低減する事となるので高速動作の妨げになるリターンパス、グラウンドバウンズ等の電気的対策が可能になる。なお、実施の形態５では実施の形態２における回路基板の構成を例に説明したが、実施の形態３における回路基板についても同様の効果を得ることができる。
（実施の形態６）
図３（ａ）は本発明の実施の形態６における半導体装置の構成を説明するための断面図であり、マルチチップ型と積層チップ型の複合半導体装置を例示している。図３（ｂ）は本発明の実施の形態６における回路基板の構成を説明するための平面図，図３（ｃ）は本発明の実施の形態６における回路基板の構成を説明するための断面図である。 In the fifth embodiment, the power supply has a wire-wiring area having a pad for supplying GND, and the power supply is independent of the signal wiring layer 3c-1 having two or more layers on the circuit board 3c. By having a conductive layer for GND 3c-3, it becomes possible to supply power and GND with a stable impedance component to the second semiconductor chip 3b, and to connect the intermediate bus to the first semiconductor chip 3a. By avoiding impedance mismatching as much as possible, it is possible to take electrical measures such as return path and ground bounce that hinder high-speed operation. In the fifth embodiment, the configuration of the circuit board in the second embodiment has been described as an example, but the same effect can be obtained for the circuit board in the third embodiment.
(Embodiment 6)
FIG. 3A is a cross-sectional view for explaining the configuration of the semiconductor device according to the sixth embodiment of the present invention, and illustrates a multi-chip type and a laminated chip type composite semiconductor device. FIG. 3B is a plan view for explaining the configuration of the circuit board according to the sixth embodiment of the present invention, and FIG. 3C is a cross section for explaining the configuration of the circuit board according to the sixth embodiment of the present invention. FIG.

図３（ａ），図３（ｂ），図３（ｃ）において、実施の形態６の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ａの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ｂの表面側に第２の半導体チップ３ｂが接着ペースト４ａで接着され、さらに、回路基板３ｃが接着シート４ｂを介してダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａと回路基板３ｃが電気的に接続され、さらに、第２の半導体チップ３ｂと回路基板３ｃが電気的に接続され、第１の半導体チップ３ａ、第２の半導体チップ３ｂ、回路基板３ｃとリードフレームの各インナーリード部１ａとが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。   3A, FIG. 3B, and FIG. 3C, the semiconductor device of the sixth embodiment has a die pad 2a and a die pad 2b that are provided with a step in a direction perpendicular to the mounting surface, and a lead frame. The first semiconductor chip 3a is bonded to the surface side of the die pad 2a with the adhesive paste 4a, the second semiconductor chip 3b is bonded to the surface side of the die pad 2b with the adhesive paste 4a, and the circuit board 3c is further bonded to the adhesive sheet 4b. The first semiconductor chip 3a and the circuit board 3c are electrically connected by a thin metal wire (gold wire) 5, and the second semiconductor chip 3b and the circuit board 3c are electrically connected. The first semiconductor chip 3a, the second semiconductor chip 3b, the circuit board 3c and each inner lead part 1a of the lead frame are electrically connected. Mold outer circumference is one package 2 chips made by the sealing resin 6.

実施の形態６では、第１の半導体チップ３ａにおける裏面のチップエッジと第２の半導体チップ３ｂや回路基板３ｃの表面エッジが接触しないでオーバーラップできるようにダイパッド２ａとダイパッド２ｂが第２の半導体チップ３ｂもしくは回路基板３ｃを足した厚さより大きい段差を持つ。このように、ダイパッド２ａ，ダイパッド２ｂ間の段差を第２の半導体チップ３ｂもしくは回路基板３ｃを足した厚さより大きくすることにより、第１の半導体チップ３ａ，第２の半導体チップ３ｂ，回路基板３ｃをオーバーラップして配置できるので、平行して段差のないダイパッドをもつマルチチップ型半導体装置よりもチップ間を詰める事が可能となり、半導体チップや回路基板の搭載領域を縮小することができると共に配線の自由度を向上させることができる。   In the sixth embodiment, the die pad 2a and the die pad 2b are connected to the second semiconductor so that the chip edge on the back surface of the first semiconductor chip 3a and the surface edge of the second semiconductor chip 3b or the circuit board 3c can be overlapped without contacting. A step larger than the thickness of the chip 3b or the circuit board 3c is added. Thus, by making the step between the die pad 2a and the die pad 2b larger than the thickness of the second semiconductor chip 3b or the circuit board 3c, the first semiconductor chip 3a, the second semiconductor chip 3b, and the circuit board 3c. Can be placed in an overlapping manner, making it possible to close the space between chips more than a multi-chip type semiconductor device having a die pad that is parallel and flat, and can reduce the mounting area of the semiconductor chip and circuit board and wiring The degree of freedom can be improved.

なお、実施の形態６では実施の形態３における回路基板の構成を例に説明したが、実施の形態２における回路基板についても同様の効果を得ることができる。
（実施の形態７）
図４（ａ）は本発明の実施の形態７における半導体装置の構成を説明するための断面図であり、マルチチップ型の半導体装置を例示している。図４（ｂ）は本発明の実施の形態７におけるワイヤー配線を説明するための平面図である。 In the sixth embodiment, the configuration of the circuit board in the third embodiment has been described as an example, but the same effect can be obtained for the circuit board in the second embodiment.
(Embodiment 7)
FIG. 4A is a cross-sectional view for explaining the configuration of the semiconductor device according to the seventh embodiment of the present invention, and exemplifies a multichip type semiconductor device. FIG.4 (b) is a top view for demonstrating the wire wiring in Embodiment 7 of this invention.

図４（ａ），図４（ｂ）において、実施の形態７の半導体装置は、互いに搭載面に垂直方向に段差を設けたダイパッド２ａおよびダイパッド２ｂを有し、リードフレームにおけるダイパッド２ａの表面側に第１の半導体チップ３ａが接着ペースト４ａで接着され、ダイパッド２ｂの表面側に第２の半導体チップ３ｂが接着ペースト４ａで接着ダイボンディングされた構造であり、金属細線（金線）５により第１の半導体チップ３ａと回路基板３ｃが電気的に接続され、さらに、第２の半導体チップ３ｂと回路基板３ｃが電気的に接続され、第１の半導体チップ３ａ、第２の半導体チップ３ｂ、回路基板３ｃとリードフレームの各インナーリード部１ａとが電気的に接続され、封止樹脂６による外囲のモールドがなされて２チップを１パッケージ化している。この時、第１の半導体チップ３ａからインナーリード１ａへ、また、第１の半導体チップ３ａから第２の半導体チップ３ｂへ、さらに、第２の半導体チップ３ｂからインナーリード１ａのワイヤー配線はお互いのワイヤーが平面上クロスして見えて立体的には接触しない様に配線することができる。   4 (a) and 4 (b), the semiconductor device of the seventh embodiment has a die pad 2a and a die pad 2b provided with a step in a direction perpendicular to the mounting surface, and the surface side of the die pad 2a in the lead frame. The first semiconductor chip 3a is bonded with the adhesive paste 4a, and the second semiconductor chip 3b is bonded to the surface of the die pad 2b with the adhesive paste 4a. The metal thin wire (gold wire) 5 The first semiconductor chip 3a and the circuit board 3c are electrically connected, and the second semiconductor chip 3b and the circuit board 3c are electrically connected. The first semiconductor chip 3a, the second semiconductor chip 3b, and the circuit The substrate 3c and the inner lead portions 1a of the lead frame are electrically connected, and the outer mold is formed by the sealing resin 6 so that two chips are packaged in one package. It has turned into. At this time, the wire wiring from the first semiconductor chip 3a to the inner lead 1a, from the first semiconductor chip 3a to the second semiconductor chip 3b, and from the second semiconductor chip 3b to the inner lead 1a is mutually connected. The wires can be wired so that they appear to cross on the plane and do not come in contact in three dimensions.

実施の形態７では、配線自由度を高めるため、第１の半導体チップ３ａからインナーリード１ａへ、また、第１の半導体チップ３ａから第２の半導体チップ３ｂへ、さらに、第２の半導体チップ３ｂからインナーリード１ａのワイヤー配線はお互いのワイヤーが平面上クロスして見えて立体的には接触しない様に出来る事からワイヤーの配線自由度が向上する。   In the seventh embodiment, in order to increase the degree of freedom of wiring, from the first semiconductor chip 3a to the inner lead 1a, from the first semiconductor chip 3a to the second semiconductor chip 3b, and further to the second semiconductor chip 3b. Therefore, the wiring of the inner lead 1a can be made such that the wires cross each other on the plane and do not come into contact in a three-dimensional manner.

なお、実施の形態７では実施の形態４の構成を例に説明したが、実施の形態１，実施の形態２，実施の形態３，実施の形態５あるいは実施の形態６における構成に対して適応しても同様の効果を得ることができる。   In the seventh embodiment, the configuration of the fourth embodiment has been described as an example. However, the configuration of the first embodiment, the second embodiment, the third embodiment, the fifth embodiment, or the sixth embodiment is applied. However, the same effect can be obtained.

本発明は、半導体チップや回路基板の搭載領域を縮小することができると共に配線の自由度を向上させることができ、複数の半導体チップをパッケージに搭載してなる半導体装置等に有効である。   INDUSTRIAL APPLICABILITY The present invention can reduce the mounting area of semiconductor chips and circuit boards and can improve the degree of freedom of wiring, and is effective for a semiconductor device or the like in which a plurality of semiconductor chips are mounted in a package.

（ａ）本発明の実施の形態１における半導体装置の構成を説明するための断面図 （ｂ）本発明の実施の形態２における半導体装置の構成を説明するための断面図 （ｃ）本発明の実施の形態３における半導体装置の構成を説明するための断面図 （ｄ）本発明の実施の形態４における半導体装置の構成を説明するための断面図(A) Cross-sectional view for explaining the configuration of the semiconductor device according to the first embodiment of the present invention (b) Cross-sectional view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention (c) Sectional drawing for demonstrating the structure of the semiconductor device in Embodiment 3 (d) Sectional drawing for demonstrating the structure of the semiconductor device in Embodiment 4 of this invention （ａ）本発明の実施の形態５における半導体装置の構成を説明するための断面図 （ｂ）本発明の実施の形態５における回路基板の構成を説明するための平面図 （ｃ）本発明の実施の形態５における回路基板の構成を説明するための断面図(A) Cross-sectional view for explaining the configuration of the semiconductor device in the fifth embodiment of the present invention (b) Plan view for explaining the configuration of the circuit board in the fifth embodiment of the present invention (c) Sectional drawing for demonstrating the structure of the circuit board in Embodiment 5. （ａ）本発明の実施の形態６における半導体装置の構成を説明するための断面図 （ｂ）本発明の実施の形態６における回路基板の構成を説明するための平面図 （ｃ）本発明の実施の形態６における回路基板の構成を説明するための断面図(A) Sectional view for explaining the configuration of the semiconductor device in the sixth embodiment of the present invention (b) Plan view for explaining the configuration of the circuit board in the sixth embodiment of the present invention (c) Sectional drawing for demonstrating the structure of the circuit board in Embodiment 6. （ａ）本発明の実施の形態７における半導体装置の構成を説明するための断面図 （ｂ）本発明の実施の形態７におけるワイヤー配線を説明するための平面図(A) Sectional drawing for demonstrating the structure of the semiconductor device in Embodiment 7 of this invention (b) The top view for demonstrating the wire wiring in Embodiment 7 of this invention （ａ）従来の半導体装置における要部の構成を示す断面図 （ｂ）従来の半導体チップを積層したマルチチップタイプの半導体装置における要部の構成を示す断面図 （ｃ）従来の半導体チップを並べたマルチチップタイプの半導体装置における要部の構成を示す断面図(A) Cross-sectional view showing configuration of main part in conventional semiconductor device (b) Cross-sectional view showing configuration of main part in multi-chip type semiconductor device in which conventional semiconductor chips are stacked (c) Arrangement of conventional semiconductor chips Sectional drawing which shows the structure of the principal part in a multi-chip type semiconductor device

符号の説明Explanation of symbols

１ａ インナーリード部
１ｂ アウターリード部
２ ダイパッド
２ａ ダイパッド
２ｂ ダイパッド
３ 半導体チップ
３ａ 第１の半導体チップ
３ｂ 第２の半導体チップ
３ｂ−１ チップ搭載エリア
３ｂ−２ ボンディングパッド
３ｃ−１ 配線層
３ｃ−３ 電源またはＧＮＤ
３ｃ 回路基板
４ 接着剤
４ａ 接着ペースト
４ｂ 接着シート
５ 金属細線
６ 封止樹脂
７ 実装基板 DESCRIPTION OF SYMBOLS 1a Inner lead part 1b Outer lead part 2 Die pad 2a Die pad 2b Die pad 3 Semiconductor chip 3a 1st semiconductor chip 3b 2nd semiconductor chip 3b-1 Chip mounting area 3b-2 Bonding pad 3c-1 Wiring layer 3c-3 Power supply or GND
3c Circuit board 4 Adhesive 4a Adhesive paste 4b Adhesive sheet 5 Metal fine wire 6 Sealing resin 7 Mounting board

Claims (3)

複数の半導体チップを搭載する半導体装置であって、
前記半導体装置の電極となるリードフレームと、
前記複数の半導体チップおよびリードフレームを互いに電気的に接続するワイヤー配線と、
前記リードフレームに保持されその搭載面の垂直方向に段差を設け前記複数の半導体チップを搭載する複数のダイパッドと
を有し、前記段差が前記半導体チップの厚みより大きく、前記複数の半導体チップの一部を互いにオーバーラップさせて前記ダイパッドに搭載可能であり、前記半導体チップの内の１または２以上の半導体チップがワイヤー配線用電極をチップ中央部に備えることを特徴とする半導体装置。 A semiconductor device mounting a plurality of semiconductor chips,
A lead frame serving as an electrode of the semiconductor device;
Wire wiring for electrically connecting the plurality of semiconductor chips and the lead frame to each other;
Have a plurality of die pads for mounting the plurality of semiconductor chips provided with a step in the vertical direction of the mounting surface is held by the lead frame, greater than the thickness of the step is the semiconductor chip, the plurality of semiconductor chips one parts and can be mounted on the die pad by overlapping the semiconductor device 1 or 2 or more semiconductor chips of said semiconductor chip and said Rukoto an electrode wire wiring chip central portion. 複数の半導体チップを搭載する半導体装置であって、
前記半導体装置の電極となるリードフレームと、
前記半導体チップの内の１または２以上の半導体チップと積層させる１または２以上の回路基板と、
前記複数の半導体チップおよびリードフレームならびに前記１または２以上の回路基板を互いに電気的に接続するワイヤー配線と、
前記リードフレームに保持されその搭載面の垂直方向に前記半導体チップと前記回路基板を積層した厚みより大きな段差を設け前記複数の半導体チップを搭載する複数のダイパッドと
を有し、前記複数の半導体チップまたは前記回路基板の一部を互いにオーバーラップさせて前記ダイパッドに搭載可能であり、前記半導体チップの内の１または２以上の半導体チップがワイヤー配線用電極をチップ中央部に備え、前記回路基板上に電源供給用のワイヤー配線用電極を有することを特徴とする半導体装置。 A semiconductor device mounting a plurality of semiconductor chips,
A lead frame serving as an electrode of the semiconductor device;
One or more circuit boards laminated with one or more semiconductor chips of the semiconductor chips;
Wire wiring for electrically connecting the plurality of semiconductor chips and lead frames and the one or more circuit boards to each other;
A plurality of die pads mounted on the lead frame and provided with a step larger than a thickness of the semiconductor chip and the circuit board stacked in a direction perpendicular to the mounting surface;
And a plurality of the semiconductor chips or a part of the circuit board can be mounted on the die pad so that one or more of the semiconductor chips have a wire wiring electrode as a chip. A semiconductor device comprising a wire wiring electrode for power supply on the circuit board, provided at a central portion . 前記ワイヤー配線は互いに電気的に独立し、平面的にはクロスすることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the wire wirings are electrically independent from each other and cross in plan view .
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