JP2014204082A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reduction in the occurrence of a void when a plurality of product formation parts are collectively covered and molded by an encapsulation resin.SOLUTION: A semiconductor device manufacturing method comprises: a process of preparing a wiring board where a semiconductor chip is mounted on each of a plurality of product formation parts; a process of mounting the wiring board on a molding mold having a cavity for collectively covering the plurality of product formation parts and a plurality of gates connected to the cavity; and a process of filling an encapsulation resin from the plurality of gates to inside the cavity to form an encapsulation resin layer which collectively covers the plurality of product formation parts of the wiring board. At the time of filling the encapsulation resin, the encapsulation resin is filled from the plurality of gates to inside the cavity in a manner such that a flow of the encapsulation resin filled from the gate located at the farthest point among the plurality of gates is distributed.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, it has become necessary to stack two or more semiconductor chips that constitute a semiconductor device in accordance with the reduction in size, thickness, and capacity of electronic devices. In stacking, a part of the upper semiconductor chip is protruded from the lower semiconductor chip (hereinafter referred to as an overhang). This type of semiconductor device is described in Patent Document 1.

  The two-stage stacked type will be briefly described. Two semiconductor chips are stacked so as to cross each other, mounted on a wiring board, and sealed with a thermosetting resin. At the time of sealing, the wiring board on which the stacked semiconductor chips are mounted is placed in a mold die of a sealing device, and molten resin is poured into a cavity of the mold die. When the resin is poured, a portion including a portion for storing the solid resin is called a cal and will be described later.

  By the way, the arrangement of the semiconductor chips is determined in consideration of the wiring board size, the number of products acquired, and the like, and it is important that the resin sealing is performed without any problem. However, in recent years, smaller packages have been demanded, and as a result, techniques for stacking semiconductor chips have been developed as described above. However, on the other hand, the following problems have also occurred, and what is important when considering this problem is the part called overhang. Since the electrodes called pads of each semiconductor chip must be connected to the electrodes of the wiring board by Au wires or the like, it is necessary to arrange the upper semiconductor chip rotated 90 degrees with respect to the lower semiconductor chip. At this time, a part of the upper semiconductor chip protrudes from the lower semiconductor chip, and the part becomes overhanging.

  When sealing semiconductor chips stacked with overhangs with resin, the poured resin is a fluid with viscosity, so depending on the location of the semiconductor chip, the resin may not enter properly under the overhang. As a result, since the resin is cured as it is, an unfilled portion of the resin may be formed. FIG. 11 shows a schematic view of the resin not filled.

  In the past, in order to prevent this unfilling of the resin, a resin having an optimum viscosity or a filler diameter contained in the resin has been selected, or the speed at which the resin is poured has been adjusted. However, as the thickness of the semiconductor chip becomes thinner and the thin package becomes mainstream, the height under the overhang becomes lower, so that it becomes more difficult to improve the resin filling property.

  On the other hand, Patent Document 2 discloses a MAP (Mold Array Process) that forms a sealing resin so as to collectively cover a plurality of product forming portions on a wiring board on which a semiconductor chip is mounted in each of the plurality of product forming portions. A method for manufacturing a semiconductor device of the type is disclosed.

  The MAP method reduces the assembly cost by sharing the outside of the product formation area of the mold and the wiring board. Therefore, in the MAP method, since the mold mold is shared, the gate position for injecting the sealing resin is also arranged at a predetermined position on the wiring board.

  For this reason, the end gate position with respect to the position of the semiconductor chip mounted on the endmost product forming portion on the gate side varies depending on the product depending on the size of the plurality of product forming portions formed in the product forming region of the wiring board.

JP 2009-99697 A JP 2012-169398 A

  When the MAP method is applied to the resin sealing of the stacked semiconductor device having the overhang described above, the following problems occur.

  Due to the variation described above, when the outermost gate is arranged outside the semiconductor chip mounted on the outermost product forming portion in the resin molding, the flow rate of the sealing resin flowing outside the product forming region is The flow rate of the sealing resin flowing in the product formation region is larger. Due to this difference in flow rate, there is a problem that voids are generated under the overhang of the semiconductor chip mounted on the product forming part on the air vent side opposite to the gate. When voids are generated in the sealing resin, the voids expand during reflow, causing package cracks and reducing the reliability of the semiconductor device.

  According to an aspect of the present invention, a step of preparing a wiring board on which a plurality of product forming portions are arranged, a step of mounting a semiconductor chip on each of the plurality of product forming portions of the wiring substrate, and the plurality of products A cavity that collectively covers the formation portion, a step of mounting the wiring board on a mold mold having a plurality of gates connected to the cavity, and a sealing resin is filled into the cavity from the plurality of gates, Forming a sealing resin layer that collectively covers the plurality of product forming portions of the wiring board, and when filling the sealing resin, from the gate located at the end of the plurality of gates Provided is a method for manufacturing a semiconductor device, wherein the sealing resin is filled into the cavity from the plurality of gates so that the flow of the filling sealing resin is dispersed.

  As described above, the flow rate of the sealing resin flowing outside the product formation region defined by the plurality of product formation portions and the flow rate of the sealing resin flowing inside the product formation region can be substantially equalized. Generation of voids can be reduced. Further, by reducing the generation of voids, the generation of package cracks during reflow can be reduced, and the reliability of the semiconductor device can be improved.

It is a top view which shows schematic structure of the MCP type semiconductor device with which the manufacturing method by the 1st Embodiment of this invention is applied. It is sectional drawing by the A-A 'line of FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device by the 1st Embodiment of this invention to process order. It is sectional drawing for demonstrating the manufacturing process following FIG. It is a top view which shows the relationship between the product formation part of the wiring board with which the manufacturing method by 1st Embodiment is applied, and the gate in the molding die of a transfer mold apparatus. It is sectional drawing for demonstrating the mold process in order of the process in the manufacturing method by 1st Embodiment. It is a top view which shows the middle of the mold process in the manufacturing method by 1st Embodiment. FIG. 8 is a plain view showing a state in which the molding process shown in FIG. 7 is completed and the resin is cured to form a sealing body. It is a top view which shows the positional relationship of the product formation area of the wiring board with which the manufacturing method by the 2nd Embodiment of this invention is applied, and the gate of a mold die. It is a top view which shows the positional relationship of the product formation area | region of the wiring board with which the manufacturing method by the 3rd Embodiment of this invention is applied, and the gate of a mold die. The cross-sectional schematic diagram for demonstrating the resin unfilling at the time of resin-sealing a semiconductor chip is shown. FIG. 6 is a plan view (FIG. A) showing the relationship between a plurality of culls provided in the mold and a wiring mother board, and an enlarged view (FIG. B) for explaining the resin flowing through the gate from the leftmost cull. The top view (figure a) which shows arrangement | positioning of the semiconductor chip by the proposal of this invention, and the positional relationship of the several cull provided in the mold metal, and the enlarged view for demonstrating resin which flows through the gate from the leftmost cull b). It is a top view for demonstrating the flow surface of the conventional resin at the time of resin molding. It is a top view for demonstrating a mode that the unfilling of resin is produced under the overhang of a laminated semiconductor chip in the case of a resin mold. It is a top view for demonstrating the flow surface of resin at the time of arrange | positioning a laminated semiconductor chip in front of the endmost gate by the proposal of this invention. It is a top view which shows the resin flow path in the case of the resin flow surface by the proposal of this invention.

  Before describing several embodiments of the present invention, discussions and test results made by the present inventors will be described.

  The present invention intends to propose the positional relationship between the cull outlets at the left and right ends of the mold and the arrangement of the semiconductor chip, and thereby a method for remarkably improving the filling property at the time of resin sealing. It is.

  There is a certain degree of freedom in the arrangement of the semiconductor chip, and there is no restriction that absolutely restricts the arrangement. Of course, if the dimensions of the product, the number of acquisitions, and the like are taken into consideration, the arrangement plan is narrowed down to some extent, but the resin filling property cannot be sacrificed.

  A preferred example of the present invention proposes to arrange a semiconductor chip just at the end of the cull outlet so as to block the resin flow path.

  The principle of the present invention will be described below. First, FIG. 12 shows a conventional resin flow path in a wiring board (hereinafter referred to as a wiring mother board) on which a laminated semiconductor chip C is mounted in a plurality of product forming portions. 12A is a plan view showing the relationship between a plurality of culls 240 provided in the mold and the wiring mother board. FIG. 12B shows the resin flowing from the leftmost cull 240 through the gate 260. FIG. It is an enlarged view for demonstrating.

  Speaking of the leftmost cull 240, conventionally, the resin from the outermost gate 260 in the leftmost cull 240 hardly flows into the semiconductor chip C in front of the eyes and flows through the end of the product formation region (mold region). (Bold dotted arrow in FIG. 12B). Even if it is a conventional product, a semiconductor chip may be arranged in front of the cull outlet, but it is not intentionally arranged, and it does not consider increasing the resin filling property. Therefore, in the following, a state where the resin collides with the semiconductor chip will be described.

  FIG. 13A is a plan view showing the positional relationship between a semiconductor chip arrangement according to the proposal of the present invention and a plurality of culls. FIG. 13B is a diagram for explaining the resin flowing through the gate from the cull outlet at the left end. It is an enlarged view. As shown in FIG. 13B, since the semiconductor chip C is arranged in front of the resin flow path, the resin divides the flow path, and the flow rate flowing through the end of the product formation area (mold area) decreases. Next, what the amount of the divided resin has will be described.

  FIG. 14 is a plan view for explaining a conventional resin flow surface during resin molding. As shown in FIG. 12B, in the case of resin molding, when more resin flows through the end of the product formation region (mold region), the state of the flow surface of the resin immediately before completion of filling is as shown in FIG. . In this case, the poured resin finally takes a flow path concentrated at one point, and as a result, the resin is not filled under the overhang of the laminated semiconductor chip C. This is shown in FIG.

  FIG. 15 is a plan view for explaining a state in which unfilled resin is generated under the overhang of the laminated semiconductor chip C in the resin molding. The black part shown in FIG. 15 shows the unfilled portion of the resin, and the unfilled portion occurs due to the influence of the fluidity of the resin.

  Next, the reason why the resin flow concentrated at one point is likely to cause unfilling of the resin will be described.

  FIG. 16 is a plan view for explaining the flow surface of the resin when the laminated semiconductor chip C is arranged in front of the cull outlet, particularly the endmost gate, according to the proposal of the present invention. In this case, since the amount of resin flowing through the end of the product formation region (mold region) is small, the flow of resin at the left and right ends is suppressed, and the flow surface immediately before filling is linear.

  The position of the semiconductor chip placed in front of the cull outlet is, for example, how far it should be from the cull outlet, how fast the resin injection speed is, and what is the ratio of the resin flow rate at the edge to the center It is difficult to quantitatively limit these. However, the resin itself is a fluid having viscosity, and from a macro viewpoint, even if there is a laminated semiconductor chip that becomes an obstacle, any of them tends to become a single fluid surface. At this time, whether or not the resin flow rates at the left and right ends can be suppressed in the first stage greatly affects the shape of the resin flow surface immediately before the end of filling. Therefore, it is extremely important to intentionally arrange a semiconductor chip in the cull outlet, particularly in front of the endmost gate, to suppress the resin flow rate.

  FIG. 17 is a plan view showing a resin flow path in the case of a resin flow surface according to the proposal of the present invention. As shown in FIG. 17, when the resin flow surface becomes linear, the resin hits the back side (the wall on the air vent side opposite to the gate) and is reflected. As a result, the resin is filled under the overhang of the back side laminated semiconductor chip where unfilling is likely to occur under the overhang, or the unfilled peripheral resin is vibrated. This is the reason why the filling property of the resin is remarkably improved by the present invention.

  Next, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a plan view showing a schematic configuration of an MCP (Multi Chip Package) type semiconductor device to which the manufacturing method according to the first embodiment is applied, and FIG. 2 is a sectional view taken along line AA ′ of FIG. It is.

  The semiconductor device 1 to which the first embodiment is applied includes a wiring substrate 10, a first semiconductor chip 20 such as a DRAM memory chip, and a second semiconductor chip 30 such as a DRAM memory chip. The semiconductor device 1 also includes a first wire 50, a second wire 51, a sealing resin 60, and an external terminal 70.

  As shown in FIGS. 1 and 2, the wiring substrate 10 includes an insulating base material 11 made of, for example, glass epoxy and formed in a substantially rectangular plate shape, and a wiring layer ( (Not shown) and an insulating film 12 formed so as to cover the wiring layer.

  A plurality of connection pads 13 are connected to the wiring layer on one side of the wiring board 10. A plurality of lands 14 are connected to the wiring layer on the other surface side of the wiring board 10. As shown in FIG. 1, the plurality of connection pads 13 are arranged in the vicinity of the peripheral edge of one surface of the wiring board 10. The plurality of lands 14 are arranged in a lattice pattern on the other surface of the wiring board 10. The plurality of connection pads 13 and the plurality of lands 14 are connected to each other by a continuous via and a conductive via that penetrates the insulating base material 11. Wires 50 and 51 are connected to the connection pad 13, and an external terminal 70 is mounted on the land 14.

  The insulating film 12 is, for example, a solder resist (SR). The insulating film 12 is formed on the entire surface of the wiring board 10 except for a predetermined region. In other words, the insulating film 12 is partially removed with respect to a predetermined region, and has one or more openings. For example, the SR opening 15 is formed on one surface side of the wiring board 10. The SR opening 15 exposes a region where the plurality of connection pads 13 are formed and a peripheral region thereof. Also on the other surface side of the wiring substrate 10, SR openings (not shown) that expose the plurality of lands 14 are formed.

  As shown in FIG. 1, the first semiconductor chip 20 is formed in a substantially rectangular plate shape, and is mounted on one surface side of the wiring board 10 in a state where the longitudinal direction thereof is along the longitudinal direction in the drawing. . The other surface of the first semiconductor chip 20 is bonded and fixed to a region where the insulating film 12 of the wiring substrate 10 is formed by an adhesive member 80 such as DAF (Die Attached Film).

  The first semiconductor chip 20 has a predetermined circuit (not shown) and a plurality of first electrode pads 21 formed on one side thereof. As shown in FIG. 1, the plurality of first electrode pads 21 are arrayed along each short side of the first semiconductor chip 20. As shown in FIG. 1, the first electrode pad 21 and the connection pad 13 are connected by a first wire 50.

  As shown in FIG. 1, the second semiconductor chip 30 is formed in a substantially rectangular plate shape, and is laminated on one surface of the first semiconductor chip 20 with the longitudinal direction thereof being in the horizontal direction in the drawing. It is installed. As shown in FIG. 1, the second semiconductor chip 30 is arranged so as not to cover the region where the first electrode pad 21 of the first semiconductor chip 20 is formed. Both ends of the second semiconductor chip 30 in the overhang over the first semiconductor chip 20 (that is, protrude). Thus, as shown in FIGS. 1 and 2, the second semiconductor chip 30 is formed on both sides of the stacked region overlapping the first semiconductor chip 20 and the stacked region in the horizontal direction in the drawing. An overhang region overhanging from the chip 20 is formed. The other surface of the second semiconductor chip 30 is bonded and fixed to the first semiconductor chip 20 by an adhesive member 80 such as DAF.

  The second semiconductor chip 30 has a predetermined circuit (not shown) and a second electrode pad 31 formed on one side thereof. The plurality of second electrode pads 31 are arranged along the short sides of the second semiconductor chip 30 (overhang region). The second electrode pads 31 and the connection pads 13 are illustrated in FIGS. As shown in FIG. 2, the second wires 51 are connected.

  The first wire 50 is made of a conductive metal such as Au, for example, and connects the first electrode pad 21 and the connection pad 13. The second wire 51 is also made of a conductive metal such as Au, and connects the second electrode pad 31 and the connection pad 13.

  The sealing resin 60 is made of an insulating resin such as an epoxy resin. As shown in FIG. 2, the first semiconductor chip 20, the second semiconductor chip 30, and the first wire 50 are formed on one side of the wiring substrate 10. And the second wire 51 and one surface of the wiring substrate 10 are covered.

  In the first embodiment, the external terminal 70 is configured as a solder ball and is mounted on the land 14 of the wiring board 10. The specific form of the external terminal 70 may be other than the solder ball.

  Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

  FIG. 3 is a cross-sectional view for explaining the semiconductor device manufacturing method according to the first embodiment in the order of steps, and FIG. 4 is a cross-sectional view for explaining the manufacturing steps subsequent to FIG.

  First, FIG. 3A shows a wiring mother board 10a including a plurality of product forming portions R partitioned by dicing lines L. FIG. These product forming portions R are regions that are later cut individually along the dicing line L to become the wiring substrate 10. In each product forming portion R, an insulating film 12, a connection pad 13, a land 14, and an SR opening 15 are formed.

  Next, as shown in FIG. 3B, the first semiconductor chip 20 and the second semiconductor chip 30 are sequentially stacked on one surface of the wiring board 10 (wiring mother board 10a). The first semiconductor chip 20 is bonded and fixed to one surface of the wiring substrate 10 (wiring mother substrate 10a) by an adhesive member 80 such as DAF provided on the other surface of the first semiconductor chip 20. Similarly, the second semiconductor chip 30 is bonded and fixed to one surface of the first semiconductor chip 20 by an adhesive member 80 such as DAF provided on the other surface of the second semiconductor chip 30.

  Next, as shown in FIG. 3C, the second wire 51 is used to connect the connection pads 13 of the wiring board 10 (wiring mother board 10a) and the second electrode pads 31 of the second semiconductor chip 30. Are electrically connected. Similarly, the connection pads 13 of the wiring board 10 (wiring mother board 10a) and the first electrode pads 21 of the first semiconductor chip 20 are electrically connected using the first wires 50.

  At this time, a wire bonding apparatus (not shown) can be used for the connection using the wires 50 and 51. The connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method. Specifically, the tips of the wires 50 and 51 in which balls are formed by melting are ultrasonically thermocompression bonded onto the electrode pads 21 and 31 so that the wires 50 and 51 draw a predetermined loop shape. The rear end is ultrasonically thermocompression-bonded on the corresponding connection pad 13.

  Next, as shown in FIG. 3 (d), by performing collective molding on the wiring substrate 10 (wiring mother substrate 10a) on which the first semiconductor chip 20, the second semiconductor chip 30 and the silicon substrate 40 are mounted. Then, the sealing resin 60 is formed. As will be described later, a transfer mold apparatus (not shown) including an upper mold (not shown), a lower mold (not shown), and the like is used for the collective molding. Specifically, this collective mold is configured such that the wiring board 10 (wiring mother board 10a) that has undergone the die bonding process and the wire bonding process is placed in a space formed by an upper mold (not shown) and a lower mold (not shown). It is performed by arranging and allowing a thermosetting epoxy resin or the like to flow into the space.

  Next, as shown in FIG. 4A, external terminals 70 are mounted on the lands 14 provided on the other surface side of the wiring board 10 (wiring motherboard 10a). The mounting of the external terminal 70 can be performed using, for example, a suction mechanism (not shown) provided with a plurality of suction holes (not shown) arranged corresponding to the plurality of lands 14. In this case, a plurality of external terminals 70 are sucked and held by a suction mechanism (not shown), a flux is transferred and formed on the held external terminals 70, and are collectively mounted on the land 14. Thereafter, the connection between the external terminal 70 and the land 14 is fixed by reflow processing.

  Next, as shown in FIG. 4B, in a state where a dicing tape (not shown) is attached to and supported by the sealing resin 60, a wiring board 10 (wiring mother board) is used using a dicing blade (not shown). 10a) and the sealing resin 60 are cut along the dicing line L. Thereby, the wiring board 10 (wiring mother board 10a) is separated into pieces for each product forming portion R, and then the separated wiring board 10 and sealing resin 60 are picked up from a dicing tape (not shown). Thus, the semiconductor device 1 as shown in FIGS. 1 and 2 is obtained.

  FIG. 5 is a plan view showing the relationship between the product formation portion of the wiring board used in the manufacturing method according to the first embodiment and the gate in the transfer mold apparatus (mold mold).

  As shown in FIG. 5, the wiring mother board 10a has a plurality of product forming portions R formed therein. Each product forming portion R is a region that becomes a wiring substrate 10 as shown in FIG. 1 by being cut and separated in a substrate dicing process.

  In the first embodiment, among the plurality of product forming portions R formed on the gate side of the wiring mother board 10a, the stacked semiconductor chips mounted on the two product forming portions R arranged at both ends (most ends). However, the product forming portions R are arranged so as to be opposed to substantially the center of the gate (most end gate) 260 located at the extreme end of the corresponding mold.

  In the MAP method, in order to share a mold die, the wiring mother board 10a has a region where a product forming portion can be formed and a gate position at the time of resin molding. In the first embodiment, for example, one product forming portion By adjusting the size of the side perpendicular to the gate, the center of the semiconductor chip mounted on the two product forming portions arranged at both ends is positioned at the extreme end of the corresponding mold die. It is configured to be located substantially at the center of 260.

  FIG. 6 is a cross-sectional view illustrating the molding process in the manufacturing method according to the first embodiment in the order of processes, and FIG. 7 is a plan view illustrating the molding process.

  As shown in FIG. 6A, the transfer mold apparatus 100 has a mold mold composed of an upper mold 200 and a lower mold 300. A cavity 250 is formed in the upper mold 200, and a recess 350 for mounting the wiring mother board 10a is formed in the lower mold 300.

  The wiring mother board 10a after completion of the wire bonding is set in the recess 350 of the lower mold 300 as shown in FIG. Then, by closing the wiring mother board 10a with the upper mold 200 and the lower mold 300, a cavity and a gate portion 260 having a predetermined size are formed above the wiring mother board 10a. The plurality of product forming portions R of the wiring mother board 10 a are collectively covered with the cavities 250 of the upper mold 200.

  In the first embodiment, the product forming portions R arranged at both ends on the gate side are formed corresponding to the gate 260 located at the extreme end of the mold as described above. When the mold is closed, the centers of the stacked semiconductor chips mounted on the two product forming portions R arranged at both ends are positioned approximately at the centers of the gates 260 positioned at the extreme ends of the corresponding mold dies. Set to do. Then, the resin tablet 360 is supplied to the pot of the lower mold 300 of the mold, and the resin tablet 360 is heated and melted.

  Then, as shown in FIG. 6C, the molten resin is injected into the cavity 250 from the gate portion 260 by the plunger 370. In the first embodiment, since the laminated semiconductor chip is arranged at the injection position of the gate 260 located at the end of the mold, the injection is performed from the gate 260 located at the end. The molten resin flow is dispersed by the laminated semiconductor chip. Due to this dispersion, as shown in FIG. 7, the flow rate of the resin flowing outside the product formation region and the flow rate of the resin flowing in the product formation region can be substantially equalized. As a result, it is possible to improve the resin filling property in the gap under the overhang of the semiconductor chip arranged in the upper stage in the product forming portion on the side of the air vent 270 opposite to the gate 260, and to the gap under the overhang. Generation of voids can be reduced. Furthermore, by reducing the occurrence of voids in the gap under the overhang, the occurrence of package cracks during reflow can be reduced, and the reliability of the semiconductor device can be improved.

  Then, after the resin is filled into the cavity 250, the resin is cured at a predetermined temperature, for example, 180 ° C., and a sealing body is formed (FIG. 8). Thereafter, the wiring mother board 10a is taken out from the mold, and the sealing body is completely cured by baking at a predetermined temperature, for example, 180 ° C., and a plurality of product forming portions as shown in FIG. A sealing resin layer 60 is formed so as to cover all of the above. Moreover, the sealing resin of the gate part, the runner part, and the cull part connected to the sealing resin is removed.

  FIG. 9 is a plan view showing the positional relationship between the product formation region of the wiring board used in the manufacturing method according to the second embodiment of the present invention and the gate of the mold die.

  In the second embodiment, the product forming portions arranged at both ends on the gate 260 side are different from the first embodiment, and the product forming portions are arranged inside the gate 260 located at the extreme end of the mold. Has been. In the second embodiment, as shown in FIG. 9, a flow suppressing member, for example, a dummy chip 400 is disposed in a product formation region (mold region) outside the product formation portion R disposed at both ends. As the dummy chip 400, for example, a silicon substrate on which no circuit is formed or a defective semiconductor chip is used.

  In the second embodiment, the stacked semiconductor chips of the product forming portion R arranged at both ends on the gate 260 side are not arranged corresponding to the corresponding endmost gate 260. However, by arranging the dummy chip 400 as a flow suppressing member outside the product forming portion R, the flow of the sealing resin injected from the outermost gate 260 is dispersed, and as in the first embodiment, It is possible to equalize the flow rate of the sealing resin flowing outside the product formation region and the flow rate of the sealing resin flowing inside the product formation region. Thereby, the same effect as the first embodiment can be obtained. Since the flow suppressing member is disposed in the empty area on the wiring mother board 10a, it can be handled without impairing the sharing of the mold.

  In the second embodiment, the flow suppressing member is provided outside the product forming portion of the wiring board so as to disperse the flow of the sealing resin injected from the outermost gate into the cavity. The flow of the sealing resin injected from the innermost gate, forming a convex portion on the inner surface of the cavity of the mold and corresponding to the outside of the product forming portion of the wiring board accommodated in the cavity May be configured to be distributed.

  FIG. 10 is a plan view showing the positional relationship between the product forming portion of the wiring board used in the manufacturing method according to the third embodiment of the present invention and the gate in the mold.

  In the third embodiment, the product forming portions R arranged at both ends on the gate 260 side are configured to be arranged inside the gate 260 located at the outermost end of the mold as in the second embodiment. Has been. In the third embodiment, as shown in FIG. 10, a protrusion 400 'formed on the resin flow suppressing member, for example, the wiring mother board 10a, is arranged in front of the gate 260 located at the end. As the convex portion 400 ′, a convex portion or a bump formed on the insulating film (12 in FIG. 2) on the wiring motherboard 10 a is used.

  Also in the third embodiment, the stacked semiconductor chips of the product forming portion R arranged at both ends on the gate 260 side are not arranged corresponding to the corresponding endmost gate 260. However, the flow of the sealing resin injected from the outermost gate 260 is dispersed by disposing the convex portion 400 ′ as the flow suppressing member at the injection position of the outermost gate 260, which is the same as in the first embodiment. Similarly, the flow rate of the sealing resin flowing outside the product formation region and the flow rate of the sealing resin flowing inside the product formation region can be equalized. Thereby, the same effect as the first embodiment can be obtained. Also in the third embodiment, since the flow suppressing member is arranged in an empty area on the wiring mother board, it can be handled without impairing the common use of the mold.

  In the third embodiment, the convex portion is formed at the injection position of the outermost gate into the cavity, and the flow of the sealing resin injected from the outermost gate into the cavity is dispersed. Alternatively, the shortest gate width may be configured to be narrower than the widths of the other gates to disperse the flow of the sealing resin.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on several embodiment, this invention is not limited to the said embodiment, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary. . For example, in the above-described embodiment, the case where the present invention is applied to a semiconductor device in which two semiconductor chips are cross-stacked has been described. However, in the case of a semiconductor device in which a plurality of semiconductor chips are stacked so as to overhang, such a stacked structure You may apply to the semiconductor device of this. Further, the present invention may be applied to a semiconductor device in which one semiconductor chip or three or more semiconductor chips are stacked. Furthermore, the present invention may be applied to any combination of semiconductor chips such as a memory chip and a logic chip.

DESCRIPTION OF SYMBOLS 10 Wiring board 11 Insulation base material 12 Insulating film 13 Connection pad 14 Land 15 SR opening 20, 30 1st, 2nd semiconductor chip 21, 31 Electrode pad 50, 51 Wire

Claims (7)

Preparing a wiring board on which a plurality of product forming portions are arranged;
Mounting a semiconductor chip on each of the plurality of product forming portions of the wiring board;
A step of mounting the wiring board on a mold die having a cavity that collectively covers the plurality of product forming portions, and a plurality of gates that are connected to the cavity;
Filling the cavity with the sealing resin from the plurality of gates, and forming a sealing resin layer that collectively covers the plurality of product forming portions of the wiring board,
When filling the sealing resin, the sealing resin is injected from the plurality of gates into the cavity so that the flow of the sealing resin filled from the gate located at the end of the plurality of gates is dispersed. A method of manufacturing a semiconductor device, comprising filling.   2. The semiconductor according to claim 1, wherein the step of mounting the semiconductor chip includes a step of stacking a plurality of semiconductor chips so that a gap is formed between at least one semiconductor chip and the wiring board. Device manufacturing method.   3. The semiconductor according to claim 2, wherein the step of laminating so as to form a gap includes a step of laminating at least one semiconductor chip so that a part thereof overhangs from a lower semiconductor chip. Device manufacturing method.   The semiconductor chip mounted on the product forming part located at the end is arranged in the filling direction of the sealing resin of the gate located at the end, and the sealing is filled from the gate located at the end by the semiconductor chip The method of manufacturing a semiconductor device according to claim 1, wherein the flow of the resin is dispersed.   The step of preparing the wiring board includes a step of forming a member that suppresses the flow of the sealing resin in the mold region outside the product forming portion located at the outermost end of the wiring board when the sealing resin is filled. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method.   The step of preparing the wiring board includes the step of forming a member that suppresses the flow of the sealing resin when filling the sealing resin at a position corresponding to the resin outlet of the gate located at the extreme end of the wiring board. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the method is included.   Among the plurality of gates, the width of the sealing resin filled from the gate located at the extreme end is dispersed by configuring the width of the gate located at the extreme end to be narrower than the width of the other gates. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device.

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