JP5205173B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent wire short-circuitting with a semiconductor chip in a semiconductor device. <P>SOLUTION: A second semiconductor chip 2 is mounted on a first semiconductor chip 1 such that a distance between an end of the upper stage second semiconductor chip 2 and an end of the lower stage first semiconductor chip 1 is longer than that between the end of the first semiconductor chip 1 and a bonding lead 7c of a wiring board 7. Further, by permitting a plurality of second wires 3b connected with the second semiconductor chip 2 to be formed by a reverse bonding system, a second wire 3b can steeply rise outside the first semiconductor chip 1 for connection, so that there can be provided clearance greatly between the end of the first semiconductor chip 1 and the second wire 3b, preventing the lower stage side first semiconductor chip 1 and the second wire 3b from being short-circuitted. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a multichip module having a plurality of stacked semiconductor chips.

In a chip stacked type semiconductor device, a bonding pad connected to a bonding lead corresponding to an address terminal of a package substrate and a bonding pad connected to a bonding lead corresponding to a data terminal are on two of the four sides. There is a technique of stacking semiconductor chips and memory chips that are arranged in a distributed manner (see, for example, Patent Document 1).
JP 2004-71838 A

  In recent years, with the high integration of semiconductor devices, a plurality of semiconductor chips tend to be mixedly mounted on one semiconductor device (package). In addition, there is a demand for miniaturization of semiconductor devices, and in order to meet this demand, as shown in Patent Document 1, it is effective to stack a plurality of semiconductor chips on a substrate (wiring board). .

  The inventor of the present application has studied a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate and the pads of the semiconductor chip and the electrodes of the substrate are electrically connected via a plurality of wires.

  Then, when further miniaturization progressed in the chip stacked type semiconductor device, a problem was found in which the wire connected to the pad of the upper semiconductor chip contacts the end of the lower semiconductor chip. As a result of examination of this problem by the present inventors, the following has been found.

  First, as the semiconductor device becomes smaller, the outer dimensions of the substrate become smaller.

  This shortens the distance between the end of the lower semiconductor chip and the bonding lead formed on the peripheral edge of the surface of the substrate.

  On the other hand, with the increase in functionality of semiconductor chips, the external dimensions of the semiconductor chips tend to shrink. Therefore, an extreme difference has arisen in the external dimension of each of a plurality of semiconductor chips.

  The semiconductor chip investigated by the present inventors is a case where the outer dimension of the upper semiconductor chip is smaller than the outer dimension of the lower semiconductor chip. In this state, a so-called positive bonding method is applied in which one end of the wire is formed on the pad of the upper semiconductor chip, and then the other end of the wire is connected to the bonding lead of the substrate corresponding to the pad. In this case, as shown in the semiconductor device 15 of the comparative example in FIG. 36, it was found that a part of the wire 3 was in contact with the end portion (corner portion) of the semiconductor chip 13 on the lower stage side.

  In Patent Document 1, there is no description about a specific countermeasure for a problem (problem in which a wire comes into contact with a chip) that occurs when the outer dimensions of a semiconductor device are shrunk.

  An object of the present invention is to provide a technique capable of preventing a wire short circuit with a semiconductor chip in a semiconductor device.

  Another object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

  Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a substrate on which a plurality of bonding leads are formed, a first semiconductor chip mounted on the surface of the substrate so as to be positioned inside the plurality of bonding leads of the substrate, and a plurality of first semiconductor chips. And a second semiconductor chip mounted on the first semiconductor chip so as to be located inside the first pad. Further, the present invention provides a plurality of first connection means for electrically connecting a plurality of first pads of the first semiconductor chip and a plurality of bonding leads of the substrate, and a plurality of second pads and the substrate of the second semiconductor chip. A plurality of second connection means for electrically connecting the plurality of bonding leads, a first semiconductor chip, a second semiconductor chip, a sealing body for sealing the plurality of first connection means and the second connection means, And a plurality of external terminals provided on the back surface of the substrate. Furthermore, the present invention provides the second semiconductor so that the distance between the end of the second semiconductor chip and the end of the first semiconductor chip is longer than the distance between the end of the first semiconductor chip and the bonding lead of the substrate. The chip is mounted on the first main surface of the first semiconductor chip, the second connection means is a wire, and the angle formed between the wire and the surface of the substrate on the second bonding lead is determined by the second pad of the second semiconductor chip. This is larger than the angle formed by the upper wire and the second main surface of the second semiconductor chip.

  The present invention also provides: (a) a step of preparing a substrate on which a plurality of bonding leads are formed; (b) a first semiconductor chip on which a plurality of first pads are formed inside the plurality of bonding leads on the substrate. (C) mounting a second semiconductor chip having a second main surface smaller than the outer dimension of the first semiconductor chip inside the plurality of first pads of the first semiconductor chip; And mounting on the first semiconductor chip so as to be positioned at the position. Further, according to the present invention, (d) a step of electrically connecting a plurality of first pads of the first semiconductor chip and a plurality of bonding leads of the substrate through a plurality of first connection means, respectively; Electrically connecting a plurality of second pads of the semiconductor chip and a plurality of bonding leads of the substrate via a plurality of second connection means, respectively. Furthermore, the present invention includes (f) a step of sealing the first semiconductor chip, the second semiconductor chip, the plurality of first connection means and the plurality of second connection means with resin; (g) a plurality of external parts on the back surface of the substrate. Forming a terminal, wherein the distance between the end of the second semiconductor chip and the end of the first semiconductor chip is greater than the distance between the end of the first semiconductor chip and the bonding lead of the substrate. Is mounted on the first main surface of the first semiconductor chip so as to be longer. Further, in the present invention, the second connecting means is a wire, and in the step (e), after connecting one end of the wire to the bonding lead of the substrate, the other end on the side opposite to the one end of the wire is connected to the second connecting means. 2 Connected to the second pad of the semiconductor chip.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The second semiconductor so that the distance between the end of the second semiconductor chip on the upper stage side and the end of the first semiconductor chip on the lower stage side is longer than the distance between the end of the first semiconductor chip and the bonding lead of the substrate. Since the chip is mounted on the first semiconductor chip and the plurality of second wires connected to the second semiconductor chip are formed by the reverse bonding method, the end of the first semiconductor chip on the lower stage side and the second wire A large clearance can be provided between the two. Thereby, a short circuit between the lower semiconductor chip and the wire can be prevented.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a plan view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention through a sealing body, and FIG. 2 is a cross section showing an example of the structure cut along the line AA in FIG. 3 is a cross-sectional view showing an example of a structure cut along the line BB in FIG.

  The semiconductor device according to the first embodiment shown in FIGS. 1 to 3 is a semiconductor package in which a plurality of semiconductor chips are stacked (stacked) on a wiring substrate 7 that is a substrate having wiring. In Embodiment 1, a multi-chip module 8 in which two semiconductor chips are stacked on a wiring board 7 will be described as an example of the semiconductor device.

  In the multichip module 8, one of the stacked semiconductor chips is, for example, an RF-IC (Integrated Circuit), and the other semiconductor chip is a Secure IC. In this case, a signal for controlling each semiconductor chip is transmitted from an external device electrically connected to the multichip module 8.

  The detailed configuration of the multichip module 8 will be described. The wiring board 7 has a front surface (main surface, chip mounting surface) 7a and a back surface 7b opposite to the front surface 7a. Each planar shape of the front surface 7a and the back surface 7b is composed of a quadrangle having a pair of sides (first side) and a pair of sides (second side) intersecting the side (first side), and each side of the surface 7a. A plurality of bonding leads (electrodes) 7c are formed along (periphery). The plurality of bonding leads 7c include a first bonding lead electrically connected to one of the stacked semiconductor chips (lower semiconductor chip 1), and the other semiconductor chip (upper semiconductor chip 2). And a second bonding lead electrically connected.

  Further, the first semiconductor chip 1 is mounted face-up on the surface 7 a of the wiring board 7 with an adhesive 6 so as to be positioned inside the plurality of bonding leads 7 c of the wiring board 7. The adhesive 6 is a film adhesive. In addition, the face-up mounting means that the semiconductor chip is mounted on the wiring substrate 7 so that the back surface (first back surface 1b) of the semiconductor chip (first semiconductor chip 1) faces the front surface 7a of the wiring substrate 7. is there.

  As shown in FIG. 1, the planar shape of the first semiconductor chip 1 which is the lower chip (first chip) is a pair of sides (fifth side) and a pair of sides intersecting with this side (fifth side). The fifth side is aligned with the first side of the wiring substrate 7, and the sixth side is aligned with the second side of the wiring substrate 7. A plurality of first pads (first electrode pads) 1c are formed on the rectangular first main surface 1a only along each of a pair of sides (sixth sides). Further, in the multichip module 8 of the first embodiment, the first pad 1c is not formed on the pair of sides (fifth sides) intersecting with this side (sixth side).

  A second semiconductor chip 2 is laminated on the first semiconductor chip 1 with an adhesive 6 interposed therebetween. The adhesive 6 is a film adhesive. In addition, the first main surface 1a of the first semiconductor chip 1 has a second main surface 2a having a second main surface 2a smaller than the outer dimensions of the first semiconductor chip 1 so as to be positioned inside the plurality of first pads 1c. 2 The semiconductor chip 2 is mounted face up via an adhesive 6. That is, the back surface (second back surface 2b) of the upper semiconductor chip (second semiconductor chip 2) is opposed to the main surface (first main surface 1a) of the lower semiconductor chip (first semiconductor chip 1). It is mounted on the lower semiconductor chip.

  The planar shape of the second semiconductor chip 2 that is the upper chip (second chip) is a pair of sides (third side) and a pair of sides (fourth side) intersecting with this side (third side). The third side is aligned with the first side of the wiring substrate 7, and the fourth side is aligned with the second side of the wiring substrate 7. A plurality of second pads (second electrode pads) 2c are formed on the peripheral edge portion along each side (third side and fourth side) on the quadratic second main surface 2a.

  A plurality of first pads 1c of the first semiconductor chip 1 and a plurality of bonding leads (first bonding leads) 7c of the wiring board 7 corresponding thereto are respectively connected by a plurality of first connecting means (first wires) 3a. The plurality of second pads 2c of the second semiconductor chip 2 and the plurality of bonding leads (second bonding leads) 7c of the wiring board 7 corresponding to the second pads 2c of the second semiconductor chip 2 are respectively connected to the plurality of second connection means. (Second wire) 3b is electrically connected. Each of the first and second connection means in the first embodiment is a wire, and is made of, for example, gold (Au).

  2 and 3, the first semiconductor chip 1, the second semiconductor chip 2, the plurality of first connection means 3a, and the plurality of second connection means 3b are sealed on the surface 7a of the wiring board 7. A sealing body 4 to be stopped is formed. The sealing body 4 is made of a mold resin (resin) 10 shown in FIG. As shown in FIG. 2, gold bumps 3c are formed on the first pad 1c and the second pad 2c. This is a ball-shaped gold bump 3c formed by discharging one end of the wire in the wire bonding step, and improves the connectivity between the wire and the pads (first pad 1c, second pad 2c). Because. Further, as shown in FIG. 3, when the reverse bonding method described later is applied, the gold bumps 3c are formed not only on the bonding leads 7c of the wiring board 7 but also on the pads of the semiconductor chip. The reason for this will be explained later.

  On the back surface 7 b of the wiring substrate 7, solder balls 5 that are a plurality of external terminals of the multichip module 8 are arranged in a grid pattern.

  As shown in FIG. 1, in the multichip module 8 of the first embodiment, the second semiconductor chip 2 includes the end portion (end surface, side surface) of the second semiconductor chip 2 and the end portion of the first semiconductor chip 1 ( The distances (L1, L2) to the end surfaces and the side surfaces are longer than the distances (M1, M2) between the end portions (end surfaces, side surfaces) of the first semiconductor chip 1 and the end portions of the bonding leads 7c of the wiring board 7. Thus, it is mounted on the first main surface 1a of the first semiconductor chip 1 (L1> M1, L2> M2). In this embodiment, the distance of L1 is about 0.5 mm, the distance of L2 is about 0.6 mm, the distance of M1 is about 0.1 mm, and the distance of M2 is about 0.3 mm, and each of L1 and L2 Is longer than the distance between M1 and M2. As shown in FIG. 1, the planar shape of the semiconductor chip 1 of the lower chip (first chip) is a rectangle. Therefore, the distance (M1) between the fifth side of the first semiconductor chip 1 and the end of the bonding lead 7c formed along the first side of the wiring substrate 7 is the sixth side of the first semiconductor chip 1 and the wiring. It is shorter than the distance (M2) from the end of the bonding lead 7c formed along the second side of the substrate 7.

  That is, the multi-chip module 8 has a smaller external dimension of the wiring board 7 due to its miniaturization, and as a result, the bonding between the end of the lower first semiconductor chip 1 and the wiring board 7 arranged outside thereof. The distance from the lead 7c is set short, and the outer dimension of the second semiconductor chip 2 on the upper stage side is smaller than the outer dimension of the first semiconductor chip 1 on the lower stage side.

  In the multichip module 8 having such a structure, a plurality of second connection means for electrically connecting the plurality of second pads 2c of the second semiconductor chip 2 and the plurality of bonding leads 7c of the wiring board 7 corresponding thereto. (Wire) 3b is partially formed by the reverse bonding method. Here, the reverse bonding method is to connect one end of the wire to the bonding lead of the wiring board and then connect the other end of the wire opposite to the one end of the wire to the pad of the semiconductor chip.

  That is, in the wire bonding process of assembling the multichip module 8, when the plurality of second pads 2c of the second semiconductor chip 2 on the upper stage side and the plurality of bonding leads 7c of the wiring substrate 7 corresponding thereto are wire bonded. First, one end of the second wire 3b is connected to the bonding lead 7c of the wiring board 7, and then the other end opposite to the one end of the second wire 3b is connected to the second pad 2c of the second semiconductor chip 2. To connect to. At this time, bumps 3c made of gold (Au) are formed on the pads (second pads 2c) of the semiconductor chip (second semiconductor chip 2). Thereby, the connectivity between the wire and the pad can be improved. Moreover, it can suppress that a part of wire contacts the main surface of a semiconductor chip.

  Here, with reference to FIG. 28 and FIG. 29, the characteristics of each wire shape when the normal bonding is performed and when the reverse bonding is performed will be described. FIG. 28 shows an example of the shape of the wire 3 after normal bonding, while FIG. 29 shows an example of the shape of the wire 3 after reverse bonding.

  As shown in FIG. 28, in the positive bonding, the 1st side is the pad 13 b of the semiconductor chip 13, and the 2nd side is the bonding lead 7 c of the wiring substrate 7. At that time, first, one end portion of the wire 3 is connected to the pad 13b of the semiconductor chip 13, and after the connection, the wire 3 is pulled up almost directly, the wire 3 is pulled out substantially horizontally at a predetermined height, and then the 2nd side is set. The wire 3 is slanted down toward the bonding lead 7c of the wiring substrate 7 to connect the other end of the wire 3 to the bonding lead 7c. Therefore, in the positive bonding, the angle (θ1) formed between the wire 3 on the pad 13b of the semiconductor chip 13 and the main surface 13a of the semiconductor chip 13 is substantially a right angle, and the wire 3 on the bonding lead 7c of the wiring substrate 7 It becomes larger than the angle (θ2) formed with the surface 7a of the wiring board 7 (θ1> θ2).

  On the other hand, in the reverse bonding shown in FIG. 29, the 1st side is the bonding lead 7 c of the wiring substrate 7, and the 2nd side is the pad 13 b of the semiconductor chip 13. At that time, first, one end of the wire 3 is connected to the bonding lead 7c of the wiring board 7, and after the connection, the wire 3 is pulled up almost directly, the wire 3 is pulled out substantially horizontally at a predetermined height, and then the 2nd side As described above, the wire 3 is drawn out toward the pad 13b of the semiconductor chip 13 and the other end of the wire 3 is connected to the gold bump 3c on the pad 13b. Therefore, in reverse bonding, the angle (θ4) formed between the wire 3 and the surface 7a of the wiring board 7 on the bonding lead 7c of the wiring board 7 is substantially a right angle (steep angle), and is on the pad 13b of the semiconductor chip 13. Is larger than an angle (θ3) formed by the wire 3 and the main surface 13a of the semiconductor chip 13 (θ4> θ3).

  In other words, on the 1st side of each of the normal bonding (FIG. 28) and the reverse bonding (FIG. 29), the distance from the 1st bond point to the bending point 3d of the nearest wire 3 is reverse to that of the normal bonding. Bonding is longer.

  As described above, in the multichip module 8 according to the first embodiment, as shown in FIG. 3, by adopting reverse bonding in which the wire 3 is pulled up substantially straight (steeply) from the bonding lead 7c of the wiring board 7, the lower stage Even in a structure in which the distance between the end portion of the first semiconductor chip 1 on the side and the bonding lead 7c of the wiring substrate 7 arranged outside the first semiconductor chip 1 is set to be short, wire bonding can be performed.

  That is, as shown in FIGS. 1 and 3 of the first embodiment, the distance (L1, L2) between the end of the second semiconductor chip 2 (upper stage) and the end of the first semiconductor chip 1 (lower stage) is as follows. In a structure longer than the distance (M1, M2) between the end portion of the first semiconductor chip 1 and the bonding lead 7c of the wiring substrate 7, the pad (second pad 2c) of the upper semiconductor chip (second semiconductor chip 2). It is preferable to form a wire that electrically connects the bonding lead (second bonding lead) 7c of the wiring board 7 with a reverse bonding method.

  As a result, a large clearance can be provided between the end of the first semiconductor chip 1 on the lower stage side and the second wire 3b, and a short circuit between the first semiconductor chip 1 on the lower stage side and the wire 3 can be prevented. .

  In addition, the second wire 3b is reverse-bonded to the bonding lead 7c of the wiring board 7, so that the upper second semiconductor chip is formed even if the gap between the lower first semiconductor chip 1 and the end of the wiring board 7 is narrow. 2 and the bonding lead 7c can be connected by the second wire 3b. Therefore, the wiring board 7 can be reduced in size. As a result, the multichip module 8 can be reduced in size.

  In the multichip module 8 of the first embodiment, as shown in FIGS. 1 to 3, a plurality of second chips connecting the second pads 2 c of the second semiconductor chip 2 and the bonding leads 7 c of the wiring substrate 7. Both reverse bonding and normal bonding are applied to the wire 3b.

  That is, in the plurality of second wires 3b, the angle formed between the second wire 3b and the surface 7a of the wiring board 7 on the bonding lead 7c of each of the plurality of second wires 3b is the second of each of the plurality of second wires 3b. A wire (second reverse bonding wire) larger than the angle formed between the second wire 3b on the second pad 2c of the semiconductor chip 2 and the second main surface 2a of the second semiconductor chip 2, and each of the plurality of second wires 3b The angle formed between the second wire 3b on the bonding lead 7c and the surface 7a of the wiring board 7 is such that the second wire 3b and the second semiconductor on the second pad 2c of the second semiconductor chip 2 of each of the plurality of second wires 3b. A wire (second positive bonding wire) 3 smaller than an angle formed with the second main surface 2a of the chip 2 is included.

  On the other hand, the bonding leads (first bonding lead, second bonding lead) formed on the surface 7a of the wiring board 7 are formed along each side (first side, second side). Bonding leads connected to the wires (first reverse bonding wire and second reverse bonding wire) formed by the step (1) are formed along the first side of the wiring substrate 7 and are formed by the positive bonding method (first first bonding wire). Bonding leads connected to the bonding wires and second positive bonding wires are formed along the second side of the wiring board 7.

  That is, in the multichip module 8 of the first embodiment, reverse bonding or normal bonding is selectively used corresponding to a pair of two sides facing each other. For example, in the multichip module 8 shown in FIG. 1, reverse bonding is applied to two opposite sides (first sides) in the vertical direction (direction of the BB cross section) as shown in FIG. As shown in FIG. 2, positive bonding is applied to two opposite sides (second sides) in the left-right direction (direction of the AA cross section).

  As described above, this is because the distance between the end of the second semiconductor chip 2 and the end of the first semiconductor chip 1 is the distance between the end of the first semiconductor chip 1 and the end of the bonding lead 7c of the wiring substrate 7. When the distance is larger than the distance, it is preferable to apply the reverse bonding method. However, the wires formed by the reverse bonding method (first reverse bonding wire and second reverse bonding wire) are wires formed by the normal bonding method. The strength is lower than (first positive bonding wire, second positive bonding wire). Therefore, in the subsequent process of forming the sealing body, the wire formed by the reverse bonding method is likely to flow due to the filling pressure of the resin.

  Therefore, in the present embodiment, all the wires connected to the second pads 2c of the second semiconductor chip 2 are formed along the fourth side of the second semiconductor chip 2 without being formed by the reverse bonding method. The bonding lead (second bonding lead) 7c formed along the second side of the second pad 2c and the wiring board 7 is electrically connected through a wire formed by a positive bonding method.

  This is because the lower semiconductor chip (first semiconductor chip 1) has a rectangular planar shape, so that the long side end (sixth side) of the first semiconductor chip 1 and the second side of the wiring substrate 7 The distance (M2) between the end of the bonding lead formed along the first side of the first side of the first semiconductor chip 1 and the first side of the wiring board 7 is equal to the distance (M2). This is because the contact between the first semiconductor chip 1 and the wire (second positive bonding wire) hardly occurs even when the positive bonding method is applied, which is larger than the distance (M1) from the end of the lead.

  In the plurality of first wires 3a that connect the first pads 1c of the lower first semiconductor chip 1 and the bonding leads 7c of the wiring substrate 7, the first wires on the bonding leads 7c of the plurality of first wires 3a respectively. The angle formed by 3a and the surface 7a of the wiring board 7 is such that the first wire 3a on the first pad 1c of the first semiconductor chip 1 of each of the plurality of first wires 3a and the first main surface 1a of the first semiconductor chip 1 It is smaller than the angle formed by.

  That is, in the present embodiment, the plurality of first wires 3a are all wire bonded by positive bonding. At that time, since positive bonding is performed, the first wire 3a is formed only on the side of the wiring substrate 7 having the longer distance (M2) between the end of the first semiconductor chip 1 and the bonding lead 7c. That is, positive bonding is performed by the first wire 3a as shown in FIG. 2 only on the two opposite sides in the left-right direction (direction of the AA cross section) of the structure shown in FIG.

  As a result, the plurality of first wires 3a formed in the multichip module 8 of the first embodiment are all connected using positive bonding.

  In the multichip module 8, the thickness of the second semiconductor chip 2 is larger than the thickness of the first semiconductor chip 1 as shown in FIGS. 2 and 3. That is, the upper second semiconductor chip 2 is thicker than the lower first semiconductor chip 1. For example, the thickness of the second semiconductor chip 2 is 140 μm, while the thickness of the first semiconductor chip 1 is 90 μm.

  By mounting the second semiconductor chip 2 thicker in the upper stage than in the lower stage in this way, a wire short on the side where the positive bonding is performed (a wire short between the second wire 3b and the lower first semiconductor chip 1) is performed. Occurrence can be prevented. That is, a predetermined clearance is secured between the second wire 3b and the lower first semiconductor chip 1 on the side where the normal bonding is performed, compared to the side where the reverse bonding is performed. Since it is difficult to secure a large clearance due to the downsizing of the multichip module 8 and chip shrink, the second wire 3b is lowered from the high position by increasing the thickness of the second semiconductor chip 2 in the upper stage, and the second wire A clearance between 3b and the lower first semiconductor chip 1 is secured.

  In the sense that the second wire 3b is lowered from a higher position, it is possible to increase the rising portion of the second wire 3b without increasing the thickness of the second semiconductor chip 2 in the upper stage. If the rising portion of the wire 3b is increased, it is likely to be affected by the wire flow during resin molding, so it is not preferable to increase the rising portion of the second wire 3b. Therefore, in the multichip module 8 according to the first embodiment, the thickness of the upper second semiconductor chip 2 is made larger than the thickness of the lower first semiconductor chip 1.

  In the multichip module 8, the plurality of bonding leads 7c arranged along the peripheral edge of each side of the rectangular surface 7a of the wiring board 7 are arranged in a line. This is because the distance between the end of the first semiconductor chip 1 at the lower stage and the end of the wiring substrate 7 is short, so that it is difficult to arrange the bonding leads 7c in a plurality of rows. Leads 7c are arranged in a line.

  In the multichip module 8, the first semiconductor chip 1 and the second semiconductor chip 2 are die-bonded with an adhesive 6. That is, the adhesive 6 is used as a die bond material for the first semiconductor chip 1 and the second semiconductor chip 2. This is because, in particular, the end portion of the lower first semiconductor chip 1 and the bonding lead 7c are arranged close to each other, so that the paste material that protrudes from the first semiconductor chip 1 when the paste material is used as the die bond material. Therefore, by using the adhesive 6 as the die bond material, it is possible to prevent adhesion of the die bond material to the bonding leads 7c.

  This also has the same effect on the adhesion of the die bond material to the first pad 1c of the first semiconductor chip 1 due to the flow of the die bond material from the second semiconductor chip 2 in the upper stage.

  Next, the assembly procedure of the semiconductor device (multi-chip module 8) of the first embodiment will be described with reference to the process flow diagram shown in FIG. 4 is a process flow diagram showing an example of a method of manufacturing the semiconductor device of FIG. 1, FIG. 5 is a plan view showing an example of the structure of a wiring board incorporated in the semiconductor device of FIG. 1, and FIG. FIG. 7 is a cross-sectional view showing an example of a structure cut along a line BB in FIG. 5. 8 is a plan view showing an example of the die bonding state of the lower chip in the first die bond of the manufacturing method shown in FIG. 4, and FIG. 9 is a cross section showing an example of the structure cut along the line AA in FIG. 10 and 10 are cross-sectional views showing an example of the structure cut along the line BB in FIG. 11 is a plan view showing an example of the die bonding state of the upper chip in the second die bond of the manufacturing method shown in FIG. 4, and FIG. 12 is a cross section showing an example of the structure cut along the line AA in FIG. 13 and 13 are cross-sectional views showing an example of the structure cut along the line BB in FIG. 14 is a plan view showing an example of the wire bonding state of the lower chip in the first wire bond of the manufacturing method shown in FIG. 4, and FIG. 15 shows an example of the structure cut along the line AA in FIG. FIG. 16 is a sectional view showing an example of a structure cut along the line BB in FIG. 17 is a plan view showing an example of the wire bonding state of positive bonding of the upper chip in the second wire bond of the manufacturing method shown in FIG. 4, and FIG. 18 is a structure cut along the line AA in FIG. FIG. 19 is a cross-sectional view showing an example of a structure cut along the line BB in FIG. 20 is a plan view showing an example of the wire bonding state of reverse bonding of the upper chip in the second wire bond of the manufacturing method shown in FIG. 4, and FIG. 21 is a structure cut along the line AA in FIG. FIG. 22 is a cross-sectional view showing an example of a structure cut along the line BB in FIG. 20. 23 is a cross-sectional view showing an example of the structure after resin sealing in the manufacturing method shown in FIG. 4, FIG. 24 is a cross-sectional view showing an example of the structure after ball attachment in the manufacturing method shown in FIG. 4 is a sectional view showing an example of the structure after cutting the substrate in the manufacturing method shown in FIG. 4, FIG. 26 is a partial sectional view showing an example of the resin filling direction in the resin sealing step of the manufacturing method shown in FIG. 4, and FIG. It is a fragmentary top view which shows an example of the resin filling direction.

  First, a back grind is applied to a semiconductor wafer (not shown) to thin the semiconductor wafer, and then an adhesive 6 as a die bond material is attached to the back surface of the wafer. Thereafter, the semiconductor wafer is diced to obtain individual chips.

  Thereafter, substrate preparation shown in step S1 of FIG. 4 is performed. Here, the wiring board 7 shown in FIGS. 5, 6 and 7 is prepared. That is, a wiring substrate 7 having a front surface 7a having a plurality of bonding leads 7c formed on the peripheral edge and a back surface 7b opposite to the front surface 7a is prepared. The plurality of bonding leads 7c are formed in a line along each side at the peripheral portion of the quadrangular surface 7a. Accordingly, a substantially quadrangular shape is formed by the row of bonding leads 7c on each side. The surface 7a of the wiring board 7 is covered with a solder resist film 7d, which is an insulating film, but each bonding lead 7c is exposed to the opening 7e of the solder resist film 7d.

  Then, the 1st die bond shown in Step S2 is performed. That is, as shown in FIGS. 8, 9, and 10, die bonding of the lower first semiconductor chip 1 is performed. Here, the first semiconductor chip 1 having the first main surface 1a on which the plurality of first pads 1c are formed is positioned inside the plurality of bonding leads 7c arranged in a substantially square shape of the wiring board 7. Mounted on the surface 7 a of the wiring substrate 7. At this time, as shown in FIG. 9, an adhesive 6 is applied in advance to the back surface 1 b of the first semiconductor chip 1. After the first semiconductor chip 1 is disposed on the front surface 7 a of the wiring substrate 7, thermocompression bonding is performed. Thus, the back surface 1b of the first semiconductor chip 1 and the front surface 7a of the wiring substrate 7 are joined. As shown in FIG. 1, the first main surface 1 a of the first semiconductor chip 1 has a plurality of first pads 1 c along each side on each of the two peripheral edges of the pair. Is formed.

  Due to the mounting of the first semiconductor chip 1, the distance (M1) between the end portion of the first semiconductor chip 1 and the bonding lead 7c on the side in the vertical direction (direction of the BB cross section) of the wiring substrate 7 in FIG. 1 is shorter than the distance (M2) between the end portion of the first semiconductor chip 1 and the bonding lead 7c on the side in the left-right direction (the direction of the AA cross section) of the wiring board 7 in FIG. 1 (M1 <M2). ).

  Thereafter, second die bonding shown in step S3 is performed. That is, as shown in FIGS. 11, 12, and 13, die bonding of the upper second semiconductor chip 2 is performed. Here, the second semiconductor chip 2 having the second main surface 2a in which a plurality of second pads 2c are formed and having a smaller outer dimension than the first main surface 1a of the first semiconductor chip 1 is referred to as the first semiconductor chip 1. The first main surface 1a is mounted on the first semiconductor chip 1 so as to be positioned inside (between) the plurality of first pads 1c provided along each of the opposing pair of sides. At this time, a pair of the first semiconductor chip 1 is also arranged from the central portion of the main surface (first main surface) 1a of the first semiconductor chip 1 to the central portion of the main surface (second main surface) 2a of the second semiconductor chip 2. Of these sides (fifth side), they are mounted shifted to one side. This is because the formation location of the second pad 2c formed on the second main surface 2a of the second semiconductor chip 2 (particularly along the fourth side) is a bonding lead (second bonding lead) 7c of the wiring board 7. This is because it does not coincide with the formation location of. Therefore, when the central portion of the second semiconductor chip 2 is not shifted and stacked, the first pad 1c formed along the sixth side of the first semiconductor chip 1 and the second side of the wiring substrate 7 are formed. A wire (first positive bonding wire) 3 that electrically connects the first bonding lead 7 c, a second pad 2 c formed along the fourth side of the second semiconductor chip 2, and a second side of the wiring substrate 7 A portion where the wire (second positive bonding wire) 3 electrically connecting the second bonding lead 7c formed along the line overlaps in a plane is generated. And in the process of forming the sealing body later, there is a possibility that the wires that have flowed by the filling pressure of the resin come into contact with each other. Therefore, in the present embodiment, the central portion of the main surface (second main surface) 2a of the second semiconductor chip 2 is changed from the central portion of the main surface (first main surface) 1a of the first semiconductor chip 1 to the first semiconductor. Of the pair of sides (fifth side) of the chip 1, the chip 1 is mounted shifted to one side. Thereby, the wire 3 electrically connected to the second semiconductor chip 2 and the wiring board 7 does not overlap with the wire 3 electrically connecting the first semiconductor chip 1 and the wiring board 7 in a plane, In the step of forming the resin sealing body, the wires can be prevented from contacting each other. In addition, as shown in FIG. 12, the adhesive 6 is attached in advance to the back surface 2 b of the second semiconductor chip 2, and the second semiconductor chip 2 is arranged on the first main surface 1 a of the first semiconductor chip 1. Thereafter, the back surface 2b of the second semiconductor chip 2 and the first main surface 1a of the first semiconductor chip 1 are joined by thermocompression bonding. Note that, on the first main surface 1a of the first semiconductor chip 1, a plurality of first pads 1c are formed along each side at each of the peripheral portions of a pair of two sides facing each other.

  By mounting the second semiconductor chip 2, the distance (L 1, L 2) between the end of the second semiconductor chip 2 and the end of the first semiconductor chip 1 is the end of the first semiconductor chip 1 as shown in FIG. And a distance (M1, M2) between the wiring board 7 and the bonding lead 7c (L1> M1, L2> M2).

  Thereafter, the first wire bonding shown in step S4 is performed. That is, as shown in FIGS. 14, 15, and 16, wire bonding of the lower first semiconductor chip 1 is performed. Here, the plurality of first pads 1c of the first semiconductor chip 1 and the plurality of bonding leads 7c of the wiring board 7 corresponding thereto are electrically connected through the plurality of first wires 3a, respectively. At that time, first, one end portion of the wire 3 is connected to the first pad 1 c of the first semiconductor chip 1, and then the other end portion of the wire 3 is connected to the bonding lead 7 c of the wiring substrate 7. That is, in the multichip module 8 according to the first embodiment, the first semiconductor chip 1 at the lower stage is provided with a plurality of first pads 1c only on two sides in one facing direction (direction of the AA cross section). Therefore, in this direction, the first pad 1c and the bonding lead 7c are connected by performing wire bonding only by positive bonding.

  Thereafter, the second wire bond shown in step S5 is performed. That is, as shown in FIGS. 17 to 22, wire bonding of the upper second semiconductor chip 2 is performed. Here, the plurality of second pads 2c of the second semiconductor chip 2 and the plurality of bonding leads 7c of the wiring board 7 corresponding thereto are electrically connected through the plurality of second wires 3b, respectively. At that time, in the second semiconductor chip 2, the second pad 2 c is formed on the peripheral edge along the four sides of the second main surface 2 a, and bonding is performed using the normal bonding and the reverse bonding separately for each side. .

  Therefore, in the second semiconductor chip 2, positive bonding is performed in the same manner on the two opposite sides on the same side as the two opposite sides on which the positive bonding is performed in the first semiconductor chip 1 in the lower stage. Reverse bonding is performed on two opposing sides in a direction intersecting the side.

  Accordingly, as shown in FIGS. 17, 18, and 19, first, positive bonding is performed on two sides on the same side as the two sides on which positive bonding is performed in the first semiconductor chip 1, and then, FIG. As shown in FIG. 21 and FIG. 22, reverse bonding is performed on two opposing sides in a direction intersecting with these two sides. At that time, in the positive bonding, first, one end of the wire 3 is connected to the second pad 2 c of the second semiconductor chip 2, and then the other end of the wire 3 is connected to the bonding lead 7 c of the wiring substrate 7. On the other hand, in reverse bonding, first, one end of the wire 3 is connected to the bonding lead 7 c of the wiring substrate 7, and then the other end of the wire 3 is connected to the second pad 2 c of the second semiconductor chip 2.

  As shown in FIG. 22, the second pad 2c of the second semiconductor chip 2 to which the other end portion of the wire 3 is connected by reverse bonding is called a stud bump on the second pad 2c before reverse bonding. The gold bump 3c is connected in advance, and the other end of the wire 3 is connected to the gold bump 3c during reverse bonding.

  At that time, the connection of the gold bumps 3c may be formed in advance for all the second pads 2c to be reverse-bonded in the first stage of the second wire bonding process in step S5, or You may form in each of the 2nd pad 2c in which a reverse bonding is performed in a series of reverse bonding operation | movement with respect to each 2nd pad 2c.

  After the second wire bond is completed, resin sealing shown in step S6 is performed. 23 is formed by transfer molding, and the first semiconductor chip 1, the second semiconductor chip 2, the plurality of first wires 3a, and the plurality of second wires 3b on the wiring substrate 7 are molded resin. Sealed with a sealing body 4 made of (resin) 10.

  36, the outer dimension of the upper semiconductor chip 13 is smaller than the outer dimension of the lower semiconductor chip 13, and the end portion of the lower semiconductor chip 13 and the semiconductor device 15 of the comparative example shown in FIG. If the distance between the wiring substrate 7 and the bonding lead 7c is short and the distance between the pad 13b of the upper semiconductor chip 13 and the bonding lead 7c is long, a wire short circuit with the chip is likely to occur.

  As a countermeasure against this wire short-circuit, it can be considered that all the wires 3 are simply reverse-bonded.

  However, as shown in FIG. 29, the distance (gap) between the wire formed by the reverse bonding method and the semiconductor chip is, as shown in FIG. 28, between the wire formed by the normal bonding method and the end of the semiconductor chip. It becomes larger than the interval (gap). Thus, the inventors of the present application have found that when a wire is formed by the reverse bonding method, the amount of resin flowing into the gap increases, and the wire flow is more likely to occur than a wire formed by the normal bonding method.

  Therefore, in the multichip module 8 of the first embodiment, not only all the wires 3 are reverse-bonded, but both reverse bonding and normal bonding are employed as shown in FIGS. The direction (filling direction) in which the mold resin 10 is supplied at the time of molding in the resin sealing process for assembling the multichip module 8 is taken into consideration.

  That is, as shown in FIG. 26 and FIG. 27, after connecting one end of the plurality of second wires 3b to the bonding lead 7c of the wiring board 7 in the resin sealing step of step S6 of FIG. A mold resin (resin) 10 is inserted into the cavity 9b of the mold 9 from the side of the wiring substrate 7 corresponding to the bonding lead 7c row in which wire bonding is performed to connect the portion to the second pad 2c of the second semiconductor chip 2. Fill. That is, among the four sides of the wiring board 7, the mold resin is inserted into the cavity 9b from the side of the wiring board 7 (one side of the pair of first sides) corresponding to the bonding lead 7c row where reverse bonding is performed. 10 is filled.

  Therefore, the mold 9 has a structure in which a plurality of gates 9c are provided on the side of the wiring board 7 corresponding to the bonding lead 7c row where reverse bonding is performed. And the mold resin 10 can be inject | poured into the filling direction 11 shown in FIG. That is, the mold 9 has a structure in which a plurality of gates 9c are provided on the side of the wiring board 7 corresponding to the bonding lead 7c row where reverse bonding is performed, so that among the plurality of second wires 3b, The mold resin 10 can be injected into the cavity 9b of FIG. 26 along the wiring direction 14 (the same direction as the BB cross section shown in FIG. 1) of the second wire 3b subjected to the reverse bonding shown in FIG. .

  The mold 9 includes an upper mold 9 a having a cavity 9 b that is a recess for forming the sealing body 4, a lower mold 9 d having a mold surface 9 e on which the wiring substrate 7 is disposed, and a mold resin 10. It has a gate 9c having an inlet to the cavity 9b, a runner 9g that is a flow path that communicates with the gate 9c and guides the mold resin 10, and a pot 9f that sends the mold resin 10 to the runner 9g.

  FIG. 26 and FIG. 27 show a case where resin molding is performed on the wiring board 7 for multi-cavity. That is, in a state where the wiring board 7 is disposed in the cavity 9b shown in FIG. 26, the wiring board 7 corresponding to the bonding lead 7c row in which reverse bonding is performed on the mold area 7f of the wiring board 7 shown in FIG. The mold resin 10 is injected from a plurality of gates 9c provided on the side of the mold so as to be in the filling direction 11 along the wiring direction 14 of the second wire 3b subjected to reverse bonding.

  By filling the mold resin 10 from the side of the wiring board 7 corresponding to the bonding lead 7c row where reverse bonding is performed in this way, wire shorts between the second wire 3b and the lower first semiconductor chip 1 can be reduced. In addition, since the resin resistance to the second wire 3b subjected to the reverse bonding during the resin molding can be reduced, the wire flow of the second wire 3b subjected to the reverse bonding can be reduced.

  After the resin filling is completed, the mold resin 10 is cured, whereby the collective sealing body 4 shown in FIG. 23 can be formed.

  Next, after the resin sealing step, ball attachment shown in step S7 in FIG. 4 is performed. That is, as shown in FIG. 24, a plurality of solder balls 5 as external terminals are formed on the back surface 7 b of the wiring board 7.

  Thereafter, substrate cutting (separation) shown in step S8 is performed. That is, as shown in FIG. 25, the wiring board 7 and the sealing body 4 are cut into individual pieces, and the assembly of the multichip module 8 is completed.

  Also in the assembly of the multichip module 8 of the first embodiment, the distance between the end of the second semiconductor chip 2 (upper stage) and the end of the first semiconductor chip 1 (lower stage) is the end of the first semiconductor chip 1. When the distance between the wiring board 7 and the bonding lead 7c of the wiring board 7 is longer than the distance between the first semiconductor chip 1 and the second semiconductor chip 2, a plurality of second wires 3b are connected by the reverse bonding method. Thus, the second wire 3b can be sharply raised.

  Accordingly, a large clearance can be provided between the end portion of the lower first semiconductor chip 1 and the second wire 3b, and a short circuit between the lower first semiconductor chip 1 and the wire 3 can be prevented. .

(Embodiment 2)
30 is a plan view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention through the sealing body, and FIG. 31 is a cross section showing an example of the structure cut along the line AA in FIG. 32 and 32 are cross-sectional views showing an example of a structure cut along the line BB in FIG. 33 is a plan view showing an example of the wire bonding state of the lower chip in the first wire bond of the method for manufacturing the semiconductor device shown in FIG. 30, and FIG. 34 is a structure cut along the line AA in FIG. FIG. 35 is a sectional view showing an example of a structure cut along the line BB in FIG. 33.

  In the semiconductor device according to the second embodiment, the first semiconductor chip 1 and the second semiconductor chip 2 whose main surface 2a is smaller than the first semiconductor chip 1 are stacked, similarly to the multichip module 8 according to the first embodiment. The multichip module 12 employs both normal bonding and reverse bonding.

  In the multichip module 8 of the first embodiment shown in FIG. 1, a plurality of first wires 3a connected to the first semiconductor chip 1 are formed along only one direction (direction of the AA cross section). On the other hand, in the multichip module 12 of the second embodiment, the two directions (the direction of the AA cross section and the direction of the BB cross section) where the plurality of first wires 3a connected to the first semiconductor chip 1 intersect. Direction).

  That is, a first pad 1c, which is a plurality of electrodes formed on the main surface 1a of the lower first semiconductor chip 1, is provided along each peripheral edge of each of the four sides of the main surface 1a. The first pads 1c and a plurality of bonding leads 7c of the wiring board 7 provided corresponding to each of the four sides of the first semiconductor chip 1 are electrically connected by the first wires 3a. That is, a plurality of first wires 3 a that connect the lower first semiconductor chip 1 and the bonding leads 7 c of the wiring substrate 7 are formed on each of the four sides of the first semiconductor chip 1.

  At that time, in the multichip module 12, among the first wires 3a formed on the four sides of the first semiconductor chip 1, a plurality of first wires 3a formed along the direction of the BB cross section of FIG. 32 is formed by reverse bonding as shown in FIG. 32. On the other hand, a plurality of first wires 3a formed along the direction of the AA cross section of FIG. 30 are formed by normal bonding as shown in FIG. Reverse bonding and normal bonding are mixed for each side.

  In other words, the plurality of first wires 3a has an angle (θ2) formed between the first wire 3a and the surface 7a of the wiring board 7 on the bonding lead 7c of each of the plurality of first wires 3a. A wire 3 (positive bonding shown in FIG. 28) smaller than an angle (θ1) formed between the first wire 3a on the first pad 1c of each first semiconductor chip 1 and the first main surface 1a of the first semiconductor chip 1 Contains. In addition, the angle (θ4) formed between the first wire 3a and the surface 7a of the wiring board 7 on the bonding lead 7c of each of the plurality of first wires 3a is the first semiconductor chip 1 of each of the plurality of first wires. The wire 3 (reverse bonding shown in FIG. 29) larger than the angle (θ3) formed between the first wire 3a on the 1 pad 1c and the first main surface 1a of the first semiconductor chip 1 is included. Includes both bonding.

  The plurality of second wires 3b connected to the upper second semiconductor chip 2 are the same as those of the multichip module 8 of the first embodiment. That is, with respect to the second wire 3b, reverse bonding is applied to the two opposing sides of the second semiconductor chip 2 in the vertical direction in FIG. 30 (the direction of the BB cross section) as shown in FIG. On the other hand, as shown in FIG. 31, positive bonding is applied to two opposing sides of the second semiconductor chip 2 in the left-right direction (direction of the AA cross section) in FIG.

  Therefore, in the multichip module 12 of the second embodiment, both the first semiconductor chip 1 and the second semiconductor chip 2 are located on the two opposite sides in the vertical direction (B-B cross section direction) in FIG. 32, reverse bonding is applied, while, on the two opposite sides in FIG. 30 in the left-right direction (direction of the AA cross section), normal bonding is applied as shown in FIG. Yes.

  Thus, in the multichip module 12, the upper second wire 3b and the lower first wire 3a are formed on each of the four sides.

  However, in the multichip module 12, like the multichip module 8, the plurality of bonding leads 7 c arranged along the peripheral edge of each side of the rectangular surface 7 a of the wiring substrate 7 are arranged in a row. . This is because the distance between the end of the first semiconductor chip 1 in the lower stage and the end of the wiring substrate 7 is short, so that it is difficult to arrange the bonding leads 7c in a plurality of rows. This is because the bonding leads 7c have to be arranged in a line.

  Therefore, in the multichip module 12, it is necessary to form each of the plurality of second wires 3b on the upper stage side and each of the plurality of first wires 3a on the lower stage side so as not to overlap in a plane.

  Therefore, the multichip module 12 of the second embodiment is provided with a means for preventing the plurality of second wires 3b on the upper stage side from overlapping the plurality of first wires 3a on the lower stage side. First, as shown in FIG. 30, the plurality of second pads 2c of the second semiconductor chip 2 on the upper stage side are arranged at a plurality of different types of pitches.

  That is, a plurality of types of pitches of the plurality of second pads 2c of the second semiconductor chip 2 are set, for example, a first pitch (P1) and a second pitch (P2) wider than the first pitch, etc. The first wires 3a are arranged between the wide second pitches (P2), so that the plurality of second wires 3b on the upper stage side and the plurality of first wires 3a on the lower stage side do not overlap in plan view. Can be.

  Further, as shown in FIG. 30, the second semiconductor chip 2 on the upper stage side is arranged so that the center 2 d of the second semiconductor chip 2 is eccentric to a position different from the center 1 d of the first semiconductor chip 1. . That is, the center 1d of the lower first semiconductor chip 1 and the center 2d of the upper second semiconductor chip 2 are shifted (eccentrically) arranged, whereby the plurality of second wires 3b on the upper stage side and the lower stage 2d are arranged. The plurality of first wires 3a on the side can be prevented from overlapping in a plane.

  It should be noted that means for preventing the plurality of second wires 3b on the upper stage side from overlapping with the plurality of first wires 3a on the lower stage side (changing the pitch of the second pads 2c or decentering the second semiconductor chip 2). Needless to say, the above may be applied to the multichip module 8 of the first embodiment.

  Since the other structure and other effects of the multichip module 12 of the second embodiment are the same as those of the multichip module 8 of the first embodiment, a duplicate description thereof is omitted.

  Next, assembly of the multichip module 12 of the second embodiment will be described. The assembly of the multichip module 12 is substantially the same as the assembly of the multichip module 8 of the first embodiment, but differs from the first embodiment in that the first wire bonding step in step S4 of the process flow shown in FIG. The first wire 3a is normally bonded and reversely bonded.

  That is, in the first wire bonding step of step S4, first, the normal bonding is performed on the lower first semiconductor chip 1 as shown in FIG. 34, and after the normal bonding is completed, the reverse bonding is performed as shown in FIG. . Thereby, as shown in FIG. 33, wire bonding to the lower first semiconductor chip 1 is completed. Thereafter, the second wire bonding step of step S5 is similarly performed in the order of normal bonding and reverse bonding.

  However, when the normal bonding and the reverse bonding are clearly classified for each side as in the multichip module 12 of the second embodiment, all the upper and lower positive bondings are performed first, and then the upper and lower The reverse bonding may be performed.

  The other steps for assembling the multichip module 12 according to the second embodiment are the same as those of the multichip module 8 according to the first embodiment, and a duplicate description thereof will be omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case of the multi-chip modules 8 and 12 having RF-IC and Secure IC is taken as an example as the semiconductor device. However, the semiconductor device includes a microcomputer chip and a memory chip. It may be SIP (System In Package) or the like.

  In the embodiment, the first semiconductor chip 1 is mounted on the wiring board 7 so that the first back surface 1b of the first semiconductor chip 1 faces the front surface 7a of the wiring board 7, and the wire serving as a connecting means is used. The first semiconductor chip 1 and the wiring substrate 7 are electrically connected via the wiring, but the present invention is not limited to this. For example, as shown in FIG. 37, protruding electrodes (gold bumps) 16 are formed on the first pads 1 c of the first semiconductor chip 1, and the first main surface 1 a of the first semiconductor chip 1 is the wiring substrate 7. The first semiconductor chip 1 may be mounted on the wiring board 7 through the protruding electrodes 16 so as to face the surface 7a. An underfill resin 17 is filled between the first semiconductor chip 1 and the wiring substrate 7. In this case, bonding leads 7c are formed on the surface 7a of the wiring board 7 at the same pitch as the first pads 1c in the chip mounting area 7g on which the first semiconductor chip 1 is mounted, as shown in FIG. Use what you have. As a result, the speed of the semiconductor device can be increased as compared with the structure in which the first semiconductor chip 1 and the wiring substrate 7 are electrically connected via the wires.

  The present invention is suitable for an electronic device having a plurality of semiconductor chips.

It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. FIG. 2 is a process flow diagram illustrating an example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a plan view showing an example of a structure of a wiring board incorporated in the semiconductor device of FIG. 1. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. FIG. 5 is a plan view illustrating an example of a die bonding state of a lower chip in a first die bond of the manufacturing method illustrated in FIG. 4. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is a top view which shows an example of the die bonding state of the upper stage chip | tip in the 2nd die bond of the manufacturing method shown in FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is a top view which shows an example of the wire bonding state of the lower stage chip | tip in the 1st wire bond of the manufacturing method shown in FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is a top view which shows an example of the wire bonding state of the positive bonding of the upper stage chip | tip in the 2nd wire bond of the manufacturing method shown in FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is a top view which shows an example of the wire bonding state of the reverse bonding of the upper stage chip | tip in the 2nd wire bond of the manufacturing method shown in FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is sectional drawing which shows an example of the structure after resin sealing in the manufacturing method shown in FIG. It is sectional drawing which shows an example of the structure after ball attachment in the manufacturing method shown in FIG. It is sectional drawing which shows an example of the structure after the board | substrate cutting | disconnection in the manufacturing method shown in FIG. It is a fragmentary sectional view which shows an example of the resin filling direction in the resin sealing process of the manufacturing method shown in FIG. It is a fragmentary top view which shows an example of the resin filling direction of FIG. It is a fragmentary sectional view which shows an example of the positive bonding in the manufacturing method of the semiconductor device of embodiment of this invention. It is a fragmentary sectional view which shows an example of the reverse bonding in the manufacturing method of the semiconductor device of embodiment of this invention. It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. FIG. 31 is a plan view illustrating an example of a wire bonding state of a lower chip in a first wire bond in the method for manufacturing the semiconductor device illustrated in FIG. 30. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is sectional drawing which shows the structure of the semiconductor device of a comparative example. It is sectional drawing of the semiconductor device of the modification of this invention. It is a top view of the wiring board in the semiconductor device of the modification of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor chip 1a 1st main surface 1b Back surface 1c 1st pad (1st electrode pad)
1d center 2 second semiconductor chip 2a second main surface 2b back surface 2c second pad (second electrode pad)
2d center 3 wire 3a first wire 3b second wire 3c gold bump 3d bending point 4 sealing body 5 solder ball (external terminal)
6 Adhesive 7 Wiring board (Board)
7a Surface (main surface)
7b Back surface 7c Bonding lead 7d Solder resist film 7e Opening 7f Mold area 7g Chip mounting area 8 Multi-chip module (semiconductor device)
9 Mold Die 9a Upper Die 9b Cavity 9c Gate 9d Lower Die 9e Die Surface 9f Pot 9g Runner 10 Mold Resin (Resin)
11 Filling direction 12 Multi-chip module (semiconductor device)
13 Semiconductor chip 13a Main surface 13b Pad 14 Wiring direction 15 Semiconductor device 16 Projection electrode 17 Underfill resin

Claims (11)

A substrate having opposite rear surface of the plurality of Bonn loading Lee surface de is formed, and said surface,
First main surface in which a plurality of first pads are formed, and the has a first back surface opposite to the first main surface, so as to be positioned inside the plurality of bonding leads of said substrate in a plan view A first semiconductor chip mounted on the surface of the substrate;
A plurality of second pads are formed, and the small second main surface than the outside dimension of the first semiconductor chip, and a second back surface opposite the second major surface, wherein in a plan view the first A second semiconductor chip mounted on the first semiconductor chip, located inside the plurality of first pads of the semiconductor chip and having the second back surface opposed to the first semiconductor chip;
A plurality of first connection means for electrically connecting the plurality of first pads of the first semiconductor chip and the plurality of first bonding leads among the plurality of bonding leads of the substrate;
A plurality of second connection means for electrically connecting the plurality of second pads of the second semiconductor chip and the plurality of second bonding leads among the plurality of bonding leads of the substrate;
A sealing body for sealing the first semiconductor chip, the second semiconductor chip, and the plurality of second connection means;
A plurality of external terminals provided on the back surface of the substrate;
Including
In the second semiconductor chip, the distance between the end of the second semiconductor chip and the end of the first semiconductor chip is longer than the distance between the end of the first semiconductor chip and the bonding lead of the substrate. Mounted on the first main surface of the first semiconductor chip,
The second connecting means is a wire;
An angle formed between the wire on the second bonding lead and the surface of the substrate is formed by the wire on the second pad of the second semiconductor chip and the second main surface of the second semiconductor chip. A semiconductor device characterized by being larger than an angle. The semiconductor device according to claim 1,
The planar shape of the surface of the substrate is a quadrangle having a pair of first sides and a pair of second sides intersecting the first sides,
The plurality of second bonding leads are formed along the first side of the substrate,
The planar shape of the second main surface of the second semiconductor chip is a quadrangle having a pair of third sides aligned with the first side of the substrate and a pair of fourth sides intersecting the third side,
The plurality of second pads are formed along the third side of the second semiconductor chip. The semiconductor device according to claim 2,
The plurality of second bonding leads are further formed along the second side,
The plurality of second pads are further formed along the fourth side,
An angle formed by the wire and the surface of the substrate on the second bonding lead formed along the second side of the substrate is formed along the fourth side of the second semiconductor chip. A semiconductor device, wherein the angle is smaller than an angle formed between the wire on the second pad and the second main surface of the second semiconductor chip. 4. The semiconductor device according to claim 3, wherein a planar shape of the first main surface of the first semiconductor chip is a pair of fifth sides aligned with the first side of the substrate and a pair of intersecting the fifth sides. A quadrilateral having a sixth side;
The distance (M1) between the fifth side of the first semiconductor chip and the second bonding lead formed along the first side of the substrate is the sixth side of the first semiconductor chip and the substrate. A semiconductor device characterized by being shorter than a distance (M2) from the second bonding lead formed along the second side.   5. The semiconductor device according to claim 4, wherein the thickness of the second semiconductor chip is thicker than the thickness of the first semiconductor chip. (A) providing a substrate having a plurality of Bonn loading Lee surface de is formed, and the surface back surface opposite;
(B) a plurality of first main surface where the first pad is formed, and the first semiconductor chip and the first major surface having a first back surface opposite the plurality of bonding leads of said substrate in a plan view Mounting on the surface of the substrate so as to be located inside the substrate;
(C) a plurality of second pads are formed, and the small second main surface than the outside dimension of the first semiconductor chip, and a second semiconductor chip having a second back surface opposite the second major surface Mounting the first semiconductor chip on the first semiconductor chip so that the second back surface faces the first semiconductor chip and is positioned inside the plurality of first pads of the first semiconductor chip in a plan view ;
(D) electrically connecting the plurality of first pads of the first semiconductor chip and the plurality of first bonding leads of the plurality of bonding leads of the substrate via a plurality of first connection means, respectively; The step of:
(E) electrically connecting the plurality of second pads of the second semiconductor chip and the plurality of second bonding leads of the plurality of bonding leads of the substrate via a plurality of second connection means, respectively. The step of:
(F) sealing the first semiconductor chip, the second semiconductor chip, and the plurality of second connection means with a resin;
(G) forming a plurality of external terminals on the back surface of the substrate;
Including
In the second semiconductor chip, the distance between the end of the second semiconductor chip and the end of the first semiconductor chip is longer than the distance between the end of the first semiconductor chip and the bonding lead of the substrate. Mounted on the first main surface of the first semiconductor chip,
The second connecting means is a wire;
In the step (e), after one end of the wire is connected to the second bonding lead of the substrate, the other end opposite to the one end of the wire is connected to the second pad of the second semiconductor chip. A method for manufacturing a semiconductor device, comprising: connecting to a semiconductor device. The method of manufacturing a semiconductor device according to claim 6, wherein the planar shape of the surface of the substrate is a quadrangle having a pair of first sides and a pair of second sides intersecting the first sides,
The plurality of second bonding leads are formed along the first side of the substrate,
The planar shape of the second main surface of the second semiconductor chip is a quadrangle having a pair of third sides aligned with the first side of the substrate and a pair of fourth sides intersecting the third side,
The method of manufacturing a semiconductor device, wherein the plurality of second pads are formed along the third side of the second semiconductor chip.   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (f), the resin is supplied from the first side of the substrate. The method of manufacturing a semiconductor device according to claim 8.
The plurality of second bonding leads are further formed along the second side,
The plurality of second pads are further formed along the fourth side,
The wire for electrically connecting the second bonding lead formed along the second side of the substrate and the second pad formed along the fourth side of the second semiconductor chip, After connecting one end of the wire to the second pad of the second semiconductor chip, connecting the other end of the wire opposite to the one end to the second bonding lead of the substrate. A method of manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 9, wherein a planar shape of the first main surface of the first semiconductor chip intersects with a pair of fifth sides aligned with the first side of the substrate and the fifth side. A quadrilateral having a pair of sixth sides,
The distance (M1) between the fifth side of the first semiconductor chip and the second bonding lead formed along the first side of the substrate is the sixth side of the first semiconductor chip and the substrate. A method of manufacturing a semiconductor device, characterized in that the distance is shorter than a distance (M2) from the second bonding lead formed along the second side.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the thickness of the second semiconductor chip is thicker than the thickness of the first semiconductor chip.

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