KR930020653A - 반도체 기억 장치의 실장 방법 - Google Patents

반도체 기억 장치의 실장 방법 Download PDF

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Publication number
KR930020653A
KR930020653A KR1019930010377A KR930010377A KR930020653A KR 930020653 A KR930020653 A KR 930020653A KR 1019930010377 A KR1019930010377 A KR 1019930010377A KR 930010377 A KR930010377 A KR 930010377A KR 930020653 A KR930020653 A KR 930020653A
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South Korea
Prior art keywords
electrodes
semiconductor
semiconductor chip
electrically connected
leads
Prior art date
Application number
KR1019930010377A
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English (en)
Other versions
KR970003913B1 (ko
Inventor
마사유끼 와다나베
도시오 스가노
세이이찌로 쯔구이
다까시 오노
요시아끼 와까시마
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
스즈끼 진이찌로
히다찌도부세미콘닥터 가부시끼가이샤
사또 고고
아끼따덴시 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62155478A external-priority patent/JP2603636B2/ja
Priority claimed from JP62226307A external-priority patent/JP2642359B2/ja
Application filed by 미다 가쓰시게, 가부시끼가이샤 히다찌세이사꾸쇼, 스즈끼 진이찌로, 히다찌도부세미콘닥터 가부시끼가이샤, 사또 고고, 아끼따덴시 가부시끼가이샤 filed Critical 미다 가쓰시게
Publication of KR930020653A publication Critical patent/KR930020653A/ko
Application granted granted Critical
Publication of KR970003913B1 publication Critical patent/KR970003913B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • G—PHYSICS
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

반도체 칩을 모듈화하여 모듈 기관에 여러개 탑재하여 구성한 반도체 기억 장치의 실장 방법으로서, 반도체칩을 기판에 고밀도로 실장하기 위하여, 집적 회로 소자와 여러개의 제1전극 및 제2전극이 형성된 주면을 갖는 제1및 제2의 반도체 칩, 제1의 반도체 칩의 여러개의 제1전근중의 하나와 제2의 반도체 칩의 여러개의 제1전극중의 하나를 각각 전기적으로 접속하고 있는 여러개의 제1리이드 제1의 반도체 칩의 제2전극에 전기적으로 접속된 제2리이드와 제2의 반도체 칩의 제2전극에 전기적으로 접속된 제3리이드로 이루어지고, 제2의 반도체 칩이 제1의 반도체 칩상에 적층된 제1의 반도체 기억 장치를 준비하고, 집적 회로 소자와 여러개의 제3전극 및 제4전극이 형성된 주면을 갖는 제3및 제4의 반도체 칩, 제3의 반도체 칩의 여러개의 제3전극중의 하나와 제4의 반도체 칩의 여러개의 제3전극중의 하나를 각각 전기적으로 접속하고 있는 여러개의 제4리이드, 제3의 반도체 칩의 제4전극에 전기적으로 접속된 제5리이드와 제4의 반도체 칩의 제4전극에 전기적으로 접속된 제6리이드로 이루어지고, 제4의 반도체 칩이 제3의 반도체 칩상에 적층된 제2의 반도체 기억 장치를 준비하고, 표면 및 이면에 여러개의 접속 단자가 형성된 양면 실장판을 준비하고, 제1의 반도체 기억 장치를, 그의 제1 및 제2의 반도체 칩의 제1전극이 제1리이드를 거쳐 공통으로 기판의 표면에 형성된 접속 단자에 전기적으로 접속되고 제1 및 제2의 반도체 칩의 제2전극이 서로 전기적으로 독립적으로 되도록 제2 및 제3리이드를 거쳐 기판의 표면에 형성된 접속 단자에 전기적으로 접속되도록 실장하며, 제2의 반도체 기억장치를, 그의 제3 및 제4의 반도체 칩의 제3전극이 제4리이드를 거쳐 공통으로 기판의 이면에 형성된 접속단자에 전기적으로 접속되고 제3 및 제4의 반도체 칩의 제4전극이 서로 전기적으로 독립적으로 되도록 제5 및 제6리이드를 거쳐 기판의 표면에 형성된 접속단자에 전기적으로 접속되도록 실장한다.
이러한 반도체 기억 장치의 실장 방법에 의해, 고밀도의 실장을 달성할 수 있다.

Description

반도체 기억 장치의 실장 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예1의 I의 반도체 장치의 개략 구성을 도시한 평면도이다.
제2도는 상기 반도체 장치의 개략 구성을 도시한 측면도이다.
제3도는 상기 반도체 장치의 개략 구성을 도시한 정면도이다.

Claims (14)

  1. 집적 회로 소자와 여러개의 제1전극 및 제2전극이 형성된 주면을 갖는 제1 및 제2의 반도체 칩, 상기 제1의 반도체 칩의 상기 여러개의 제1전극중의 하나와 상기 제2의 반도체 칩의 상기 여러개의 제1전극중의 하나를 각각 전기적으로 접속하고 있는 여러개의 제1리이드, 상기 제1의 반도체 칩의 제2전극에 전기적으로 접속된 제2리이드와 상기 제2의 반도체 칩의 제2전극에 전기적으로 접속된 제3리이드로 이루어지고, 상기 제2의 반도체 칩이 상기 제1의 반도체 칩상에 적층된 제1의 반도체 기억 장치를 준비하는 공정, 집적 회로 소자와 여러개의 제3전극 및 제4전극이 형성된 주면을 갖는 제3 및 제4의 반도체 칩, 상기 제3의 반도체 칩의 상기 여러개의 제3전극중의 하나와 상기 제4의 반도체 칩의 상기 여러개의 제3전극중의 하나를 각각 전기적으로 접속하고 있는 여러개의 제4리이드, 상기 제3의 반도체 칩의 제4전극에 전기적으로 접속된 제5리이드와 상기 제4의 반도체 칩의 제4전극에 전기적으로 접속된 제6리이드로 이루어지고, 상기 제4의 반도체 칩이 상기 제3의 반도체 칩상에 적층된 제2의 반도체 기억 장치를 준비하는 공정, 표면 및 이면에 여러개의 접속 단자가 형성된 양면 실장판을 준비하는 공정, 상기 제1의 반도체 기억 장치를, 그의 상기 제1 및 제2의 반도체 칩의 제1전극이 제1리이드를 거쳐 공통으로 상기 기판의 표면에 형성된 접속 단자에 전기적으로 접속되고 제1 및 제2의 반도체 칩의 제2전극이 서로 전기적으로 독립적으로 되도록 상기 제2 및 제3리이드를 거쳐 상기 기판의 표면에 형성된 접속 단자에 전기적으로 접속되도록 실장하는 공정과, 상기 제2의 반도체 기억장치를, 그의 상기 제3 및 제4의 반도체 칩의 제3전극이 상기 제4리이드를 거쳐 공통으로 상기 기판의 이면에 형성된 접속단자에 전기적으로 접속되고 상기 제3 및 제4의 반도체 칩의 제4전극이 서로 전기적으로 독립적으로 되도록 상기 제5 및 제6리이드를 거쳐 상기 기판의 표면에 형성된 접속단자에 전기적으로 접속되도록 실장하는 공정으로 이루어지는 반도체 기억 장치의 실장 방법.
  2. 제1항에 있어서, 상기 여러개의 제1 및 제4리이드는 상기 제1, 제2, 제3 및 제4의 반도체 칩상에 배치된 어드레스 신호 입력 전극에 접속되어 있는 반도체 기억 장치의 실장 방법.
  3. 제1항에 있어서, 상기 여러개의 제1 및 제4리이드는 상기 제1, 제2, 제3 및 제4의 반도체 칩상에 배치된 데이타 입출력 신호용의 전극에 접속되어 있는 반도체 기억 장치의 실장 방법.
  4. 제1항에 있어서, 상기 제2 및 제3리이드는 상기 제1 및 제2의 반도체 칩상에 배치된 제1 및 제2의 반도체 칩을 선택하는 신호를 입력하는 전극에 각각 접속되어 있는 반도체 기억 장치의 실장 방법.
  5. 제1항에 있어서, 상기 제5 및 제6리이드는 상기 제3 및 제4의 반도체 칩상에 배치된 제3 및 제4의 반도체 칩을 선택하는 신호를 입력하는 전극에 각각 접속되어 있는 반도체 기억 장치의 실장 방법.
  6. 제1항에 있어서, 상기 제2 및 제4전극은 칩 선택 단자인 반도체 기억 장치의 실장 방법.
  7. 제1항에 있어서, 상기 제1, 제2, 제3 및 제4전극은 범프 전극인 반도체 기억 장치의 실장 방법.
  8. 집적 회로 소자와 여러개의 제1전극 및 제2전극이 형성된 주면을 갖는 제1 및 제2의 반도체 칩, 상기 제1의 반도체 칩의 상기 여러개의 제1전극중의 하나와 상기 제2의 반도체 칩의 상기 여러개의 제1전극중의 하나를 각각 전기적으로 접속하고 있는 여러개의 제1리이드, 상기 제1의 반도체 칩의 제2전극에 전기적으로 접속된 제2리이드와 상기 제2의 반도체 칩의 제2전극에 전기적으로 접속된 제3리이드로 이루어지고, 상기 제2의 반도체 칩이 상기 제1의 반도체 칩상에 적층된 제1의 반도체 기억 장치를 준비하고, 집적 회로 소자와 여러개의 제3전극 및 제4전극이 형성된 주면을 갖는 제3 및 제4의 반도체 칩, 상기 제3의 반도체 칩의 상기 여러개의 제3전극중의 하나와 상기 제4의 반도체 칩의 상기 여러개의 제3전극중의 하나를 각각 전기적으로 접속하고 있는 여러개의 제4리이드, 상기 제3의 반도체 칩의 제4전극에 전기적으로 접속된 제5리이드와 상기 제4의 반도체 칩의 제4전극에 전기적으로 접속된 제6리이드로 이루어지고, 상기 제4의 반도체 칩이 상기 제3의 반도체 칩상에 적층된 제2의 반도체 기억 장치를 준비하고, 표면 및 이면에 여러개의 접속 단자가 형성되고 상기 접속 단자에 전기적으로 접속된 여러개의 외부리이드를 갖는 양면 실장판을 준비하고, 상기 제1의 반도체 기억 장치를, 그의 상기 제1및 제2의 반도체 칩의 제1전극이 제1리이드를 거쳐 공통으로 상기 기판의 표면에 형성된 접속 단자에 전기적으로 접속되고 상기 제1및 제2의 반도체 칩의 제2전극이 서로 전기적으로 독립적으로 되도록 상기 제2 및 제3리이드를 거쳐 상기 기판의 표면에 형성된 접속 단자에 전기적으로 접속되도록 실장하는 공정과, 상기 제2의 반도체 기억장치를, 그의 상기 제3및 제4의 반도체 칩의 제3전극이 상기 제4리이드를 거쳐 공통으로 상기 기판의 이면에 형성된 접속단자에 전기적으로 접속되고 상기 제3 및 제4의 반도체 칩의 제4전극이 서로 전기적으로 독립적으로 되도록 상기 제5및 제6리이드를 거쳐 상기 기판의 표면에 형성된 접속단자에 전기적으로 접속되도록 실장하는 것에 의해 반도체 메모리 모듈을 조립하는 공정, 여러개의 납땜부가 형성된 배선 기판을 준비하는 공정과 상기 양면 실장판의 상기 외부 리이드가 상기 납땜부와 전기적으로 접속하도록 상기 반도체 메모리 모듈을 상기 배선 기판상에 실장하는 공정으로 이루어지는 반도체 기억 장치의 실장 방법.
  9. 제8항에 있어서, 상기 여러개의 제1 및 제4리이드는 상기 제1, 제2, 제3 및 제4의 반도체 칩상에 배치된 어드레스 신호 입력 전극에 접속되어 있는 반도체 기억 장치의 실장 방법.
  10. 제8항에 있어서, 상기 여러개의 제1 및 제4리이드는 상기 제1, 제2, 제3 및 제4의 반도체 칩상에 배치된 데이타 입출력 신호용의 전극에 접속되어 있는 반도체 기억 장치의 실장 방법.
  11. 제8항에 있어서, 상기 제2 및 제3리이드는 상기 제1 및 제2의 반도체 칩상에 배치된 제1 및 제2의 반도체 칩을 선택하는 신호를 입력하는 전극에 각각 접속되어 있는 반도체 기억 장치의 실장 방법.
  12. 제8항에 있어서, 상기 제5 및 제6리이드는 상기 제3및 제4의 반도체 칩상에 배치된 제3 및 제4의 반도체 칩을 선택하는 신호를 입력하는 전극에 각각 접속되어 있는 반도체 기억 장치의 실장 방법.
  13. 제8항에 있어서, 상기 제2 및 제4전극은 칩 선택 단자인 반도체 기억 장치의 실장 방법.
  14. 제8항에 있어서, 상기 제1, 제2, 제3 및 제4전극은 범프 전극인 반도체 기억 장치의 실장 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930010377A 1987-06-24 1993-06-09 반도체 기억 장치의 실장 방법 KR970003913B1 (ko)

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JP62155478A JP2603636B2 (ja) 1987-06-24 1987-06-24 半導体装置
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JP62226307A JP2642359B2 (ja) 1987-09-11 1987-09-11 半導体装置

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KR930020654A (ko) 1993-10-20
KR890001186A (ko) 1989-03-18

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