KR970077555A - 적층형 버텀 리드 패키지 - Google Patents

적층형 버텀 리드 패키지 Download PDF

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Publication number
KR970077555A
KR970077555A KR1019960016640A KR19960016640A KR970077555A KR 970077555 A KR970077555 A KR 970077555A KR 1019960016640 A KR1019960016640 A KR 1019960016640A KR 19960016640 A KR19960016640 A KR 19960016640A KR 970077555 A KR970077555 A KR 970077555A
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South Korea
Prior art keywords
lead package
package according
bottom lead
lead
stacked bottom
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KR1019960016640A
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English (en)
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KR100186309B1 (ko
Inventor
김용찬
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문정환
Lg 반도체 주식회사
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Priority to KR1019960016640A priority Critical patent/KR100186309B1/ko
Priority to DE1997116668 priority patent/DE19716668C2/de
Priority to CN97104301A priority patent/CN1064780C/zh
Priority to JP9119047A priority patent/JP2819285B2/ja
Priority to US08/856,317 priority patent/US5939779A/en
Publication of KR970077555A publication Critical patent/KR970077555A/ko
Application granted granted Critical
Publication of KR100186309B1 publication Critical patent/KR100186309B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 적층형 버텀 리드 패키지에 관한 것으로, 종래의 버텀 리드 패키지는 금속 와이어를 이용하여 전기적인 연결을 함으로서 패키지의 경박단소화에 한계가 있는 등의 문제점이 있었던 바, 본 발명 적층형 버텀 리드 패키지는 금속 와이어를 이용하여 전기적인 연결을 하는 와이어 본딩을 배제함으로서 고집적화되는 효과가 있으며, 상, 하부 리드의 양단부를 돌출시켜 접속부를 형성함으로서 패키지의 전기적인 검사가 용이한 효과가 있다.

Description

적층형 버텀 리드 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명 적층형 버텀 리드 패키지의 구조를 보인 종단면도

Claims (6)

  1. 제1 및 제2반도체 칩과. 그 제1 및 제2반도체 칩의 상, 하면 양측에 설치되며 돌기부가 각각 형성된 다수개의 상, 하부 리드와, 상기 돌기부와 상기 반도체 칩의 상면에 형성된 다수개의 칩패드를 각각 연결하는 솔더와, 상기 상부 리드와 하부 리드 사이에 개재되는 접착부재와, 상기 다수개의 리드에 형성된 돌출부가 외부로 노출됨과 아울러 상기 반도체 칩, 상, 하부 리드를 감싸도록 몰딩한 몰딩부를 구비하여서 구성된 것을 특징으로 하는 적층형 버텀 리드 패키지.
  2. 제1항에 있어서, 상기 칩패드와 돌기부가 접속된 부분을 제외한 제1 및 제2반도체 칩의 상면에는 두꺼운 폴리이미드 층이 형성된 것을 특징으로 하는 적층형 버텀 리드 패키지.
  3. 제1항에 있어서, 상기 접착부재는 솔더인 것을 특징으로 하는 것을 특징으로 하는 적층형 버텀 리드 패키지
  4. 제1항에 있어서, 상기 접착부재는 폴리이미드인 것을 특징으로 하는 것을 특징으로 하는 적층형 버텀 리드 패키지.
  5. 제1항에 있어서, 상기 돌출부에는 솔더가 플래덩된 것을 특징으로 하는 것을 특징으로 하는 적층형 버텀 리드 패키지.
  6. 제1항에 있어서, 상기 몰딩부의 양측에는 상, 하부 리드가 연장되어 돌출형성된 접속부가 형성된 것을 특징으로 하는 적층형 버텀 리드 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960016640A 1996-05-17 1996-05-17 적층형 버텀 리드 패키지 KR100186309B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019960016640A KR100186309B1 (ko) 1996-05-17 1996-05-17 적층형 버텀 리드 패키지
DE1997116668 DE19716668C2 (de) 1996-05-17 1997-04-21 Halbleiterchip-Stapelgehäuse mit untenliegenden Zuleitungen
CN97104301A CN1064780C (zh) 1996-05-17 1997-05-04 底部引线半导体芯片堆式封装
JP9119047A JP2819285B2 (ja) 1996-05-17 1997-05-09 積層型ボトムリード半導体パッケージ
US08/856,317 US5939779A (en) 1996-05-17 1997-05-14 Bottom lead semiconductor chip stack package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960016640A KR100186309B1 (ko) 1996-05-17 1996-05-17 적층형 버텀 리드 패키지

Publications (2)

Publication Number Publication Date
KR970077555A true KR970077555A (ko) 1997-12-12
KR100186309B1 KR100186309B1 (ko) 1999-03-20

Family

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Application Number Title Priority Date Filing Date
KR1019960016640A KR100186309B1 (ko) 1996-05-17 1996-05-17 적층형 버텀 리드 패키지

Country Status (5)

Country Link
US (1) US5939779A (ko)
JP (1) JP2819285B2 (ko)
KR (1) KR100186309B1 (ko)
CN (1) CN1064780C (ko)
DE (1) DE19716668C2 (ko)

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DE19716668C2 (de) 1999-05-27
US5939779A (en) 1999-08-17
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