KR970077556A - 적층형 반도체 패키지 - Google Patents

적층형 반도체 패키지 Download PDF

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Publication number
KR970077556A
KR970077556A KR1019960016646A KR19960016646A KR970077556A KR 970077556 A KR970077556 A KR 970077556A KR 1019960016646 A KR1019960016646 A KR 1019960016646A KR 19960016646 A KR19960016646 A KR 19960016646A KR 970077556 A KR970077556 A KR 970077556A
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South Korea
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semiconductor package
thinner
stacked semiconductor
package
package according
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KR1019960016646A
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KR0179921B1 (ko
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조재원
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문정환
Lg 반도체주식회사
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Priority to KR1019960016646A priority Critical patent/KR0179921B1/ko
Priority to CN97104303A priority patent/CN1065660C/zh
Priority to JP9119046A priority patent/JP2819284B2/ja
Priority to DE19720275A priority patent/DE19720275B4/de
Priority to US08/857,462 priority patent/US6153928A/en
Publication of KR970077556A publication Critical patent/KR970077556A/ko
Application granted granted Critical
Publication of KR0179921B1 publication Critical patent/KR0179921B1/ko

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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2924/1627Disposition stacked type assemblies, e.g. stacked multi-cavities

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 적층형 반도체 패키지에 관한 것으로, 종래의 적층형 반도체 패키지는 상, 하부의 인너리드가 소정간격을 두고 설치되어 패키지의 두께가 두꺼워짐으로서 경박단소화에 한계가 있는 등의 문제점이 있었던 바, 본 발명의 적층형 반도체 패키지는 몸체부의 내측에 형성되는 패들을 몸체부보다 얇게 하고, 그 패들의 상, 하면에 제1 및 제2반도체 칩을 실장함으로서 패키지를 경박단소화시키는 효과가 있고, 종래의 까다롭고, 고가의 장비를 필요로하는 범프를 매개로한 본딩을 배재함으로서 생산성 향상 및 원가절감의 효과가 있다.

Description

적층형 반도체 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명 적층형 반도체 패키지의 제조공정 중 준비단계를 설명하기 위한 것으로, (가)는 평면도, (나)는 종단면도.

Claims (5)

  1. 변부에 다수개의 상, 하부 패턴이 형성된 몸체부와, 그 몸체부의 내측에 설치되며 몸체부보다 두께가 얇은 패들과, 그 패들의 상, 하면에 각각 부착되는 제1 및 제2반도체 칩과, 그제1 및 제2반도체 칩과 다수개의 상, 하부 패턴이 각각 전기적으로 연결되는 금속 와이어와, 상기 제1 및 제2반도체 칩, 금속 와이어를 포함하는 일정면적이 코팅된 코팅부를 구비하여서 구성된 것을 특징으로 하는 적층형 반도체 패키지.
  2. 제1항에 있어서, 상기 몸체부는 세라믹인 것을 특징으로 하는 적층형 반도체 패키지.
  3. 제1항에 있어서, 상기 몸체부는 플라스틱인 것을 특징으로 하는 적층형 반도체 패키지.
  4. 제1항에 있어서, 상기 몸체부의 모서리에는 패키지의 다층 구성시 얼라인하기 위한 관통홀이 형성된 것을 특징으로 하는 적층형 반도체 패키지.
  5. 제1항에 있어서, 상기 코팅부는 액상의 폴리이미드인 피아이큐인 것을 특징으로 하는 적층형 반도체 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960016646A 1996-05-17 1996-05-17 적측형 반도체 패키지 KR0179921B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019960016646A KR0179921B1 (ko) 1996-05-17 1996-05-17 적측형 반도체 패키지
CN97104303A CN1065660C (zh) 1996-05-17 1997-05-04 半导体封装基片及其制造方法以及半导体封装
JP9119046A JP2819284B2 (ja) 1996-05-17 1997-05-09 半導体パッケージ用基板およびその製造方法と その基板を利用した積層型半導体パッケージ
DE19720275A DE19720275B4 (de) 1996-05-17 1997-05-14 Substrat für eine Halbleiteranordnung, Herstellungsverfahren für dasselbe und eine das Substrat verwendende stapelbare Halbleiteranordnung
US08/857,462 US6153928A (en) 1996-05-17 1997-05-16 Substrate for semiconductor package, fabrication method thereof, and stacked-type semiconductor package using the substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960016646A KR0179921B1 (ko) 1996-05-17 1996-05-17 적측형 반도체 패키지

Publications (2)

Publication Number Publication Date
KR970077556A true KR970077556A (ko) 1997-12-12
KR0179921B1 KR0179921B1 (ko) 1999-03-20

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US (1) US6153928A (ko)
JP (1) JP2819284B2 (ko)
KR (1) KR0179921B1 (ko)
CN (1) CN1065660C (ko)
DE (1) DE19720275B4 (ko)

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CN1065660C (zh) 2001-05-09
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CN1166058A (zh) 1997-11-26
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