KR950034706A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

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Publication number
KR950034706A
KR950034706A KR1019950002026A KR19950002026A KR950034706A KR 950034706 A KR950034706 A KR 950034706A KR 1019950002026 A KR1019950002026 A KR 1019950002026A KR 19950002026 A KR19950002026 A KR 19950002026A KR 950034706 A KR950034706 A KR 950034706A
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South Korea
Prior art keywords
polyimide resin
lead frame
semiconductor device
protective film
resin layer
Prior art date
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KR1019950002026A
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English (en)
Inventor
마사주미 아마가이
마사기 오수미
Original Assignee
윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
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Application filed by 윌리엄 이. 힐러, 텍사스 인스트루먼츠 인코포레이티드 filed Critical 윌리엄 이. 힐러
Publication of KR950034706A publication Critical patent/KR950034706A/ko

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Abstract

반도체 펙키지가 반도체 칩 기판에 부착된 제1패시배이션 보호막, 제1보호막에 부착된 제2보호막 및 제2보호막에 부착되고 반도체 칩 안에 형성된 회로에 연결된 리드 프레임을 갖는다. 리드 프레임의 주요 부분은 제2보호막의 열가소성 수지 층을 통하여 제2보호막에 부착된다.

Description

반도체 장치 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 LOC 구조를 갖는 IC 팩키지의 단면도, 제2도는 (제4도의 선 Ⅱ-Ⅱ을 따라 절취한) 제1도의 팩키지의 주요 부분의 확대 단면도, 제3도는 (제4도의 선 Ⅲ-Ⅲ을 따라 절취한) 제1도의 팩키지의 주요 부분의 확대 단면도.

Claims (15)

  1. 반도체 칩 상의 제1보호막, 제1보호막 상에 배치된 제2보호막 및 주요 부분이 적어도 제2보호막의 일부로서 작용되는 열가소성 수지에 의하여 제2보호막에 부착되도록 제2보호막에 부착되고 전기적으로 반도체 칩 내에 형성된 회로에 연결된 리드 프레임을 포함하는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 제2보호막이 그 하단 층이 열경화성 폴리이미드형 수지로 만들어지고 그 상단의 층이 열가소성 폴리이미드형 수지로 만들어지고 그 상단의 층이 열가소성 폴리이미드형 수지로 만들어진 라미네이트인 것을 특징으로 하는 반도체 장치.
  3. 제2항에 있어서, 리드 프레임이 접착되는 영역에서는, 열가소성 폴리이드형 수지 층의 두께는 15 내지 35㎛이고 열경화성 폴리이미드형 수지의 두께는 10 내지 30㎛인 상기 열가소성 폴리이드형 수지 층과 상기 열경화성 폴리이미드형 수지 층들이 거의 같은 패턴으로 형성되고, 상기 리드 프레임이 접착되지 않는 영역에서는 열경화성 포리이미드형 수지의 두께가 5 내지 15㎛인 것을 특징으로 하는 반도체 장치.
  4. 제2항에 있어서, 열가소성 폴리이미드형 수지 층이 리드 프레임이 접착되지 않은 영역에서는 열경화성 폴리이미드형 수지 층 상에 역시 배치되고, 열가소성 폴리이미드형 수지 층의 두께가 15 내지 35㎛이고, 열경화성 폴리이미드형 수지의 두께는 10 내지 30㎛인 것을 특징으로 하는 반도체 장치.
  5. 제2항에 있어서, 상기 라미네이트의 전체 두께가 적어도 리드 프레임의 접착영역내에서 35 내지 65㎛인 것을 특징으로 하는 반도체 장치.
  6. 제1항에 있어서, 제2보호막이 단기 열가소성 폴리이미드형 수지인 것을 특징으로 하는 반도체 장치.
  7. 제6항에 있어서, 열가소성 폴리이미드형 수지 층의 두께가 30 내지 50㎛인 것을 특징으로 하는 반도체 장치.
  8. 제6항에 있어서, 열가소성 폴리이미드형 수지가 리드 프레임이 접착되지 않은 영역 상에 역시 배치되는 것을 특징으로 하는 반도체 장치.
  9. 제1항에 있어서, 리드 프레임이 접차고디는 영역 상의 열가소성 폴리이미드형 수지 층의 단부가 상기 리드 프레임의 단부로부터 0.1 내지 0.15㎜만큼 돌출한 것을 특징으로 하는 반도체 장치.
  10. 제1항에 있어서, 반도체 칩의 접착 패드의 변(side)상에서, 반도체 칩의 셀부분의 단부와 열가소성 폴리이미드형 수지 층의 단부 사이의 간격이 100 내지 500㎛인 것을 특징으로 하는 반도체 장치.
  11. 제1항에 있어서, 접착 영역 내에 열가소성 폴리이미드형 수지 층 및/또는 열경화성 폴리이미드형 수지층이 있는 것을 특징으로 하는 반도체 장치.
  12. 제1항에 있어서, 접착 패드와 리드 프레임들이 장치의 전채 바디(body)가 수지에 의하여 밀봉된 상태로 와이어-접착되는 것을 특징으로 하는 반도체 장치.
  13. 제1항에 있어서, 리드 프레임들이 신호 와이어링(wiring)을 위한 제1리드 프레임 부분과 전원 와이어링을 위한 제2리드 프레임을 포함하는 것을 특징으로 하는 반도체 장치.
  14. 제1항의 반도체 장치를 제조하는 방법으로서, 반도체 칩의 보호막 상에 열가소성 수지 층을 코팅하는 단계와 그 다음으로 코팅된 수지를 패터닝(patterning)하고 경화(curing)하며, 그 다음으로 열가소성 수지 층상에 리드 프레임을 접착시키는 단계들을 포함하는 것을 특징으로 하는 반도체 장치.
  15. 제14항에 있어서, 리드 프레임을 접착시킨 후, 반도체 칩의 접착 패드를 리드 프레임에 와이어-접착시키는 단계가 수행되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950002026A 1994-01-31 1995-02-02 반도체 장치 및 그 제조 방법 KR950034706A (ko)

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JP3427713B2 (ja) * 1997-01-22 2003-07-22 株式会社日立製作所 樹脂封止型半導体装置およびその製造方法
TW378345B (en) 1997-01-22 2000-01-01 Hitachi Ltd Resin package type semiconductor device and manufacturing method thereof
JP3169072B2 (ja) 1998-05-15 2001-05-21 日本電気株式会社 半導体装置
JP4666703B2 (ja) * 1999-10-12 2011-04-06 旭化成イーマテリアルズ株式会社 半導体装置及びその材料
JP4003780B2 (ja) 2004-09-17 2007-11-07 カシオ計算機株式会社 半導体装置及びその製造方法
DE102005047856B4 (de) 2005-10-05 2007-09-06 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Systemträger zur Aufnahme der Halbleiterbauteilkomponenten und Verfahren zur Herstellung des Systemträgers und von Halbleiterbauteilen
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US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
US5286679A (en) * 1993-03-18 1994-02-15 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer

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