JP4270095B2 - 電子装置 - Google Patents
電子装置 Download PDFInfo
- Publication number
- JP4270095B2 JP4270095B2 JP2004301406A JP2004301406A JP4270095B2 JP 4270095 B2 JP4270095 B2 JP 4270095B2 JP 2004301406 A JP2004301406 A JP 2004301406A JP 2004301406 A JP2004301406 A JP 2004301406A JP 4270095 B2 JP4270095 B2 JP 4270095B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- wiring
- lead terminal
- electronic device
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims abstract description 119
- 239000011347 resin Substances 0.000 claims description 45
- 229920005989 resin Polymers 0.000 claims description 45
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 238000005304 joining Methods 0.000 claims description 18
- 230000017525 heat dissipation Effects 0.000 claims description 9
- 230000005855 radiation Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 77
- 238000000034 method Methods 0.000 description 47
- 239000000919 ceramic Substances 0.000 description 37
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000007639 printing Methods 0.000 description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 11
- 229910052709 silver Inorganic materials 0.000 description 11
- 239000004332 silver Substances 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 9
- 239000002356 single layer Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 238000007789 sealing Methods 0.000 description 6
- 230000020169 heat generation Effects 0.000 description 5
- 238000010030 laminating Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 206010037660 Pyrexia Diseases 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000011231 conductive filler Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Description
端子(40)と接合される面側から当該配線基板の一部が除去されてなる溝(16)が形
成されており、第1の配線基板の一部とは、第1の配線基板(10)におけるリード端子(40)と接合される面に直交する方向における当該第1の配線基板の全部ではなく途中までの部位であり、溝(16)は、リード端子(40)における第1の配線基板(10)との接合部にて、リード端子(40)の接合部形状に対応した形状に設けられており、リード端子(40)における第1の配線基板(10)との接続端部が、導電性接合部材(50)を介して溝(16)にはめ込まれることにより、第1の配線基板(10)とリード端子(40)との接合がなされていること。
図1は、本発明の第1実施形態に係る電子装置S1の概略断面構成を示す図である。
図1に示される電子装置S1においては、積層して配置された一対の配線基板10、20が備えられている。ここで、図1中の下側の配線基板10を第1の配線基板10、上側の配線基板20を第2の配線基板20とする。
次に、本実施形態の電子装置S1の製造方法について、図2を参照して説明する。図2は、本製造方法を示す工程図であり、(a)〜(d)は概略断面図、(e)は各配線基板10、20とリードフレーム40との接合部の拡大斜視図である。
ところで、本実施形態によれば、積層して配置された第1の配線基板10および第2の配線基板20と、第1の配線基板10と第2の配線基板20との間に介在し、第1および第2の配線基板10、20の間を電気的に接続するリード端子としてのリードフレーム40とを備え、第1および第2の配線基板10、20の周辺部には、リードフレーム40の接合部に対応した位置に溝16、26が形成されており、リードフレーム40における第1および第2の配線基板10、20との接続端部が、導電性接合部材50を介して溝16、26にはめ込まれることにより、第1および第2の配線基板10、20とリードフレーム40との接合がなされていることを特徴とする電子装置S1が提供される。
図3は、本発明の第2実施形態に係る電子装置S2の概略断面構成を示す図である。また、図4は、図3中の下方に位置する矢印A方向から見た概略平面図、図5は、図3中の下方に位置する矢印B方向から見た概略平面図である。なお、図4、図5では、モールド樹脂60の外形を破線にて示してある。
本実施形態の電子装置S2において、配線基板10は、セラミック基板、プリント基板などからなるものであり、また、単層基板であっても、積層基板(多層基板)であってもよい。本例では、配線基板10としては、一般的に知られているセラミック積層基板を採用している。
次に、本実施形態の電子装置S2の製造方法について説明する。
ところで、本実施形態によれば、第1の電子素子30、31が搭載された配線基板10と、この配線基板10に導電性接合部材50を介して接合されたリードフレーム40とを備え、配線基板10の周辺部には、リードフレーム40との接合部に対応した位置に、溝16が形成されており、リードフレーム40における配線基板10との接続端部が、導電性接合部材50を介して溝16にはめ込まれることにより、配線基板10とリードフレーム40との接合がなされており、リードフレーム40のうち配線基板10に接合された面とは反対側の面に、第2の電子素子34が搭載されており、第2の電子素子34と配線基板10とは電気的に接続されていることを特徴とする電子装置S2を提供することができる。
図7は、本発明の第3実施形態に係る電子装置S3の概略断面構成を示す図である。また、図8は、本電子装置S3を図7中の上方に位置する矢印C方向から見た概略平面図である。
本実施形態の電子装置S3において、第1の配線基板10は、セラミック基板、プリント基板などからなるものであり、また、単層基板であっても、積層基板(多層基板)であってもよい。本例では、第1の配線基板10としては、一般的に知られているセラミック積層基板を採用している。
次に、本実施形態の電子装置S3の製造方法について、図9、図10を参照して説明する。図9は、本製造方法を示す工程図であり、図10は、図9に続く本製造方法を示す工程図である。
ところで、本実施形態によれば、次のような点を特徴とする電子装置S3が提供される。
図11は、本発明の第4実施形態に係る電子装置における要部の概略断面構成を示す図である。
図12は、本発明の第5実施形態に係る電子装置S11の概略断面構成を示す図である。本実施形態の電子装置S11は、上記第1実施形態に示した電子装置S1を一部変形したものであり、相違点を中心に述べる。
図13は、本発明の第6実施形態に係る電子装置S21の概略断面構成を示す図である。本実施形態の電子装置S21は、上記第2実施形態に示した電子装置S2を一部変形したものであり、相違点を中心に述べる。
図14は、本発明の第7実施形態に係る電子装置S12の概略断面構成を示す図である。本実施形態の電子装置S12は、上記第1実施形態に示した電子装置S1を一部変形したものであり、相違点を中心に述べる。
図16は、本発明の第8実施形態に係る電子装置S22の概略断面構成を示す図である。本実施形態の電子装置S22は、上記第1実施形態に示した電子装置S1を一部変形したものであり、相違点を中心に述べる。
図17は、本発明の第9実施形態に係る電子装置の要部における概略断面構成を示す図である。図17に示される構成は、上記図4に示される第2実施形態の電子装置の一部を変形したものであるが、本実施形態は、上記第1実施形態の電子装置にも適用することができる。
図18は、本発明の第10実施形態に係る電子装置S23の概略断面構成を示す図である。本実施形態の電子装置S23は、上記第2実施形態に示した電子装置S2を一部変形したものであり、相違点を中心に述べる。
なお、上記実施形態では、配線基板10、20を主として積層基板からなるものとして説明したが、この配線基板10、20は、厚膜基板、プリント樹脂基板であってもよい。さらに、複数の配線基板を採用する実施形態においては、配線基板を積層基板、厚膜基板、プリント樹脂基板などの種類の異なる基板の組合せとしてもよい。
11、12、13、14、21、22、23、24…セラミック層、
16、26…溝、17…端子、20…第2の配線基板、
30、31…第1の電子素子、34…第2の電子素子、35…ボンディングワイヤ、
40…リード端子としてのリードフレーム、
42…リードフレームの延設部、43…放熱板、45…ヒートシンク、
50…導電性接合部材、70…ケース、70a…ケースにおける対向面、
71…ヒートシンク。
Claims (19)
- 積層して配置された第1の配線基板(10)および第2の配線基板(20)と、
前記第1の配線基板(10)と前記第2の配線基板(20)との間に介在し、前記第1および第2の配線基板(10、20)の間を電気的に接続するリード端子(40)とを備え、
前記第1および第2の配線基板(10、20)の周辺部には、これら配線基板(10、20)における前記リード端子(40)と接合される面側から当該配線基板の一部が除去されてなる溝(16、26)が形成されており、
前記配線基板の一部とは、前記配線基板(10、20)における前記リード端子(40)と接合される面に直交する方向における前記配線基板の全部ではなく途中までの部位であり、
前記溝(16、26)は、前記リード端子(40)における前記配線基板(10、20)との接合部にて、前記リード端子(40)の接合部形状に対応した形状に設けられており、
前記リード端子(40)における前記第1および第2の配線基板(10、20)との接続端部が、前記導電性接合部材(50)を介して前記溝(16、26)にはめ込まれることにより、前記第1および第2の配線基板(10、20)と前記リード端子(40)との接合がなされていることを特徴とする電子装置。 - 積層して配置された第1の配線基板(10)および第2の配線基板(20)と、
前記第1の配線基板(10)と前記第2の配線基板(20)との間に介在し、前記第1および第2の配線基板(10、20)の間を電気的に接続するリード端子(40)とを備え、
前記第1および第2の配線基板(10、20)の周辺部には、前記リード端子(40)との接合部に対応した位置に、溝(16、26)が形成されており、
前記リード端子(40)における前記第1および第2の配線基板(10、20)との接続端部が、前記導電性接合部材(50)を介して前記溝(16、26)にはめ込まれることにより、前記第1および第2の配線基板(10、20)と前記リード端子(40)との接合がなされており、
前記第1の配線基板(10)および前記第2の配線基板(20)は、複数の層(11〜14、21〜24)が積層されてなる積層基板であり、
前記溝(16、26)は、前記積層された複数の層(11〜14、21〜24)のうち
外面側に位置する層(14、24)の一部が除去されたものとして構成されていることを
特徴とする電子装置。 - 前記第1の配線基板(10)および前記第2の配線基板(20)は、複数の層(11〜14、21〜24)が積層されてなる積層基板であり、
前記溝(16、26)は、前記積層された複数の層(11〜14、21〜24)のうち外面側に位置する層(14、24)の一部が除去されたものとして構成されていることを特徴とする請求項1に記載の電子装置。 - 前記第1の配線基板(10)および前記第2の配線基板(20)の少なくとも一方における前記リード端子(40)との接続面には、端子(17)が設けられており、
前記リード端子(40)の一部は、前記端子(17)まで延びる延設部(42)となっており、
この延設部(42)と前記端子(17)とが電気的に接続されていることを特徴とする請求項1ないし3のいずれか1つに記載の電子装置。 - 前記第1の配線基板(10)と前記第2の配線基板(20)との間には、前記第1および前記第2の配線基板(10、20)と熱的に接続された放熱板(43)が介在しており、
この放熱板(43)を介して、前記両配線基板(10、20)の放熱が可能になっていることを特徴とする請求項1ないし3のいずれか1つに記載の電子装置。 - 第1の電子素子(30、31)が搭載された配線基板(10)と、
この配線基板(10)に導電性接合部材(50)を介して接合されたリード端子(40)とを備え、
前記配線基板(10)の周辺部には、前記リード端子(40)との接合部に対応した位置に、溝(16)が形成されており、
前記リード端子(40)における前記配線基板(10)との接続端部が、前記導電性接合部材(50)を介して前記溝(16)にはめ込まれることにより、前記配線基板(10)と前記リード端子(40)との接合がなされており、
前記リード端子(40)のうち前記配線基板(10)に接合された面とは反対側の面に、第2の電子素子(34)が搭載されており、
前記第2の電子素子(34)と前記配線基板(10)とは電気的に接続されていることを特徴とする電子装置。 - 前記第2の電子素子(34)と前記配線基板(10)とはボンディングワイヤ(35)を介して電気的に接続されていることを特徴とする請求項6に記載の電子装置。
- 前記配線基板(10)における前記リード端子(40)との接続面には、端子(17)が設けられており、
前記リード端子(40)の一部は、前記端子(17)まで延びる延設部(42)となっており、
この延設部(42)と前記端子(17)とが電気的に接続されていることを特徴とする請求項6に記載の電子装置。 - 前記配線基板(10)における前記リード端子(40)との接続面には、前記配線基板(10)と熱的に接続された放熱板(43)が介在しており、
この放熱板(43)を介して、前記配線基板(10)の放熱が可能になっていることを特徴とする請求項6に記載の電子装置。 - 前記配線基板(10)における前記リード端子(40)との接続面側には、ヒートシンク(45)が設けられており、
前記リード端子(40)は前記ヒートシンク(45)と熱的に接続されており、
前記ヒートシンク(45)の一部および前記リード端子(40)の一部が露出するように、前記第1の電子素子(30、31)、前記配線基板(10)、前記第2の電子素子(34)、前記リード端子(40)および前記ヒートシンク(45)が、モールド樹脂(60)により封止されていることを特徴とする請求項6に記載の電子装置。 - 前記リード端子(40)と前記ヒートシンク(45)とは一体に成形されたものであることを特徴とする請求項10に記載の電子装置。
- 前記配線基板(10)は複数の層(11〜14)が積層されてなる積層基板であり、
前記溝(16)は、前記積層された複数の層(11〜14)のうち外面側に位置する層(14)の一部が除去されたものとして構成されていることを特徴とする請求項7ないし11のいずれか1つに記載の電子装置。 - 第1の電子素子(30、31)が搭載された第1の配線基板(10)と、
この第1の配線基板(10)に導電性接合部材(50)を介して接合されたリード端子(40)とを備え、
前記第1の配線基板(10)の周辺部には、前記第1の配線基板(10)における前記リード端子(40)と接合される面側から当該配線基板の一部が除去されてなる溝(16)が形成されており、
前記第1の配線基板の一部とは、前記第1の配線基板(10)における前記リード端子(40)と接合される面に直交する方向における前記第1の配線基板の全部ではなく途中までの部位であり、
前記溝(16)は、前記リード端子(40)における前記第1の配線基板(10)との接合部にて、前記リード端子(40)の接合部形状に対応した形状に設けられており、
前記リード端子(40)における前記第1の配線基板(10)との接続端部が、前記導電性接合部材(50)を介して前記溝(16)にはめ込まれることにより、前記第1の配線基板(10)と前記リード端子(40)との接合がなされており、
前記リード端子(40)は、ケース(70)に支持されており、
前記ケース(70)は前記第1の配線基板(10)と対向する対向面(70a)を有しており、
前記ケース(70)の対向面(70a)に第2の配線基板(20)が設けられており、
前記第2の配線基板(20)に第2の電子素子(34)が搭載されており、
前記第1の配線基板(10)と前記第2の配線基板(20)とは前記リード端子(40)を介して電気的に接続されていることを特徴とする電子装置。 - 第1の電子素子(30、31)が搭載された第1の配線基板(10)と、
この第1の配線基板(10)に導電性接合部材(50)を介して接合されたリード端子(40)とを備え、
前記第1の配線基板(10)の周辺部には、前記リード端子(40)との接合部に対応した位置に、溝(16)が形成されており、
前記リード端子(40)における前記第1の配線基板(10)との接続端部が、前記導電性接合部材(50)を介して前記溝(16)にはめ込まれることにより、前記第1の配線基板(10)と前記リード端子(40)との接合がなされており、
前記リード端子(40)は、ケース(70)に支持されており、
前記ケース(70)は前記第1の配線基板(10)と対向する対向面(70a)を有しており、
前記ケース(70)の対向面(70a)に第2の配線基板(20)が設けられており、
前記第2の配線基板(20)に第2の電子素子(34)が搭載されており、
前記第1の配線基板(10)と前記第2の配線基板(20)とは前記リード端子(40)を介して電気的に接続されており、
前記第1の配線基板(10)は複数の層(11〜14)が積層されてなる積層基板であり、
前記溝(16)は、前記積層された複数の層(11〜14)のうち外面側に位置する層(11)の一部が除去されたものとして構成されていることを特徴とする電子装置。 - 前記ケース(70)はヒートシンク(71)を備えており、前記ヒートシンク(71)の一面が前記ケース(70)の対向面(70a)として構成されていることを特徴とする請求項13または14に記載の電子装置。
- 前記ケース(70)は樹脂製であり、前記リード端子(40)は前記ケース(70)にインサート成型されることにより一体化されて支持されていることを特徴とする請求項13ないし15のいずれか1つに記載の電子装置。
- 前記第2の配線基板(20)と前記リード端子(40)とはボンディングワイヤ(35)を介して電気的に接続されていることを特徴とする請求項13ないし16のいずれか1つに記載の電子装置。
- 前記第1の配線基板(10)における前記リード端子(40)との接続面には、端子(17)が設けられており、
前記リード端子(40)の一部は、前記端子(17)まで延びる延設部(42)となっており、
この延設部(42)と前記端子(17)とが電気的に接続されていることを特徴とする請求項13または14に記載の電子装置。 - 前記第1の配線基板(10)は複数の層(11〜14)が積層されてなる積層基板であり、
前記溝(16)は、前記積層された複数の層(11〜14)のうち外面側に位置する層(11)の一部が除去されたものとして構成されていることを特徴とする請求項13、15ないし18のいずれか1つに記載の電子装置。
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Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6856006B2 (en) * | 2002-03-28 | 2005-02-15 | Siliconix Taiwan Ltd | Encapsulation method and leadframe for leadless semiconductor packages |
CN104183591A (zh) * | 2005-07-01 | 2014-12-03 | 维税-希力康克斯公司 | 以单个贴装封装实现的完整功率管理系统 |
EP1909377B1 (en) * | 2006-01-16 | 2017-12-06 | Mitsubishi Electric Corporation | Drive circuit of motor and outdoor unit of air conditioner |
US7687882B2 (en) * | 2006-04-14 | 2010-03-30 | Allegro Microsystems, Inc. | Methods and apparatus for integrated circuit having multiple dies with at least one on chip capacitor |
US7573112B2 (en) * | 2006-04-14 | 2009-08-11 | Allegro Microsystems, Inc. | Methods and apparatus for sensor having capacitor on chip |
JP2007329387A (ja) * | 2006-06-09 | 2007-12-20 | Mitsubishi Electric Corp | 半導体装置 |
US20080013298A1 (en) | 2006-07-14 | 2008-01-17 | Nirmal Sharma | Methods and apparatus for passive attachment of components for integrated circuits |
US7659608B2 (en) * | 2006-09-15 | 2010-02-09 | Stats Chippac Ltd. | Stacked die semiconductor device having circuit tape |
JP4879276B2 (ja) * | 2006-10-24 | 2012-02-22 | パナソニック株式会社 | 3次元電子回路装置 |
JP4329884B2 (ja) * | 2007-11-20 | 2009-09-09 | 株式会社村田製作所 | 部品内蔵モジュール |
DE102008003790A1 (de) * | 2008-01-10 | 2009-07-16 | Robert Bosch Gmbh | Elektronisches Bauteil und Verfahren zur Herstellung des elektronischen Bauteils |
JP2009253152A (ja) * | 2008-04-09 | 2009-10-29 | Asmo Co Ltd | 樹脂封止型半導体装置 |
US8093670B2 (en) | 2008-07-24 | 2012-01-10 | Allegro Microsystems, Inc. | Methods and apparatus for integrated circuit having on chip capacitor with eddy current reductions |
ES2928766T3 (es) * | 2010-02-22 | 2022-11-22 | Swiss Tech Enterprise Gmbh | Procedimiento para producir un módulo semiconductor |
JP2012069764A (ja) | 2010-09-24 | 2012-04-05 | On Semiconductor Trading Ltd | 回路装置およびその製造方法 |
US20130105956A1 (en) * | 2011-10-31 | 2013-05-02 | Samsung Electro-Mechanics Co., Ltd. | Power module package and method for manufacturing the same |
US8629539B2 (en) | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9494660B2 (en) | 2012-03-20 | 2016-11-15 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9012267B2 (en) * | 2012-05-23 | 2015-04-21 | Intersil Americas LLC | Method of manufacturing a packaged circuit including a lead frame and a laminate substrate |
US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
DE102013219992A1 (de) * | 2013-10-02 | 2015-04-02 | Conti Temic Microelectronic Gmbh | Schaltungsvorrichtung und Verfahren zu deren Herstellung |
US20160021737A1 (en) * | 2014-07-17 | 2016-01-21 | Samsung Electro-Mechanics Co., Ltd. | Electric device module and method of manufacturing the same |
JP6345583B2 (ja) * | 2014-12-03 | 2018-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10411498B2 (en) | 2015-10-21 | 2019-09-10 | Allegro Microsystems, Llc | Apparatus and methods for extending sensor integrated circuit operation through a power disturbance |
US10636765B2 (en) | 2017-03-14 | 2020-04-28 | STATS ChipPAC Pte. Ltd. | System-in-package with double-sided molding |
US10636774B2 (en) | 2017-09-06 | 2020-04-28 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a 3D integrated system-in-package module |
US10978897B2 (en) | 2018-04-02 | 2021-04-13 | Allegro Microsystems, Llc | Systems and methods for suppressing undesirable voltage supply artifacts |
KR102163662B1 (ko) * | 2018-12-05 | 2020-10-08 | 현대오트론 주식회사 | 양면 냉각 파워 모듈 및 이의 제조방법 |
US11069605B2 (en) * | 2019-04-30 | 2021-07-20 | Advanced Semiconductor Engineering, Inc. | Wiring structure having low and high density stacked structures |
US11894347B2 (en) * | 2019-08-02 | 2024-02-06 | Semiconductor Components Industries, Llc | Low stress asymmetric dual side module |
US11469163B2 (en) * | 2019-08-02 | 2022-10-11 | Semiconductor Components Industries, Llc | Low stress asymmetric dual side module |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
JP7388912B2 (ja) * | 2019-12-23 | 2023-11-29 | ダイヤゼブラ電機株式会社 | イグナイタ |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH043453A (ja) | 1990-04-19 | 1992-01-08 | Ngk Insulators Ltd | 半導体装置および半導体装置へのリードフレームの取付方法 |
JPH05326817A (ja) | 1992-05-26 | 1993-12-10 | Hitachi Cable Ltd | マルチチップパッケージ |
JPH06334059A (ja) | 1993-05-20 | 1994-12-02 | Toppan Printing Co Ltd | 半導体搭載用基板及びその製造方法 |
US5540378A (en) * | 1993-09-27 | 1996-07-30 | Olin Corporation | Method for the assembly of an electronic package |
JPH08213531A (ja) | 1995-02-02 | 1996-08-20 | Hitachi Ltd | 半導体装置 |
KR100203934B1 (ko) * | 1996-02-17 | 1999-06-15 | 윤종용 | 패턴닝된 리드프레임을 이용한 멀티 칩 패키지 |
KR100285664B1 (ko) * | 1998-05-15 | 2001-06-01 | 박종섭 | 스택패키지및그제조방법 |
JP2000307027A (ja) | 1999-04-23 | 2000-11-02 | Shinko Electric Ind Co Ltd | 半導体装置とそれに用いるリードフレーム |
JP2001068582A (ja) | 1999-08-27 | 2001-03-16 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6559525B2 (en) * | 2000-01-13 | 2003-05-06 | Siliconware Precision Industries Co., Ltd. | Semiconductor package having heat sink at the outer surface |
JP2001210736A (ja) | 2000-01-27 | 2001-08-03 | Kyocera Corp | 電子部品搭載用基板およびその製造方法 |
US6545345B1 (en) * | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
US7652381B2 (en) * | 2003-11-13 | 2010-01-26 | Interconnect Portfolio Llc | Interconnect system without through-holes |
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