JPH0621328A - 半導体素子の実装方法 - Google Patents

半導体素子の実装方法

Info

Publication number
JPH0621328A
JPH0621328A JP4176397A JP17639792A JPH0621328A JP H0621328 A JPH0621328 A JP H0621328A JP 4176397 A JP4176397 A JP 4176397A JP 17639792 A JP17639792 A JP 17639792A JP H0621328 A JPH0621328 A JP H0621328A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor chip
bonding
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4176397A
Other languages
English (en)
Inventor
Ryoichi Fujimori
良一 藤森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4176397A priority Critical patent/JPH0621328A/ja
Publication of JPH0621328A publication Critical patent/JPH0621328A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 （修正有） 【構成】半導体素子１，２の回路構成面（以下、「能動
面」と呼ぶ。）上を利用して、二つの半導体素子の能動
面を向かい合うように、一方の半導体素子のワイヤーボ
ンディング部４を利用して接合する。 【効果】従来の実装方法に比べ半導体素子を高密度で実
装することが出来、かつ半導体素子と外部回路とを接続
する配線の本数を従来に比べ低減させることが出来、信
頼性を向上させる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体素子の実装方法
に関し、更に詳しくは、半導体素子の高密度実装に関す
るものである。
【０００２】
【従来の技術】従来の半導体素子の実装方法は、半導体
素子一つ一つを一つの部品と考えていたため、リードフ
レームに搭載しワイヤーボンディングによって半導体素
子とリードフレームの端子と電気的に接続し、収納容器
に封止することにより、一つの部品として回路基板に搭
載している。あるいは、回路基板上に直接半導体素子を
搭載しワイヤーボンディングまたはフェースダウンボン
ディングにより回路と電気的に接続している。しかし、
近年パーソナルコンピューター等に代表される回路基板
の軽薄短小の要求が非常に高くなっており、部品一つ一
つの占有するスペースについても考慮する必要が出てき
ているのが現状であるが、半導体素子の場合、素子その
ものが既に高集積化されているため外部回路との電気的
接続が大きな問題となっているため、回路が構成されて
いる面を利用しての高密度実装は余り考慮されていなか
った。
【０００３】
【発明が解決しようとする課題】本発明の目的は、半導
体素子上の回路が構成されている面を有効に利用して、
従来以上の高密度実装を実現することにある。
【０００４】
【課題を解決するための手段】上記目的は、半導体素子
上の回路が構成されている面（以下、「能動面」と呼
ぶ。）を利用して、二つの半導体素子の能動面を向かい
合うように接合することにより達成される。
【０００５】
【実施例】以下、本発明の一実施例を図１から図４によ
り説明する。
【０００６】図１は、回路基板上に半導体素子を直接実
装する実装方法（以下、「ＣＯＢ」と呼ぶ）に本発明を
実施した例の断面図である。また、図２は従来のＣＯＢ
の断面図である。
【０００７】従来のＣＯＢは図２のように、半導体素子
１が回路基板５に直接搭載され、金、銅等から成るボン
ディングワイヤー３によって半導体素子上の外部回路と
の電気的接続用の電極（以下、「パット」と呼ぶ。）と
回路基板５の回路パターン６に電気的に接続され、エポ
キシ等からなる封止樹脂７によって封止される。
【０００８】本発明では図１のごとく、ワイヤーボンデ
ィングにおいて半導体素子１のパット上に形成されるボ
ール４を、半導体素子をワイヤーボンディングによらず
パットを回路基板上の回路パターンに対向させて接続す
るフェースダウンボンディングやＴＡＢ方式で接続する
際に外部と接続しやすいように半導体素子のパットを突
起状にするバンプの代わりに使用して、他の半導体素子
２をフェースダウンボンディングにより半導体素子１と
接続する。
【０００９】本発明によれば、半導体素子の能動面上に
別の半導体素子が搭載され回路の集積度が増加すると共
に、半導体素子の電極を共通の回路パターンと接続する
場合配線の本数を従来に比べ低減させることが出来る。
【００１０】図３は、本発明の他の実施例の断面図を示
すものである。
【００１１】図３は図１と同様であるが、ワイヤーボン
ディングの方法が図１のボールボンディングに対して、
ウェッジボンディングを用いた方法である。この場合、
使用する半導体素子にバンプ８を予め構成しておく必要
があるが、ウェッジボンディングはボールボンディング
に比べ、ボンディング時のボンディングワイヤーの高さ
が低く抑えられるため、半導体素子１に半導体素子２を
搭載する際、ボンディングワイヤーが半導体素子２に接
触する可能性が更に少なくなるという利点を有する。
【００１２】図４は、通常のリードフレームを使用した
クワッドフラットパッケージ（以下、「ＱＦＰ」と呼
ぶ）に本発明を実施した例の断面図である。
【００１３】従来のＱＦＰの場合、一つの収納容器には
一つの半導体素子が収納されるだけであったが、本発明
により収納容器の構造を変更することなく、一つの収納
容器内に複数の半導体素子を収納することが可能とな
る。
【００１４】
【発明の効果】本発明によれば、従来の実装方法に比べ
半導体素子を高密度で実装することが出来、かつ半導体
素子と外部回路とを接続する配線の本数を従来に比べ低
減させることが出来、信頼性を向上させる効果がある
【図面の簡単な説明】
【図１】本発明をボールボンディングでのＣＯＢに用い
た実施例の断面図。
【図２】従来のＣＯＢの断面図。
【図３】本発明をウェッジボンディングでのＣＯＢの用
いた実施例の断面図。
【図４】本発明をＱＦＰに用いた実施例の断面図。
【符号の説明】
１ 半導体素子 ２ 半導体素子 ３ ボンディングワイヤー ４ ワイヤーボンディングにおけるボール部 ５ 回路基板 ６ 回路基板上の回路パターン ７ 封止樹脂 ８ 半導体素子の電極上に構成されたバンプ
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/60 ３１１ Ｑ 6918−4Ｍ

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 半導体素子の実装方法において、ワイヤ
    ーボンディングによる電気的接続を行った後、半導体素
    子の回路構成面が向かい合う状態で別の半導体素子を、
    同一ボンディングワイヤーに電気的に接続することを特
    徴とする半導体素子の実装方法。
JP4176397A 1992-07-03 1992-07-03 半導体素子の実装方法 Pending JPH0621328A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4176397A JPH0621328A (ja) 1992-07-03 1992-07-03 半導体素子の実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4176397A JPH0621328A (ja) 1992-07-03 1992-07-03 半導体素子の実装方法

Publications (1)

Publication Number Publication Date
JPH0621328A true JPH0621328A (ja) 1994-01-28

Family

ID=16012957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4176397A Pending JPH0621328A (ja) 1992-07-03 1992-07-03 半導体素子の実装方法

Country Status (1)

Country Link
JP (1) JPH0621328A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
KR20020020088A (ko) * 2000-09-07 2002-03-14 마이클 디. 오브라이언 반도체패키지 및 그 제조 방법
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
KR100384834B1 (ko) * 2001-03-30 2003-05-23 주식회사 하이닉스반도체 다중 기판 상에 형성되는 반도체 장치 및 그 제조 방법
US6977439B2 (en) 2002-03-21 2005-12-20 Samsung Electronics Co., Ltd. Semiconductor chip stack structure
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US7518223B2 (en) * 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
KR20020020088A (ko) * 2000-09-07 2002-03-14 마이클 디. 오브라이언 반도체패키지 및 그 제조 방법
KR100384834B1 (ko) * 2001-03-30 2003-05-23 주식회사 하이닉스반도체 다중 기판 상에 형성되는 반도체 장치 및 그 제조 방법
US7518223B2 (en) * 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6977439B2 (en) 2002-03-21 2005-12-20 Samsung Electronics Co., Ltd. Semiconductor chip stack structure

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