KR970024081A - 리드프레임을 적용한 칩 스케일 패키지(chip scale package) - Google Patents

리드프레임을 적용한 칩 스케일 패키지(chip scale package) Download PDF

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KR970024081A
KR970024081A KR1019950037832A KR19950037832A KR970024081A KR 970024081 A KR970024081 A KR 970024081A KR 1019950037832 A KR1019950037832 A KR 1019950037832A KR 19950037832 A KR19950037832 A KR 19950037832A KR 970024081 A KR970024081 A KR 970024081A
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South Korea
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chip
scale package
chip scale
bonding pads
lead frame
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KR1019950037832A
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English (en)
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KR0152555B1 (ko
Inventor
김일웅
김강수
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김광호
삼성전자 주식회사
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Priority to KR1019950037832A priority Critical patent/KR0152555B1/ko
Publication of KR970024081A publication Critical patent/KR970024081A/ko
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Publication of KR0152555B1 publication Critical patent/KR0152555B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 칩 스케일 패키지에 관한 것으로, 리드 프레임을 적용하여 칩 스케일 패키지를 실현하여 종래 패키지 제조 장치를 사용할 수 있기 때문에 제조 단가 측면에서 저렴한 패키지를 실현할 수 있으며, TSOP 수준의 신뢰도를 보장하는 동시에 상대적으로 고 난이도의 제조 기술이 요구되지 않는 특징을 갖는다.

Description

리드프레임을 적용한 칩 스케일 패키지(chip scale package)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 일 실시예에 의한 리드프레임을 적용한 센터 패드(center pad)를 갖는 칩 스케일 패키지를 나타내는 단면도.
제5도는 본 발명의 다른 실시예에 의한 리드프레임을 적용한 센터 패드를 갖는 칩 스케일 패키지를 나타내는 단면도.
제6도는 본 발명의 또 다른 실시예에 의한 리드프레임을 적용한 에지 패드(edge pad)를 갖는 칩 스케일 패키지를 나타내는 단면도.

Claims (7)

  1. 칩의 크기에 대응되는 크기를 갖는 칩 스케일 패키지(chip scale package)에 있어서, 복수개의 본딩 패드들을 갖는 칩과, 그 본딩 패드들에 각기 대응되어 전기적 연결된 내부리드들과, 그 내부리드들과 각기 일체형으로 대응된 외부리드들을 포함하는 리드프레임과; 상기 칩과 리드프레임의 내부리드들이 내재·봉지된 성형수지를 포함하며, 그 리드프레임의 외부리드들과 상기 칩의 본딩 패드들이 형성된 반대 면이 상기 성형 수지에 대하여 노출된 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지(chip scale package).
  2. 제1항에 있어서, 상기 본딩 패드들과 각기 대응되는 내부리드들의 전기적 연결이 본딩 와이어에 의해 각기 전기적 연결된 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지.
  3. 제1항에 있어서, 상기 칩의 하부면의 본딩 패드들이 형성되지 않은 부분과 상기 내부리드들이 폴리이미드 테이프에 의해 접착되어 리드프레임이 지지되는 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지.
  4. 제1항에 있어서, 상기 칩의 하부면의 본딩 패드들이 형성되지 않은 부분과 상기 내부리드들이 각기 본딩 와이어에 의해 리드프레임이 지지되는 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지.
  5. 제1항에 있어서, 상기 성형수지가 액상 수지인 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지.
  6. 제1항에 있어서, 상기 칩의 본딩 패드들이 칩의 중앙 부분에 형성된 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지.
  7. 제1항에 있어서, 상기 칩의 본딩 패드들이 칩의 가장자리 부분에 형성된 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950037832A 1995-10-28 1995-10-28 리드프레임을 적용한 칩 스케일 패키지 KR0152555B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950037832A KR0152555B1 (ko) 1995-10-28 1995-10-28 리드프레임을 적용한 칩 스케일 패키지

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037832A KR0152555B1 (ko) 1995-10-28 1995-10-28 리드프레임을 적용한 칩 스케일 패키지

Publications (2)

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KR970024081A true KR970024081A (ko) 1997-05-30
KR0152555B1 KR0152555B1 (ko) 1998-10-01

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KR1019950037832A KR0152555B1 (ko) 1995-10-28 1995-10-28 리드프레임을 적용한 칩 스케일 패키지

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