KR960019621A - 수지 봉합형 반도체장치의 구조 - Google Patents

수지 봉합형 반도체장치의 구조 Download PDF

Info

Publication number
KR960019621A
KR960019621A KR1019950036671A KR19950036671A KR960019621A KR 960019621 A KR960019621 A KR 960019621A KR 1019950036671 A KR1019950036671 A KR 1019950036671A KR 19950036671 A KR19950036671 A KR 19950036671A KR 960019621 A KR960019621 A KR 960019621A
Authority
KR
South Korea
Prior art keywords
semiconductor element
opposite
chip support
resin
bonded
Prior art date
Application number
KR1019950036671A
Other languages
English (en)
Other versions
KR100366111B1 (ko
Inventor
에쓰오 야마다
야스시 시라이시
히로시 가와노
신지 오오우찌
히데까즈 나스
Original Assignee
사와무라 시꼬
오끼덴끼고오교 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사와무라 시꼬, 오끼덴끼고오교 가부시끼가이샤 filed Critical 사와무라 시꼬
Publication of KR960019621A publication Critical patent/KR960019621A/ko
Application granted granted Critical
Publication of KR100366111B1 publication Critical patent/KR100366111B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

[목적]
종래의 박형의 수지봉합형 반도체장치에서는, 다이패드의 측면과 몰드수지의 사이에 박리가 발생하기 쉬우며, 더욱 진행하면 몰드수지에 균열이 발생한다는 문제도 있었다.
[해결수단]
반도체 소자(1)의 금선(4)이 접속되는 편면(1a)측에, 금선(4)이 접속되는 부분을 피하여 접착 테이프(2)로 면접착된 칩 서포트(3)를 형성함과 동시에, 반도체 소자(1)의 평면(1a)과 반대측에 위치하는 다른면(1b) 및, 칩 서포트(3)의 반도체 소자(1)에 접착된 면(3a)과 반대측의 면(3b)을 각각 노출시켜서 몰드수지(6)로 봉합한다.

Description

수지 봉합형 반도체장치의 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예 1로서 나타내는 수지봉합형 반도체장치의 종단측면도,
제2도는 본 발명의 실시예 2로서 나타내는 수지봉합형 반도체장치의 요부 평면도,
제3도는 제2도의 선 A-A에 따른 확대 종단 측면도.

Claims (12)

  1. 표면에 금선이 접속되는 반도체 소자와, 상기 반도체 소자의 금선이 접속되는 부분을 피하여 고착되는 칩 서포트와, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 이면 및, 상기 칩 서포트의 상기 반도체 소자에 고착된 면과 반대측의 면을 각각 노출시켜서 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  2. 표면에 금선이 접속되는 반도체 소자와, 상기 반도체 소자의 금선이 접속되는 부분을 피하여 고착되는 한 쌍의 칩 서포트와, 상기 한 쌍의 칩 서포트와, 상기 반도체장치를 고착하는 상기 한 쌍의 칩 서포트 사이에 주입되는 접착제와, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 이면 및, 상기 칩 서포트의 상기 반도체 소자에 고착된 면과 반대측의 면을 각각 노출시켜서 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  3. 제2항에 있어서, 상기 칩 서포트를 수평부와 수직부를 일체로 형성하여 단면이 대락 L자 상으로 형성되고, 각 칩 서포트의 수평부의 선단을 각각 대향하게 맞추어서 배치하여 이루어지는 수지봉합형 반도체장치의 구조.
  4. 표면에 금선이 접속되는 반도체 소자와, 상기 반도체 소자의 금선이 접속되는 부분을 피하여 복수의 방향으로부터 신장하여 배치되고, 선단에 상하방향으로 관통된 접착제 주입용 구멍을 갖는 칩 서포트로서, 상기 접착제 주입용 구멍으로부터 주입된 접착제에 의해 상기 반도체 소자와 접착하는 상기 칩 서포트와, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 이면 및, 상기 칩 서포트의 상기 반도체 소자에 접착된 면과 반대측의 면을 각각 노출시켜서 봉합되는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  5. 표면에 금선이 접속되는 반도체 소자와, 상기 표면과 반대의 이면측에 배치되는 한 쌍이상의 다이패드와, 이 한 쌍의 다이패드 사이에 주입되는 상기 다이패드 사이 및, 상기 다이패드 사이와 상기 반도체 소자를 각각 접속시킴과 동시에 상기 다이패드의 상기 반도체 소자에 접착된 면과 반대측의 면을 노출시켜서 수지봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  6. 반도체 소자와, 상기 반도체 소자의 표면에 배치되는 선단에 접착제 주입용 구멍을 가진 리드와, 상기 반도체 소자와 상기 리드의 사이를 접착시키는 상기 접착제 주입용 구멍으로부터 주입되는 접착제와, 상기 반도체 소자와, 상기 리드를 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  7. 표면에 금선이 접속되는 반도체 소자와, 상기 반도체 소자의 표면에 상기 금선이 접속되는 부분을 피하여 접속되고, 이 접착되는 면과 반대측의 면에 돌기부를 갖는 칩 서포트와, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 이면 및, 상기 칩 서포트의 상기 돌기부의 선단을 각각 노출시켜 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  8. 표면에 금선이 접속되는 반도체 소자와, 상기 금선이 접속되는 부분을 피하여 탄력성의 접착층을 통하여 면접착된 칩 서포트와, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 이면 및, 상기 칩 서포트의 상기 반도체 소자에 접착된 면과 반대측의 면을 각각 노출시켜서 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  9. 표면에 본딩패드를 갖는 반도체 소자와, 상기 본딩패드와 전기적으로 접속되는 내부리드와, 상기 반도체 소자의 표면의 상기 본딩패드를 피하여 접착되는 금속판과, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 다른면 및, 상기 금속판의 상기 반도체 소자에 접착된 면과 반대측의 면을 각각 노출시켜서 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  10. 제9항에 있어서, 상기 금속판은, 방열성의 금속판인 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  11. 제10항에 있어서, 상기 방열성의 금속판은, Cu, Al, Cu/W로부터 선택된 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
  12. 표면에 본딩패드를 갖는 반도체 소자와, 상기 본딩패드와 전기적으로 접속되는 내부리드와, 상기 반도체 소자의 표면의 상기 본딩패드를 피하여 접착되는 상기 내부리드 보다도 얇은 칩 서포트와, 상기 반도체 소자의 상기 표면과 반대측에 위치하는 다른면 및, 상기 칩 서포트의 상기 반도체 소자에 접착된 면과 반대측의 면을 각각 노출시켜서 봉합하는 몰드수지를 포함하는 것을 특징으로 하는 수지봉합형 반도체장치의 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950036671A 1994-11-08 1995-10-23 수지봉합형 반도체장치의 구조 KR100366111B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-273262 1994-11-08
JP27326294 1994-11-08

Publications (2)

Publication Number Publication Date
KR960019621A true KR960019621A (ko) 1996-06-17
KR100366111B1 KR100366111B1 (ko) 2003-03-06

Family

ID=17525385

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950036671A KR100366111B1 (ko) 1994-11-08 1995-10-23 수지봉합형 반도체장치의 구조

Country Status (4)

Country Link
US (1) US6002181A (ko)
EP (1) EP0712159A3 (ko)
KR (1) KR100366111B1 (ko)
TW (1) TW357443B (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG60099A1 (en) * 1996-08-16 1999-02-22 Sony Corp Semiconductor package and manufacturing method of lead frame
US6127724A (en) * 1996-10-31 2000-10-03 Tessera, Inc. Packaged microelectronic elements with enhanced thermal conduction
US5920112A (en) * 1998-04-07 1999-07-06 Micro Networks Corporation Circuit including a corral for containing a protective coating, and method of making same
JP2000077435A (ja) 1998-08-31 2000-03-14 Hitachi Ltd 半導体装置及びその製造方法
FR2788882A1 (fr) * 1999-01-27 2000-07-28 Schlumberger Systems & Service Dispositif a circuits integres, module electronique pour carte a puce utilisant le dispositif et procede de fabrication dudit dispositif
TW429494B (en) * 1999-11-08 2001-04-11 Siliconware Precision Industries Co Ltd Quad flat non-leaded package
US6559525B2 (en) * 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
TW518729B (en) * 2001-09-04 2003-01-21 Siliconware Precision Industries Co Ltd Quad flat non-leaded semiconductor package structure and manufacturing process
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
TWI334638B (en) * 2005-12-30 2010-12-11 Ind Tech Res Inst Structure and process of chip package
US7911040B2 (en) * 2007-12-27 2011-03-22 Stats Chippac Ltd. Integrated circuit package with improved connections
KR20160038364A (ko) * 2014-09-30 2016-04-07 현대모비스 주식회사 비절연 타입의 전력 반도체 모듈 및 이의 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0775253B2 (ja) * 1987-06-30 1995-08-09 株式会社日立製作所 半導体装置およびその製造方法
JP2660732B2 (ja) * 1989-01-09 1997-10-08 株式会社日立製作所 半導体装置
JPH02260558A (ja) * 1989-03-31 1990-10-23 Nec Corp 半導体装置のリードフレーム
US5157478A (en) * 1989-04-19 1992-10-20 Mitsubishi Denki Kabushiki Kaisha Tape automated bonding packaged semiconductor device incorporating a heat sink
JP2875334B2 (ja) * 1990-04-06 1999-03-31 株式会社日立製作所 半導体装置
JPH04245462A (ja) * 1991-01-30 1992-09-02 Hitachi Ltd 半導体集積回路装置およびその製造方法
US5173764A (en) * 1991-04-08 1992-12-22 Motorola, Inc. Semiconductor device having a particular lid means and encapsulant to reduce die stress
JPH04317360A (ja) * 1991-04-16 1992-11-09 Sony Corp 樹脂封止型半導体装置
JP2970060B2 (ja) * 1991-06-06 1999-11-02 日本電気株式会社 樹脂封止型半導体装置用リードフレーム
JPH05315526A (ja) * 1992-05-08 1993-11-26 Hitachi Ltd 半導体装置
US5387554A (en) * 1992-09-10 1995-02-07 Vlsi Technology, Inc. Apparatus and method for thermally coupling a heat sink to a lead frame
JP2824175B2 (ja) * 1992-09-17 1998-11-11 シャープ株式会社 半導体装置及びその製造方法
JP2874483B2 (ja) * 1992-10-05 1999-03-24 松下電器産業株式会社 半導体装置

Also Published As

Publication number Publication date
US6002181A (en) 1999-12-14
EP0712159A3 (en) 1997-03-26
EP0712159A2 (en) 1996-05-15
TW357443B (en) 1999-05-01
KR100366111B1 (ko) 2003-03-06

Similar Documents

Publication Publication Date Title
KR960012449A (ko) 반도체장치
KR920010853A (ko) 수지봉지형 반도체장치
KR860007735A (ko) 반도체장치 및 그 제조방법과 그 제조방법에 사용하는 리이드 프레임
KR950001998A (ko) 소형 다이 패드를 갖고 있는 반도체 디바이스 및 이의 제조 방법
KR950030323A (ko) 반도체 장치와 반도체 장치의 생산방법 및 반도체 모듈
KR960005972A (ko) 수지 밀폐형 반도체 장치 및 그 제조 방법
KR960019621A (ko) 수지 봉합형 반도체장치의 구조
KR960019688A (ko) 디바이스 에지에서 기계적 스트레스를 줄이기 위한 개별 영역 리드 프레임 주조법 또는 하프 에칭법
JPH08321521A (ja) 樹脂封止型半導体装置及びその製造方法
US5652184A (en) Method of manufacturing a thin semiconductor package having many pins and likely to dissipate heat
US5874783A (en) Semiconductor device having the inner end of connector leads displaced onto the surface of semiconductor chip
KR960039449A (ko) 반도체 패키지, 리드프레임 및 제조방법
JP2908350B2 (ja) 半導体装置
KR970077602A (ko) 칩접착부가 일체형으로 형성된 타이바를 갖는 패드리스 리드프레임과 이를 이용한 반도체 칩 패키지
KR940008060A (ko) 반도체 집적회로 장치
KR950002001A (ko) 반도체 패키지
JPH0739237Y2 (ja) 半導体装置
KR970024081A (ko) 리드프레임을 적용한 칩 스케일 패키지(chip scale package)
KR870000753A (ko) 수지봉합형 반도체장치
JPH0888310A (ja) 樹脂封止半導体装置
KR970013280A (ko) 더미 패드(dummy pad)를 갖는 리드프레임 및 그를 이용한 칩 패키지
KR0142756B1 (ko) 칩홀딩 리드 온 칩타입 반도체 패키지
KR970008505A (ko) 반도체 패키지
KR970023917A (ko) 와이어의 단락을 방지하기 위한 반도체 패키지
KR970053758A (ko) 반도체 패키지의 구조

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091210

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee