CN1099131C - 栅阵列球半导体封装 - Google Patents

栅阵列球半导体封装 Download PDF

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CN1099131C
CN1099131C CN97112488A CN97112488A CN1099131C CN 1099131 C CN1099131 C CN 1099131C CN 97112488 A CN97112488 A CN 97112488A CN 97112488 A CN97112488 A CN 97112488A CN 1099131 C CN1099131 C CN 1099131C
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lead
wire
pad
encapsulation
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CN1187029A (zh
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李柱华
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SK Hynix Inc
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LG Semicon Co Ltd
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Abstract

一种栅阵列(BGA)半导体封装包括：垫片；借助绝缘粘结剂贴在垫片表面上的半导体芯片；围绕垫片外围部分设置的数根第一引线，各引线间有恒定间距，每根第一引线的一端向下弯曲；贴在第一引线下表面上的数根第二引线；电连接半导体芯片和第一引线的数根导线；按使每根第二引线的下表面部分外露的方式密封整个结构的模制部件；分别贴在每根第二引线的暴露下表面上的焊球。

Description

栅阵列球半导体封装
技术领域
本发明涉及一种栅阵列球(此后称为BGA)半导体封装，特别涉及一种用引线框代替基板的改进BGA半导体封装。
背景技术
近来，在方形扁平封装(此后称为QFP)中，人们的注意力已集中在一种多管脚封装上，相应于这种多管脚趋势，外引线的宽度正在变得更窄，引线间距正在变小。结果，在把引线表面安装于印刷电路板(PCB)上时引线容易弯曲，所以很难将封装与PCB对准，且很难控制焊料量。因此，为了适应多管脚趋势和克服QFP的这些缺点，已研制出并使用了BGA半导体封装，由于BGA半导体封装没有外引线，代之以焊球作外引线，所以可以克服QFP的缺点。
图1是展示根据常规技术的BGA半导体封装结构的纵剖图，该BGA半导体封装包括：有数根小型布线形式的内引线(未示出)的基板1；用粘结剂3粘贴在基板1上表面上的半导体芯片2；数根电连接半导体芯片2与置于基板中的每根内引线一端的导线4；所形成的用于用环氧树脂化合物密封基板1上表面预定区域的模制造部件5，以此方式包封半导体芯片2和连线4；及数个形成于基板1下表面上的焊球6，焊球6与设置于基板1中的每根内引线的另一端连接。
然而，常规BGA半导体封装使用其中设有内引线的基板1，由于通过叠置导电层和绝缘层并进行腐蚀制造基板1，所以基板1有较高的吸湿率。因此，影响了半导体封装的可靠性，基板内的汽压可能导致分层和龟裂，这一切的发生是不可避免的。因此，限制了半导体封装可靠性的增强。而且，由于环氧树脂模制部件5只在基板1上表面上形成，所以容易在基板1和模制部件5的界面处发生分层。
发明内容
因此，本发明的目的是提供一种用引线框代替基板的改进BGA半导体封装，以避免由基板引起的分层和剥离(脱落)。
为了实现上述目的，本发明提供一种栅阵列球(BGA)半导体封装，该封装包括：垫片；借助绝缘粘结剂贴在垫片下表面上的半导体芯片；围绕垫片外围部分设置的数根第一引线，各引线间有恒定间距，每根引线的一端向下弯曲；贴在第一引线下表面上的相应数根第二引线；电连接半导体芯片和第一引线的数根导线；按使每根第二引线的下表面部分外露的方式密封整个结构的模制部件；及分别贴在每根第二引线的暴露下表面上的焊球。
附图说明
借助以下给出的详细说明及说明性的附图，可以更充分地理解本发明，但它们并不是对本发明的限制，其中：
图1是展示根据常规技术的BGA半导体封装结构的纵剖图；
图2A和2B分别是根据本发明的第一引线框的平面图和纵剖图；
图3是根据本发明的第二引线框的平面图；
图4是根据本发明第一实施例的BGA半导体封装的纵剖图；
图5是根据本发明第二实施例的BGA半导体封装的纵剖图；
图6是根据本发明第三实施例的BGA半导体封装的纵剖图；
图7是根据本发明第四实施例的BGA半导体封装的纵剖图；
图8是根据本发明第五实施例的BGA半导体封装的纵剖图；
图9是根据本发明第六实施例的BGA半导体封装的纵剖图。
具体实施方式
下面结合各附图详细说明本发明的BGA半导体封装。
图2A和2B分别是根据本发明的第一引线框的平面图和纵剖图。如图所示，有一容纳半导体芯片(未示出)的矩形垫片11。围绕垫片11的外围部分设置数根第一引线13，每根第一引线的一端向下弯曲，各引线间有预定间距。每根第一引线13的另一端与引线支撑条15相连，由此得以支撑。另外，垫片11通过拉杆17与引线支撑条15相连，由此得以支撑。参考数字19表示的是第一引线框10的接合部件，对应于图3所示的第二引线框20的接合部件25，这将在以后说明，在进行封装时利用根据本发明的第一引线框。
图3是根据本发明的第二引线框的平面图。形成数根对应于图2中每根第一引线的第二引线21。每根第二引线21的一端形成为圆形，其另一端与引线支撑条23相连。规则排列的第二引线21有交替形成的短引线21a和长引线21b，以使以圆形形成的每根第二引线21的端部彼此不交叠。参考数字25表示的是接合部件。
图4是根据本发明第一实施例的BGA半导体封装的纵剖图。如图所示，提供垫片11，围绕垫片11的外围设置数根一端向下弯曲的第一引线13，使各引线间有预定的间距。数根相应的第二引线21分别贴在第一引线13的下表面上。垫片11的上表面上，用绝缘粘结剂30粘贴着半导体芯片40，半导体芯片40和每根引线13借助数根导线50电连接。形成模制部件60，以密封整个结构，使每根第二引线21的下表面暴露于外，焊球70附着在每根第二引线21的暴露下表面上。更详细地说，焊球70附着在图3中第二引线21形成为圆形的端部。涂敷第二引线除焊球70附着部分外的下表面，以防止焊球70流散。
图5是根据本发明第二实施例的BGA半导体封装的纵剖图。如该图所示，半导体芯片40利用绝缘粘结剂30粘贴在垫片的下表面上，半导体芯片40和每根第一引线13借助垫片11下的数根导线50电连接。其余结构与图4的本发明第一实施例相同。即，在图4中，半导体芯片40贴在垫片11的上表面上，但图5中，半导体芯片40贴在垫片11的下表面上。图5示出的本发明的结构可以降低完成后半导体封装的高度。
图6是根据本发明第三实施例的BGA半导体封装的纵剖图。如该图所示，形成模制部件60，以密封整个结构，使垫片11的上表面暴露于外。该结构具有容易把半导体芯片40产生的热散发到外部的作用。
图7是根据本发明第四实施例的BGA半导体封装的纵剖图。如该图所示，提供垫片91，在垫片91上并围绕其外围部分设置数根扁平第一引线92，使这些引线间有预定间距，数根一端向下弯曲的相应第二引线93分别附着在第一引线92的下表面部分上，垫片91的上表面上，利用绝缘粘结剂94粘贴着半导体芯片95，半导体芯片95和每根第一引线92借助数根导线96电连接。形成模制部件97，以密封整个结构，使第二引线93的向下弯曲部分的下表面暴露于外，焊球98附着在每根第二引线93的暴露下表面上。
图8是根据本发明第五实施例的BGA半导体封装的纵剖图。如该图所示，半导体芯片95利用绝缘粘结剂94粘贴在垫片91的下表面上，半导体芯片95和每根第一引线92借助垫片下的导线96电连接。其余结构与图7所示本发明第四实施例的结构相同。即，在图7中，半导体芯片95贴在垫片91的上表面上，而在图8中，半导体芯片95贴在垫片91的下表面上。与图7的结构相比，图8所示本发明的结构可以降低完成后半导体封装的高度。
图9是根据本发明第六实施例的BGA半导体封装的纵剖图。如该图所示，形成模制部件97，以密封整个结构，使垫片91的上表面暴露于外。与图8相比，图9所示结构具有更容易把半导体芯片95产生的热量散发到外部的作用。
下面将结合图2-5详细说明根据本发明的用于半导体封装的制造方法。
首先，用绝缘粘结剂30作介质，把半导体芯片40粘贴在图2中第一引线框10的垫片11的上或下表面上。由导电金属线50电连接半导体芯片40和数根第一引线13。然后，定位形成于图3中第二引线框20的上表面上的接合部件25，使之相应地与形成于第一引线框10的下表面上的接合部件19接触，通过热压使第一和第二引线框10、20贴在一起。这里，用锡(Sn)镀敷有形成于其中的第一引线13的第一引线框10的接合部件19，并用金(Au)镀敷第二引线框20的接合部件25。接着，为保护整个结构，在包括半导体芯片40、连线50、第一引线13和第二引线21的区域中模制环氧树脂模制化合物，从而形成模制部件60。这里，要注意的是，模制第二引线21的下表面，使之通过模制部件60的下表面暴露出来。然后，把焊球70贴附在每根第二引线21的暴露下表面的圆形端部上，然后，为防止焊球70流散，镀敷(或涂敷)第二引线21除贴附着焊球部分外的下表面。最后，通过修整去除暴露于模制部件60外的第一和第二引线框10、20的每根引线支撑条15、23，从而完成根据本发明的BGA半导体封装。
如上所述，根据本发明的BGA半导体封装有以下作用，即，通过使用小面积的引线框代替基板，可以防止由于采用其中设置了小型布线的基板所导致的分层和剥离(脱落)。
尽管为了说明而公开了本发明的优选实施例，但在不脱离本发明所附权利要求书限定的发明精神和范围的情况下，本领域的普通技术人员可以做出各种改型、附加和替换。

Claims (10)

1.一种栅阵列球(BGA)半导体封装，该封装包括：
垫片；
借助绝缘粘结剂贴在垫片下表面上的半导体芯片；
围绕垫片外围部分设置的数根第一引线，各引线间有恒定间距，每根引线的一端向下弯曲；
贴在第一引线下表面上的相应数根第二引线；
电连接半导体芯片和第一引线的数根导线；
按使每根第二引线的下表面部分外露的方式密封整个结构的模制部件；及
分别贴在每根第二引线的暴露下表面上的焊球。
2.根据权利要求1的封装，其特征在于，按使垫片的上表面外露的方式形成模制部件。
3.根据权利要求1的封装，其特征在于，每根第二引线的一端形成为圆形。
4.根据权利要求3的封装，其特征在于，焊球贴在第二引线的圆形端。
5.根据权利要求1的封装，其特征在于，第二引线包括交替形成的长和短第二引线。
6.一种BGA半导体封装，该封装包括：
垫片；
围绕垫片的外围部分设置的数根第一引线，各引线间有规则的间距；
分别贴在每根第一引线部分下表面上的数根相应第二引线，其一端向下弯曲；
借助绝缘粘结剂贴在垫片下表面上的半导体芯片；
电连接半导体芯片和每根第一引线的数根导线；
按仅使每根第二引线向下弯曲部分的下表面外露的方式密封整个结构的模制部件；
贴在每根第二引线的暴露下表面上的焊球。
7.根据权利要求6的封装，其特征在于，按使垫片的上表面外露的方式形成模制部件。
8.根据权利要求6的封装，其特征在于，每根第二引线的一端形成为圆形。
9.根据权利要求8的封装，其特征在于，焊球贴在第二引线的圆形端。
10.根据权利要求6的封装，其特征在于，第二引线包括交替形成的长和短第二引线。
CN97112488A 1996-12-28 1997-06-17 栅阵列球半导体封装 Expired - Fee Related CN1099131C (zh)

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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3685947B2 (ja) * 1999-03-15 2005-08-24 新光電気工業株式会社 半導体装置及びその製造方法
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US6483180B1 (en) * 1999-12-23 2002-11-19 National Semiconductor Corporation Lead frame design for burr-free singulation of molded array packages
JP2002118222A (ja) 2000-10-10 2002-04-19 Rohm Co Ltd 半導体装置
US6677667B1 (en) 2000-11-28 2004-01-13 National Semiconductor Corporation Leadless leadframe package design that provides a greater structural integrity
US6933174B1 (en) 2000-11-28 2005-08-23 National Semiconductor Corporation Leadless leadframe package design that provides a greater structural integrity
US20030178719A1 (en) * 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
SG105544A1 (en) * 2002-04-19 2004-08-27 Micron Technology Inc Ultrathin leadframe bga circuit package
KR20040017625A (ko) * 2002-08-22 2004-02-27 주식회사 칩팩코리아 플립 칩 패키지
US8859339B2 (en) 2008-07-09 2014-10-14 Freescale Semiconductor, Inc. Mold chase
CN102130085B (zh) * 2010-01-18 2013-03-13 矽品精密工业股份有限公司 具电性连接结构的半导体封装件及其制法
US20130249071A1 (en) * 2010-09-07 2013-09-26 Jinzhong Yao Semiconductor device and method of assembling same
JP6357371B2 (ja) * 2014-07-09 2018-07-11 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
CN105719975B (zh) 2014-08-15 2019-01-08 恩智浦美国有限公司 半导体封装的浮动模制工具

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801765A (en) * 1986-01-06 1989-01-31 American Telephone And Telegraph Company, At&T Bell Laboratories Electronic component package using multi-level lead frames
US5581122A (en) * 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157480A (en) * 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
KR930006868A (ko) * 1991-09-11 1993-04-22 문정환 반도체 패키지
TW272311B (zh) * 1994-01-12 1996-03-11 At & T Corp
US5578871A (en) * 1994-10-18 1996-11-26 Fierkens; Richard H. J. Integrated circuit package and method of making the same
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
US5594234A (en) * 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
JP3332308B2 (ja) * 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
KR0179803B1 (ko) * 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
KR100187715B1 (ko) * 1996-08-19 1999-06-01 윤종용 리드 프레임을 이용한 칩 스케일 패키지 제조 방법
US5825628A (en) * 1996-10-03 1998-10-20 International Business Machines Corporation Electronic package with enhanced pad design

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801765A (en) * 1986-01-06 1989-01-31 American Telephone And Telegraph Company, At&T Bell Laboratories Electronic component package using multi-level lead frames
US5581122A (en) * 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits

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US6201294B1 (en) 2001-03-13
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