CN1213176A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1213176A
CN1213176A CN98120024A CN98120024A CN1213176A CN 1213176 A CN1213176 A CN 1213176A CN 98120024 A CN98120024 A CN 98120024A CN 98120024 A CN98120024 A CN 98120024A CN 1213176 A CN1213176 A CN 1213176A
Authority
CN
China
Prior art keywords
semiconductor device
solder ball
semiconductor chip
conductive component
bonding line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN98120024A
Other languages
English (en)
Inventor
木村直人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1213176A publication Critical patent/CN1213176A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

本发明的目的是在不使用引线情况下可以连接形成在半导体芯片上的焊盘和焊料球,其中焊料球与外部电路相通,增加了键合的自由度,并使半导体器件小型化。在其表面上提供有导电部件的绝缘柱粘附于半导体芯片上。半导体芯片上的焊盘经过键合线与绝缘柱的导电部件相连,焊料球与导电部件连接。

Description

半导体器件及其制造方法
本发明涉及半导体器件及其制造方法，特别涉及芯片上引线(lead orchip)(LOC)型模制球栅阵列(BGA)半导体器件及其制造方法。
在常规的LOC型BGA半导体器件中，引线经过绝缘胶带粘附到半导体芯片上，形成在半导体芯片上的引线和焊盘通过键合线连接。但是，在半导体芯片小型化或提供多个管脚时，相邻引线间的间隔变窄，从而不可能通过导线键保装置连接引线和焊盘。因而，强烈地希望发展一种半导体器件，其中引线和焊盘可以不用引线连接，因为使用引线将妨碍半导体器件的小型化。
因此，本发明的一个目的是解决这些问题并提供一种半导体器件，其中不必使用引线以与最近的趋势，即半导体芯片被小型化，其管脚数量增加相符合。
本发明另一目的是解决这些问题，并提供制造半导体器件的方法，其中不必使用引线以与最近的趋势，即半导体芯片小型化，其管脚(pin)数量增加相符合。
根据本发明的第一特点，半导体器件包括：
绝缘部件，部分地用导电部件覆盖并粘附到半导体芯片上；
键合线，用于将形成在半导体芯片上的焊盘与导电部件相连接；和
与导电部件相连接的外部端子。
根据本发明的第二特点，制造半导体器件的方法包括以下步骤：
将被导电部件部分覆盖的绝缘部件粘附到半导体芯片上；
通过键合线将形成在半导体芯片上的焊盘与导电部件连接；
将导电部件连接到外部端子。
下面参照附图说明本发明，其中：
图1是表示常规半导体器件的透视图；
图2A和2B分别是用于解释本发明第一优选实施例的顶视图和截面图；
图3A-3E是用于解释本发明第一优选实例中使用的绝缘树脂柱(shafe)的制造工艺的侧视图；
图4A和4B分别是用于解释本发明第一优选实施例的制造工艺的顶视图和截面图；
图5A-5D是用于解释本发明第一优选实施例的制造工艺的截面图；
图6A-6B分别是用于解释本发明第二优选实施例的透视图和截面图；
图7是用于解释本发明第三优选实施例的截面图。
在说明本发明优选实施例中的半导体器件和其制造方法之前，先解释上述常规半导体器件。
如图1的透视图中所示，在常规的LOC型BAG阵列半导体器件中，引线19通过绝缘胶带17与半导体芯片1的上表面相连，键合线3的两端与形成在半导体芯片1上的焊盘2和引线19的端部相连。包括键合线3的半导体芯片1通过模制树脂4密封后，在引线19上设置焊料球10，并以此方法完成了半导体器件。起始于焊盘2的键合线3向上弯曲，并且其端部斜着与引线19键合。
在上述常规半导体器件中，当半导体芯片是小尺寸的或提供多个管脚时，引线19与引线框架20相连，相邻引线之间的间隔变得很小，在键合时很难插入导线键保装置的毛细管，因此不可能进行导线键保。
下面参照附图解释本发明的实施例。图2A和2B分别表示根据本发明第一优选实施例的半导体器件的顶视图和截面图，其中使用绝缘树脂柱代替引线，绝缘树脂柱7的表面用低熔点的多个焊料镀层(solder-ploted loyers)(导电部件)8覆盖。在图2A中，半导体芯片1通过银膏6与引线框架20的岛状物5连接，其中银膏是作为粘合剂。起始于形成在半导体芯片1上的焊盘2的键合线3与焊料镀层8相连，此后半导体芯片1通过密封树脂密封。然后，在对应于绝缘柱7上的焊料镀层8的部分上设置焊料球10并与之连接。
带有焊料镀层的绝缘树脂柱的制造如图3A-3E的截面图中所示，图3A-3E表示下面的工艺步骤。首先，如图3A所示，绝缘树脂形成圆柱形结构的柱7。柱的截面可以是方形。接着，如图3B所示，在没有形成焊料镀层的部分施加保护膜(resist)11。再次，如图3C所示，通过汽化在基底金属涂层部分12上涂敷作为镀层的基底金属的Pd。再其次，如图3D所示，通过无电镀敷(electroless plating)形成焊料镀层13，如图3E所示，去掉保护膜11。然后，留下焊料镀层13。
下面参照图4A-4B和图5A-5B解释本发明的半导体器件的制造方法。如图4A的顶视图和图4B的截面图中所示，位于引线框架20的岛状物5两侧(左和右)上的悬引线14分别提供有支撑板15，该板垂直于悬浮引线14。半导体芯片1通过银膏6与岛状物5相连。
然后，如图5A所示，通过图3A-3E中的工艺制造的绝缘树脂柱7用绝缘粘合剂9粘附到半导体芯片1上。而且，如图5B所示，键合线3经过绝缘树脂柱7从半导体芯片1上的焊盘2伸展到支撑板15，而且焊盘2和焊料镀层13与键合线3连接。然后如图5C所示，键合线3在焊料镀层13的边缘被削断，并移走支撑板15。接着如图5D所示，具有与之相连接的键合线3的半导体芯片1用树脂4密封，在焊料球10设置在对应于焊料镀层13的部分上并与之连接。
如上所述，根据本发明的实例，不用引线通过制成位于焊盘2和焊料球10之间的、提供有焊料镀层13的绝缘树脂柱7可以互连焊盘2和焊料球10，并小型化半导体器件。
图6A和6B分别表示本发明第二优选实施例的透视图和截面图，其中使用绝缘带代替引线。在本例中，使用了导电带焊盘18与之粘附的绝缘带17代替图2A和2B中所示的绝缘树脂柱7。如图6A所示，绝缘带17粘附到半导体芯片1上，并且键合线3与粘附到绝缘带17上的带焊盘18键合。键合线3的剩余部分形成管脚16，管脚16接近垂直于带焊盘18。然后，具有管脚16和键合线3的半导体芯片1除了管脚16的圆周边外用密封树脂4密封。然后在对应管脚16的部分设置焊料球10，并与之连接。
图7表示本发明第三实施例的截面图，其中使用带焊盘代替引线。在本例中，设有使用图6A和6B所示的管脚16，焊料球10直接设置在带焊盘18上并与之连接。
根据第二和第三实例，不用引线，通过制成位于焊盘和焊料球之间的、提供有带焊盘18的绝缘带17可以直接将键合线3连接到作为外部端子的焊料球10上。
如上所述，根据本发明的实例，不使用妨碍常规半导体器件小型的引线，可以将形成在半导体芯片上的焊盘连接到与外部电路相通的焊料球上，从而键合的自由度增加了，半导体器件可以小型化了。
虽然为全面和清楚公开，本发明关于具体实例已经描述了，但是所附的权利要求书不限于此，而是应该被看作所有修改和改变结构的具体体现，而这些修改和改变是可以由本领域普通技术人员做出的。

Claims (15)

1．一种半导体器件，包括：
绝缘部件，部分地被导电部件覆盖并粘附到半导体芯片上；
键合线，用于连接形成在所述半导体芯片上的焊盘和所述导电部件；和
与所述导电部件连接的外部端子。
2．如权利要求1的半导体器件，其特征在于，所述绝缘部件是绝缘树脂柱，所述导电部件是焊料镀层。
3．如权利要求2的半导体器件，其特征在于，所述外部端子是焊料球，并形成球栅阵列。
4．如权利要求1的半导体器件，其特征在于，所述绝缘部件是绝缘带，所述导电部件是导电焊盘。
5．如权利要求4的半导体器件，其特征在于，所述外部端子是焊料球，并形成球栅阵列。
6．如权利要求5的半导体器件，其特征在于所述焊料球经过导电管脚与所述导电焊盘相连。
7．如权利要求5的半导体器件，其特征在于，所述焊料球直接与所述导电焊盘连接。
8．如权利要求4的半导体器件，其特征在于，所述导电焊盘的表面镀有焊料。
9．如权利要求1的半导体器件，其特征在于，所述半导体芯片、所述键合线、所述绝缘部件和所述导电部件用树脂密封。
10．一种制造半导体器件的方法，包括以下步骤：
将部分被导电部件覆盖的绝缘部件粘附到半导体芯片上；
用键合线连接形成在所述半导体芯片上的焊盘和所述导电部件；
使所述导电层与外部端子相连。
11．如权利要求10的方法，其中所述绝缘部件是绝缘树脂柱，所述导电部件是焊料镀层，所述外部端子是焊料球。
12．如权利要求11的方法，还包括以下步骤：
用树脂密封所述半导体芯片，所述键合线、所述绝缘树脂柱和所述焊料镀层；和
连接所述焊料球和所述焊料镀层，以形成球栅阵列。
13．如权利要求10的方法，其中所述绝缘部件是绝缘带，所述导电部件是带焊盘，所述外部端子是焊料球。
14．如权利要求13的方法，其中连接所述带焊盘和所述焊料球的所述步骤包括下列步骤：
在连接所述键合线和所述带焊盘后，将所述键合线的剩余部分制成垂直于所述带焊盘的管脚；
使所述管脚与所述焊料球相连。
15．如权利要求13的方法，还包括以下步骤：
用树脂密封所述半导体芯片、所述键合线、所述绝缘带和所述带焊盘；和
连接所述焊料球和所述带焊盘，以形成球栅阵列。
CN98120024A 1997-09-22 1998-09-22 半导体器件及其制造方法 Pending CN1213176A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP256988/97 1997-09-22
JP9256988A JP2954108B2 (ja) 1997-09-22 1997-09-22 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
CN1213176A true CN1213176A (zh) 1999-04-07

Family

ID=17300172

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98120024A Pending CN1213176A (zh) 1997-09-22 1998-09-22 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US6011306A (zh)
JP (1) JP2954108B2 (zh)
CN (1) CN1213176A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303992B1 (en) * 1999-07-06 2001-10-16 Visteon Global Technologies, Inc. Interposer for mounting semiconductor dice on substrates
US6888256B2 (en) * 2001-10-31 2005-05-03 Infineon Technologies Ag Compliant relief wafer level packaging
US7071421B2 (en) * 2003-08-29 2006-07-04 Micron Technology, Inc. Stacked microfeature devices and associated methods

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
JPH07169872A (ja) * 1993-12-13 1995-07-04 Fujitsu Ltd 半導体装置及びその製造方法
US5834339A (en) * 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5770479A (en) * 1996-01-11 1998-06-23 Micron Technology, Inc. Bonding support for leads-over-chip process

Also Published As

Publication number Publication date
JP2954108B2 (ja) 1999-09-27
US6011306A (en) 2000-01-04
JPH1197472A (ja) 1999-04-09

Similar Documents

Publication Publication Date Title
JP2858246B2 (ja) 半導体パッケージ
US6228683B1 (en) High density leaded ball-grid array package
US7148080B2 (en) Method for joining lead frames in a package assembly, method for forming a chip stack package, and a chip stack package
CN1041254C (zh) 三维结构的半导体器件
US7247944B2 (en) Connector assembly
US5834836A (en) Multi-layer bottom lead package
CN1099131C (zh) 栅阵列球半导体封装
KR100804341B1 (ko) 반도체장치 및 그 제조방법
US20090102029A1 (en) Semiconductor Device
US5559305A (en) Semiconductor package having adjacently arranged semiconductor chips
CN1076873C (zh) 集成芯片的封装及其所使用的连接部件
CN1213176A (zh) 半导体器件及其制造方法
KR100390466B1 (ko) 멀티칩 모듈 반도체패키지
JP3466354B2 (ja) 半導体装置
KR100481927B1 (ko) 반도체패키지및그제조방법
JP2636808B2 (ja) 半導体装置
JPH09252020A (ja) 半導体装置およびその製造方法
JPH03265148A (ja) 半導体装置及びその製造方法
KR100381839B1 (ko) 반도체패키지
KR20030025481A (ko) 플립칩 반도체패키지 및 그의 제조방법
JP2000323641A (ja) リードフレームおよびその製造方法
JPH02180061A (ja) リードフレームおよび半導体装置
JPH07153867A (ja) 半導体装置およびその製造方法
JPH08111494A (ja) 面実装型半導体装置
JPH03119755A (ja) リードフレームの製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Owner name: NEC ELECTRONICS TAIWAN LTD.

Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD.

Effective date: 20030328

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20030328

Address after: Kawasaki, Kanagawa, Japan

Applicant after: NEC Corp.

Address before: Tokyo, Japan

Applicant before: NEC Corp.

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication