CN1169033A - 一种改进的半导体封装 - Google Patents

一种改进的半导体封装 Download PDF

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CN1169033A
CN1169033A CN96120807A CN96120807A CN1169033A CN 1169033 A CN1169033 A CN 1169033A CN 96120807 A CN96120807 A CN 96120807A CN 96120807 A CN96120807 A CN 96120807A CN 1169033 A CN1169033 A CN 1169033A
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chip
lead
connection pads
lamella
installation
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CN1071495C (zh
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车基本
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SK Hynix Inc
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LG Semicon Co Ltd
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Abstract

本发明的半导体封装包括有形成于其中的金属布线图形的安装片层，和粘结在安装片层的至少一个表面上的半导体芯片。多根连线电连接形成在半导体芯片上的多个芯片焊盘与安装片层。每根引线包括接合到安装片层的表面上的第一引线，和至少部分暴露的第二引线。导电粘结剂粘结安装片层与第一引线，模制树脂构成封装的管壳。与常规封装相比，上述结构的半导体封装有不同的优点。即，可使占据面积比最小化和防止引线的有害弯曲。而且，由于半导体芯片可以粘结在安装片层的两个表面上，所以可获得集成半导体封装。

Description

一种改进的半导体封装
本发明涉及一种半导体封装，特别涉及一种改进的底部引线半导体封装。
图1是表示外引线为J形的SOJ(小型J引线)半导体封装结构的剖面图。常规半导体封装包括：由粘结剂7粘接在安装片2上的半导体芯片1；有多根已与半导体芯片1引线接合的内引线3和由内引线3延伸出的外引线的引线结构。多根金属连线5电连接芯片1和引线结构的内引线3，模制树脂6通过包封包括半导体芯片1和内引线3的预定区域构成半导体封装的管座。
当常规半导体安装在基片上时，由于外引线从半导体封装管壳侧边突出来，所以封装所占面积变得较大。所占面积比变得较高；安装率下降；外引线会发生有害的弯曲。而且，由于在一个封装中只能安装一个芯片，所以很难获得多芯片封装，且很难封装中心焊盘型半导体芯片。
一种至少可部分实现本发明的芯片封装包括：有多个芯片焊盘的第一芯片；有第一和第二表面的安装片层，该安装片层有多个第一连接焊盘、多个第二连接焊盘、和使相应的第一和第二连接焊盘彼此耦合的导电介质；把第一芯片安装到安装片层的第一表面上且电接合相应的芯片焊盘与相应的第一连接焊盘的装置；有第一和第二表面的多根引线；把相应的第二连接焊盘电安装到相应的引线的第一表面的预定部位的装置；及封装第一芯片、安装片层、连接装置、多根引线和安装装置的模制树脂。
一种至少也能部分实现本发明的安装片层用于有多个芯片焊盘的芯片的封装，该安装片层包括：用于安装芯片的区域；多个与芯片焊盘电连接的第一连接焊盘；多个与封装的引线电连接的第二连接焊盘；及使相应的第一和第二连接焊盘彼此耦合的导电介质。
下面的说明会部分地表现出本发明的其它优点、目的和其它特点，而且本领域的技术人员通过下面的试验或通过实践本发明会更清楚本发明的这些优点、目的和特点。所附权利要求书所特别指出的方案，可以实现本发明的目的和取得本发明的优点。
下面将参照附图详细说明本发明，各附图中相同的标记表示相同的部件。
图1是常规SOJ(小型J引线)半导体封装的纵剖图；
图2是本发明的一个实施例的底部引线半导体封装的纵剖图；
图3是接合在图2中的安装片层上的半导体芯片的平面图；
图4是本发明的另一个实施例的底部引线半导体封装的纵剖图；
图5是本发明的再一个实施例的底部引线半导体封装的纵剖图；
图6是通过接合引线接合在图5中的安装片层上的半导体芯片的平面图。
如图2所示，用双面绝缘带或膏状的粘结剂21，分别把半导体芯片20a、20b粘结在安装片层10的上下表面的近乎中心区域，该安装片层有形成于其中的电路布线图形。半导体芯片20a、20b的芯片焊盘与安装片层10的连接焊盘分别彼此连接。
多根引线包括多根内引线22a和底部引线22b。用导电粘结剂23粘结引线框架20的内引线22a与在安装片层10的底表面侧边形成的引线连接焊盘13。这里用双面带或膏状粘结剂作导电粘结剂23。底部引线22b从内引线22a向下延伸预定深度。
用模制树脂25模制包括已引线接合的半导体芯片20a、20b和引线22的预定区域，从而制成半导体封装管壳。为了把半导体芯片20a、20b的电信号输送到外部，在完成封装时，使底部引线22b暴露于封装管壳的底表面，并安装在基片上(未示出)。
图3是引线接合后粘结在图2中的安装片层10上的半导体芯片的平面图。把半导体芯片20粘结到安装片层10的安装片11上。用连线24连接芯片20的多个芯片焊盘20-1与多个引线连接焊盘12。引线连接焊盘13围绕安装片层10形成，以通过形成于安装片层10中的金属布线图形分别与引线连接焊盘12连接。在矩形间隔处焊盘12和引线连接焊盘13之间的空间中形成孔14。
图4是本发明的另一个实施例的底部引线半导体封装的纵剖图。用多个导电凸起分别把半导体芯片40a、40b接合到安装片层30的上下表面的中心部位，其中所述安装片层30有形成于其中的的电路布线图形。与形成于安装片层30上引线连接焊盘12类似，多个形成于半导体芯片40a、40b上的芯片焊盘与多个块状焊盘彼此接合。
另外，引线框架42包括多根内引线42a和底部引线42b，且引线框架42的内引线42a通过导电粘结剂43粘接到形成于安装片层30的底表面侧边的引线连接焊盘上。引线框架42的上述结构与图2中的引线框架22相同。这里用双面带或膏状导电粘结剂作导电粘结剂43。
用模制树脂45模制包括半导体芯片、安装片层30和引线42的预定区域，从而制成封装管壳。为了把半导体芯片40a、40b的电信号输送到外部，在完成封装时，使引线42的底部引线42b暴露于封装管壳的底表面，并安装在基片上。
在图4中的半导体封装结构中，半导体芯片40a、40b的芯片焊盘与安装片层30的突起的连接焊盘通过导电凸起44彼此电连接。电通道短于图2中通过连线24彼此连接的电通道，所以可增强电特性。通过改变安装片层30的金属布线图形的设计，可更容易地封装有形成于其中心和侧边部位的芯片焊盘的整个半导体芯片。即，可根据形成于安装片层30上的突起的焊盘是否位于中心或侧边，来选择地封装侧边焊盘型或中心焊盘型半导体芯片。
图5是本发明的再一个实施例的底部引线半导体封装的纵剖图。用双面绝缘带或膏状粘结剂61，把中心焊盘型半导体芯片60粘结在安装片层50底表面的中心部位，所述安装片层50中有电路布线图形，和形成于其中心部位的第一孔54。通过安装片层50的第一孔54，暴露形成于半导体芯片中心部位的芯片焊盘60-1。安装片层50的连接焊盘51和芯片焊盘60-1分别通过导电连线64彼此连接。
引线62包括多根内引线62a和底部引线62b，且内引线62a通过导电粘结剂63粘接到形成于安装片层50底表面侧边的引线连接焊盘52上。这里用双面带或糊型粘结剂作导电粘结剂63。引线62的上述结构与图2和4中的引线22、42相同。
用模制树脂65模制包括已引线接合了的半导体芯片60、引线框架62和安装片层50的预定区域，从而制成封装管壳。为了把半导体芯片60的电信号输出到外部，在完成封装时，使底部引线62b暴露于封装管壳的底表面，并安装在基片上(未示出)。
图6是已引线接合到在图5中的安装片层50上的半导体芯片60的平面图。如该图所示，在安装片层50的近乎中心部位形成第一孔54，以便在把有在中心部位的中心焊盘60-1的半导体芯片粘结到安装片层50上时，暴露芯片焊盘60-1，且围绕第一孔54，借助连线64，把形成于芯片60上的多个芯片焊盘60-1接合到多个连接焊盘51上。绕安装片层50的边缘，形成引线连接焊盘52，以便使之通过粘结剂63与内引线62a粘结。另外，在矩形间隔处键合焊盘51和引线连接焊盘52之间的空间中形成第二孔53。显然，芯片焊盘60-1可通过焊料块或其它合适的连接装置与连接焊盘51连接。
如上所述，关于本发明的底部引线半导体封装，由于封装靠其底表面上暴露的底部引线安装在基片上，所以可以使封装占据基片的面积比最小化，还可以防止引线的有害弯曲。另外，由于半导体芯片粘结在安装片层的两个表面上，并封装，所以可获得集成半导体封装，并且可以封装在中心或侧边部位有芯片焊盘的整个半导体芯片。
上述实施例仅是例证性的，并不限制本发明，可以容易地将本发明的方案用于此线暴露于封装的底表面或上表面的其它类型的封装。例如，本发明可以用于公开于美国专利5363279、5428248、5326932、5444301和5471088中的封装，这些申请一般归于与本申请相同的受让者，通过引证可把它们所公开的内容结合进本申请。而且，本发明公开了用模制树脂完全包封的芯片。显然，本发明也可用于不完全包封半导体芯片的封装，即，模制树脂封装或模制半导体芯片。在上述实施例中，为了便于用附图说明本发明，称各表面为上和下表面或上和底表面。显然，对表面的引用取决于封装的取向。本发明的说明只是说明性的，并不限制要求书的范围。本领域的技术人员可以对本发明作出许多替换、改型和变化。

Claims (21)

1.一种芯片封装，包括：
有多个芯片焊盘的第一芯片；
有第一和第二表面的安装片层，所述安装片层有多个第一连接焊盘、多个第二连接焊盘、和使相应的第一和第二连接焊盘彼此耦合的导电介质；
把所述第一芯片附加到所述安装片层的所述第一表面上、且电耦合相应的芯片焊盘与相应的第一连接焊盘的装置；
有第一和第二表面的多根引线；
把相应的第二连接焊盘电安装到相应引线的第一表面的第一预定部位的装置；及
封装所述第一芯片、安装片层、连接装置、多根引线和安装装置的模制树脂。
2.如权利要求1所述的芯片封装，其特征在于：暴露所述多根引线的所述第二表面的第一预定部分。
3.如权利要求2所述的芯片封装，其特征在于：所述多根引线的所述第二表面的第一预定部分基本与所述模制树脂的外表面共面。
4.如权利要求1所述的芯片封装，其特征在于：所述模制管壳包封所述第一芯片、安装片层、连接装置、安装装置及所述多根引线的预定部分。
5.如权利要求1所述的芯片封装，其特征在于：用模制树脂部分模制第一芯片，暴露所述第一芯片的至少一个表面。
6.如权利要求1所述的芯片封装，其特征在于：所述多根引线的每一根皆包括第一引线和第二引线，在将第一连接引线端弄弯曲后，所述第二引线与所述第一连接引线平行。
7.如权利要求6所述的芯片封装，其特征在于：暴露第二引线的第二表面。
8.如权利要求6所述的芯片封装，其特征在于：所述安装装置耦合所述安装片层的所述二表面与第一引线的所述第一表面。
9.如权利要求1所述的芯片封装，其特征在于：所述导电介质是埋在所述安装片层中的金属布线。
10.如权利要求1所述的芯片封装，其特征在于：所述连接装置包括：
绝缘粘结所述第一芯片与所述安装片层的所述第一表面的粘结剂；及
电耦合所述多个芯片焊盘与所述第一连接焊盘的多根连线。
11.如权利要求1所述的芯片封装，其特征在于：所述连接装置包括使所述多个芯片焊盘与所述第一连接焊盘耦合的多个导电凸起。
12.如权利要求10所述的芯片封装，其特征在于：所述安装片层还包括一开口，所述多个芯片焊盘是位于所述芯片表面的中心区的中心芯片焊盘，把所述芯片连接到所述安装片层，以便通过所述安装片的所述开口暴露中心芯片焊盘，从而允许所述连线电耦合所述中心芯片焊盘与所述第一连接焊盘。
13.如权利要求1所述的芯片封装，其特征在于：所述第二连接焊盘基本围绕所述第一连接焊盘。
14.如权利要求1所述的芯片封装还包括第二芯片，其特征在于：所述连接装置把所述第二芯片连接到所述安装片层的第二表面上，且电耦合相应的第二芯片的芯片焊盘与相应的第一连接焊盘。
15.如权利要求1所述的芯片封装，其特征在于：所述安装装置是一导电双面带或糊型粘结剂。
16.一种安装片层，用于有多个芯片焊盘的芯片的封装，包括：
安装芯片的区域；
多个与所述芯片焊盘电连接的第一连接焊盘；
多个与封装引线电连接的第二连接焊盘；及
使相应的第一和第二连接焊盘彼此耦合的导电介质。
17.如权利要求16所述的安装片层，其特征在于：所述区域包括一开口，以便暴露中心芯片焊盘，使之与所述多个第一连接焊盘连接。
18.如权利要求16所述的安装片层，其特征在于：所述导电介质是形成于安装片层中的多根布线。
19.如权利要求16所述的安装片层，其特征在于：基本围绕所述区域形成所述多个第一连接焊盘。
20.如权利要求19所述的安装片层，其特征在于：所述第二连接焊盘基本围绕所述多个第一连接焊盘。
21.如权利要求20所述的安装片层，还包括形成于矩形间隔处所述多个第一和第二连接焊盘间的多个孔。
CN96120807A 1996-06-14 1996-11-27 安装片层及使用该安装片层的芯片封装 Expired - Lifetime CN1071495C (zh)

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US5861668A (en) 1999-01-19
KR980006167A (ko) 1998-03-30
CN1071495C (zh) 2001-09-19
JP2881733B2 (ja) 1999-04-12
KR0179924B1 (ko) 1999-03-20
JPH1084069A (ja) 1998-03-31

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