KR0157857B1 - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR0157857B1
KR0157857B1 KR1019920000421A KR920000421A KR0157857B1 KR 0157857 B1 KR0157857 B1 KR 0157857B1 KR 1019920000421 A KR1019920000421 A KR 1019920000421A KR 920000421 A KR920000421 A KR 920000421A KR 0157857 B1 KR0157857 B1 KR 0157857B1
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South Korea
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semiconductor package
chip
lead
semiconductor
package according
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KR1019920000421A
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KR930017154A (ko
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유진성
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문정환
엘지반도체주식회사
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Priority to KR1019920000421A priority Critical patent/KR0157857B1/ko
Priority to TW81108390A priority patent/TW262583B/zh
Priority to US07/964,718 priority patent/US5326932A/en
Priority to JP29615992A priority patent/JP3110174B2/ja
Priority to DE19924238438 priority patent/DE4238438A1/de
Publication of KR930017154A publication Critical patent/KR930017154A/ko
Application granted granted Critical
Publication of KR0157857B1 publication Critical patent/KR0157857B1/ko

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Abstract

본 발명은 반도체 패키지에 관한 것으로, 세라믹이나 알루미늄 재질로 형성된 베이스의 캐비티에 접착제를 이용하여 반도체 칩을 부착고정하고, 다이어태치된 반도체 칩의 상측에 절연성의 폴리이미드계 필름이나 비도전성의 세라믹 재질의 사각판으로 이루어진 리드(lid)를 부착고정하여 인너리드 본딩방식으로 상기 칩의 본드 패드와, 리드의 솔더범프를 전기적으로 접속연결한 후 상기 각 솔더범프의 상측에 도전성의 금속으로 컨택트부를 각각 형성하여 구성한 것이다.
이와같이된 본 발명에 의한 반도체 패키지는 리드프레임 및 금속와이어가 제거되므로 제조공정이 간소화되고 구조가 간단하여 제조원가 절감 및 생산성 향상을 기할 수 있고, 패키지의 경박 단소화 및 고밀도 실장을 실현할 수 있는 효과가 있다.

Description

반도체 패키지
제1도 및 제2도는 종래의 일반적인 반도체 패키지의 구성을 보인 단면도 및 부분 절결 사시도.
제3도 및 제4도는 종래의 반도체 패키지에 있어서, 패키지의 경박단소화를 위하여 리드프레임의 패들을 제거한 구조의 반도체 패키지를 보인 도면으로서, 제3도는 COL(Chip On Lead)타입 반도체 패키지의 구조를 보인 부분 절결 사시도. 제4도는 LOC(Lead On Chip)타입 반도체 패키지의 구조를 보인 부분 절결 사시도.
제5도 및 제6도는 본 발명에 의한 반도체 패키지의 바람직한 실시예를 보인 도면으로서, 제5도는 절연성의 폴리이미드 필름을 사용한 경우의 패키지 구조를 보인 단면도. 제6도는 비전도성의 세라믹 리드를 사용한 경우의 패키지 구조를 보인 단면도.
* 도면의 주요부분에 대한 부호의 설명
11 : 반도체 칩(Chip) 11a : 본드 패드(bond pad)
12 : 베이스(base) 12a : 캐비티(cavity)
13 : 접착제 14 : 리드(lid)
14' : 폴리이미드계 필름 14 : 세라믹 사각판
14a : 솔더범프(solder bump) 15 : 금속컨택트부
본 발명은 반도체 패키지 구조에 관한 것으로, 특히 리드프레임 및 금속와이어를 제거하여 제조공정 및 구조를 간소화하고, 아이씨(IC)의 다핀화구조에 적용가능토록 함과 아울러 패키지의 경박단소화 및 고밀도 실장에 적합하도록 한 반도체 패키지에 관한 것이다.
종래의 일반적인 반도체 패키지는 제1도 및 제2도에 도시한 바와같이 리드프레임의 패들(1)위에 접착제(2)를 이용하여 반도체칩(3)을 부착고정하고, 그 칩(3)의 상측 양변부에 형성된 복수개의 본드 패드(3a)와 리드프레임의 인너리드(4)들을 금속와이어(5)를 이용하여 전기적으로 접속 연결하며, 에폭시 몰딩 컴파운드(6)로 밀페한 후, 외부로 돌출된 리드프레임의 아웃리드(7)들을 소정의 모양으로 절곡형성한 구성으로 되어있다.
또한, 최근에는 더욱 경박단소화되는 패키지 추세에 따라 제3도 및 제4도에 도시한 바와같이 리드프레임의 패들을 제거하고 리드프렘임의 인너리드(4)에 절연테이프(8)를 이용하여 반도체 칩(3)을 부착고정한 후, 상기와 같은 제조공정으로 제작한 구조의 반도체 패키지가 알려지고 있는 바, 통상 제3도에 도시한 바와같이 리드(4)위에 칩(3)이 올려지는 구조의 COL(Chip On Lead)타입 반도체 패키지와, 제4도에 도시한 바와같이 리드(4)가 칩(3)위에 올려지는 구조의 LOC(Lead On Chip)타입 반도체 패키지가 알려지고 있다. 도면에서 제1도의 일반적인 패키지와 동일한 부분에 대해서는 동일부호를 부여하였고 그의 상세한 설명은 생략하였다.
그러나, 상기한 바와같은 종래에 제공된 여러종류의 반도체 패키지는 모두 리드프레임을 이용하여 제작하는 구조로서 인너리드(4)가 배치되어야 하고 금속와이어(5)의 접합이 필요하므로 패키지의 실장면적이 커져야 하는 결함이 있었고, 또한, 구조상의 구성물질(Meterial)들에 따른 트러블(Trouble)발생이 많은 것이었다.
즉, 구성물질(실리콘, 접착제, 금속성의 리드프레임 및 에폭시 몰딩 컴파운드 등)들간의 열팽창계수 차이로 인한 패키지 깨짐 불량이라든지 또는, 금속와이어(5)접합에 따른 칩의 전기적인 특성저하 및 와이어 본딩의 난점 등 제조상의 어려움이 있는 것이었다.
이를 감안하여 창안한 본 발명의 목적은 리드프레임을 제거함과 아울러 금속와이어 접합을 배제하고 칩의 본드 패드 부분에 외부와의 접촉을 위한 컨텍트부를 형성하여 단자로 이용함으로써 제조공정을 간소화하고, 경박단소화 및 여러 트러블을 제거한 반도체 패키지를 제공함에 있다.
이와같은 본 발명의 목적은 세라믹 또는 알루미늄(Al)재질로 형성된 베이스의 캐비티에 복수개의 본드 패드가 구비된 반도체 칩을 접착제를 이용하여 부착 고정하고 그 상측에 상기 반도체 칩의 본드 패드와 접촉되도록 복수개의 솔더범프가 구비된 장방형의 비전도성 리드(lid)를 부착한 후 상기 솔더범프의 상측에 알루미늄이나 알루미늄 합금류의 금속 컨택트부를 형성하여 구성함을 특징으로 하는 반도체 패키지를 제공함으로써 달성되는것이다.
이와같이된 본 발명에 의한 반도체 패키지는 리드프레임과 금속와이어가 제거되므로 제조공정이 단순해지고, 각 구성물질들간의 열팽창계수 차이로 발생되는 트러블을 줄일 수 있으며 패키지의 경박단소화 및 IC의 다핀 구조에 유리하게 적용할 수 있는 등의 여러 장점이 있는 것이다.
이하에서는 이러한 본 발명을 첨부한 도면에 의거하여 보다 상세히 설명하겠다.
제5도 및 제6도에 도시한 바와같이 본 발명에 의한 반도체 패키지는 양변부에 복수개의 본드 패드(11a)가 구비된 반도체 칩(11)과, 그 반도체 칩(11)이 안착되는 캐비티(12a)가 구비된 세라믹, 또는 알루미늄 재질의 베이스(12)와, 그 베이스(12)의 캐비티(12a)에 상기 반도체 칩(11)을 부착고정하기 위한 접착제(13)와, 다이어태치된 반도체 칩(11)의 상측에 부착되며, 상기 칩(11)의 본드 패드(11a)와 접촉되는 다수개의 솔더범프(14a)가 구비된 비전도성 재질의 리드(lid)(14)와, 그 리드(14)의 솔더범프(14a)에 형성되는 다수개의 금속컨택트부(15)로 구성되어 있다.
상기 접착제(13)는 폴리이미드(Poloyimide)계 또는 에폭시(Epoxy)계의 절연테이프를 사용할 수 있고 그외에 어떠한 종류의 접착제를 사용하여도 무방하다.
또한, 상기 리드(14)는 제5도에 도시한 바와같이 절연성의 폴리이미드계 필름(14')를 사용할 수 있고 제6도에 도시한 바와같이 비전도성의 세라믹 재질의 사각판(14)을 사용할 수도 있으며, 그 외에도 비전도성의 어떠한 물질은 사용하여도 무방하나 이를 꼭 한정할 필요는 없다.
또한, 상기 금속컨택트부(15)의 재질은 알루미늄이나 알루미늄 합금류의 어떠한 전도성 재질을 사용하여도 무방하다.
이와같이 구성된 본 발명에 의한 반도체 패키지는 먼저, 베이스(12)의 캐비티(12a)에 접착제(13)를 이용하여 반도체 칩(11)을 부착고정하고, 그 상측에 리드(14)를 부착하여 종래의 인너리드 본딩방식으로 칩(11)의 본드 패드(11a)와 상기 리드(14)의 솔더범프(14a)를 전기적으로 접속연결한 후, 그 솔더범프(14a)의 상측에 도전성의 금속으로 금속컨택트부(15)를 형성하는 순서로 제작하며, 이와같이 제작된 반도체 패키지는 도시되지 않은 인쇄회로기판의 메탈라인에 상기 컨택트부(15)를 일치시켜 표면 실장법으로 장착하는 것이다.
이상에서 상세히 설명한 바와같이 본 발명에 의한 반도체 패키지는 리드프레임 및 금속와이어가 제거되므로 종래에 비해 패키지 제조공정이 간소화되어 제조원가 절감 및 생산성 향상을 기할 수 있고, 각 구성물질들간의 열팽창 계수차이로 발생되는 여러 트러블을 줄일 수 있으며, 패키지의 경박단소화 및 IC의 다핀구조에 유리하게 적용할 수 있을 뿐만아니라 고밀도 실장을 실현할 수 있는 등의 여러 효과가 있는 것이다.

Claims (6)

  1. 양변부에 복수개의 본드 패드(11a)가 구비된 반도체 칩(11)과 그 반도체 칩(11)이 안착되는 캐비티(12a)가 구비된 베이스(12)와, 그 베이스(12)의 캐비티(12a)에 상기 반도체 칩(11)을 부착고정하기 위한 접착제(13)와, 다이어태치된 상기 칩(11)의 상측에 부착 고정되며 그 칩(11)의 본드 패드(11a)와 접촉되는 다수개의 솔더범프(14a)가 구비된 비전도성 재질의 리드(14)와, 그 리드(14)의 각 솔더범프(14a)에 형성되는 다수개의 금속컨택트부(15)로 구비하여서 된 반도체 패키지.
  2. 제1항에 있어서, 상기 베이스(12)는 세라믹 또는, 알류미늄 재질인 것을 특징으로 하는 반도체 패키지.
  3. 제1항에 있어서, 상기 접착제(13)는 폴리이미드계 또는, 에폭시계인 것을 특징으로 하는 반도체 패키지.
  4. 제1항에 있어서, 상기 리드(14)는 절연성의 폴리이미드계 필름(14)에 다수개의 솔더범프(14a)를 형성한 것임을 특징으로 하는 반도체 패키지.
  5. 제1항에 있어서, 상기 리드(14)는 비전도성의 세라믹 재질의 사각판(14)에 다수개의 솔더범프(14a)를 형성한 것임을 특징으로 하는 반도체 패키지.
  6. 제1항에 있어서, 상기 금속컨택트부(15)는 알루미늄(Al) 또는, 알루미늄 합금계열의 도전성 금속인 것을 특징으로 하는 반도체 패키지.
KR1019920000421A 1992-01-14 1992-01-14 반도체 패키지 KR0157857B1 (ko)

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KR1019920000421A KR0157857B1 (ko) 1992-01-14 1992-01-14 반도체 패키지
TW81108390A TW262583B (ko) 1992-01-14 1992-10-21
US07/964,718 US5326932A (en) 1992-01-14 1992-10-22 Semiconductor package
JP29615992A JP3110174B2 (ja) 1992-01-14 1992-11-05 半導体パッケージ
DE19924238438 DE4238438A1 (en) 1992-01-14 1992-11-13 Semiconductor component - comprises chip with bonding sites, base with hollow to house chip and lid on upper surface of chip

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KR0179924B1 (ko) * 1996-06-14 1999-03-20 문정환 버텀리드 반도체 패키지
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
KR100206910B1 (ko) * 1996-06-14 1999-07-01 구본준 반도체 패키지의 디플래쉬 방법
US6335225B1 (en) * 1998-02-20 2002-01-01 Micron Technology, Inc. High density direct connect LOC assembly
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
FR2819936B1 (fr) * 2001-01-22 2003-05-30 St Microelectronics Sa Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a puces de circuits integres
US6981230B1 (en) 2002-07-30 2005-12-27 Apache Design Solutions, Inc. On-chip power-ground inductance modeling using effective self-loop-inductance

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US5139968A (en) * 1989-03-03 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Method of producing a t-shaped gate electrode
JPH03227541A (ja) * 1990-02-01 1991-10-08 Hitachi Ltd 半導体装置
US5139969A (en) * 1990-05-30 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Method of making resin molded semiconductor device
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US5153385A (en) * 1991-03-18 1992-10-06 Motorola, Inc. Transfer molded semiconductor package with improved adhesion
JPH05251513A (ja) * 1991-05-28 1993-09-28 Oki Electric Ind Co Ltd 半導体装置

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JPH05343558A (ja) 1993-12-24
DE4238438A1 (en) 1993-07-15

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