CN1169032A - 引线框架和半导体封装 - Google Patents

引线框架和半导体封装 Download PDF

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CN1169032A
CN1169032A CN96120809A CN96120809A CN1169032A CN 1169032 A CN1169032 A CN 1169032A CN 96120809 A CN96120809 A CN 96120809A CN 96120809 A CN96120809 A CN 96120809A CN 1169032 A CN1169032 A CN 1169032A
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金善东
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SK Hynix Inc
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LG Semicon Co Ltd
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Abstract

一种引线框架包括第一引线和形成于第一引线上的第二引线。第二引线可包括导电粘结剂和粘接于第一引线上的导电层。所述引线可用于一种封装，其中第二引线暴露于模制树脂的外部，和/或半导体芯片具有多个中心芯片焊盘。

Description

引线框架和半导体封装
本发明涉及一种引线框架和半导体封装，特别涉及一种改进了的底部引线封装的引线框架。
图1是常规底部引线半导体封装的纵剖图。如该图所示，常规底部引线半导体封装包括：半导体芯片1；和由多根连接基片的引线2a组成的引线2，引线2a的上表面安装半导体芯片1，底表面与基片连接(未示出)。多个连接芯片的引线2b从连接基片的引线2a延伸，以便与半导体芯片1引线接合。
粘结剂3把半导体芯片1粘结在引线2的连接基片的引线2a的上表面上。多根连线5电连接半导体芯片1的芯片焊盘/接合焊盘(未示出)和引线2的连接芯片的引线2a。模制树脂4模制包括已导线连接的半导体芯片1和引线2的两种引线2a及2b的预定区域，以使引线框架的连接基片的引线2a的底表面暴露于封装管座的底表面。引线2的基片连接的引线2a从连接芯片的引线2b向下延伸预定深度。
美国专利5428248中详细说明了这种有上述结构的半导体封装，该专利已转让给本发明的受让者，在此可对它所公开的内容作了引证。然而，在上述常规半导体封装中，当芯片焊盘位于半导体封装的侧边时，可以进行引线接合，但当芯片焊盘位于其中心时，无法进行引线接合。
一种至少可部分实现本发明的集成芯片封装的引线框架包括：彼此相隔预定距离的一对导轨；连接这对导轨的至少一个阻拦条；从阻拦条上延伸出的多根第一引线，该第一引线有预定长度；及多根第二引线，相应的第二引线形成于相应的第一引线的第一表面的预定部位。
一种至少可部分实现本发明的芯片封装包括：a)有第一和第二表面及形成于第一表面上的多个焊盘的集成芯片；b)多根引线，每根引线包括i)有第一和第二表面的第一引线，第一引线的第一表面与集成芯片的第一表面连接，及ii)形成于第一引线的第二表面的预定部位上的第二引线；用于电耦合多个接合焊盘与多根引线的装置；以及用于模制集成芯片、多根引线和电耦合装置的模制树脂，其中第二引线的预定部分暴露于模制树脂的外表面。
下面的说明会部分地表现出本发明的其它优点、目的和其它特点，而且本领域的技术人员通过下面的试验或通过实践本发明会更清楚本发明的这些优点、目的和特点。所附权利要求书所特别指出的方案，可以实现本发明的目的和取得本发明的优点。
下面将参照附图详细说明本发明，各附图中相同的标记表示相同的部件。
图1是常规技术的纵剖图；
图2A是本发明的一个实施例的引线框架的平面图；
图2B是沿图2A的A-A线的剖面图；
图3A至3D是表示按照本发明的用图2中的引线框架的底部引线半导体封装的制造方法及其结构；
图4A是本发明的另一实施例的引线框架的平面图；
图4B是沿图4A的B-B线的剖面图；
图5A至5D是表示按照本发明的用图4中的引线框架的底部引线半导体封装的制造方法及其结构。
如图2A和2B所示，形成一对彼此平行的导轨10a和10b，它们之间有预定间距，在半导体封装制造过程中，用它们作传送引导装置。形成垂直连接于导轨10a和10b间的多根阻拦条11，它们在一对导轨间有预定长度。在半导体封装制造过程中，阻拦条11可防止模制树脂渗入其它地方。
多根第一引线12从阻拦条11的侧边延伸。所形成第一引线12与导轨10a和10b平行。第一引线12有预定长度，以使与另一侧的第一引线12间有预定宽度。于是，在阻拦条11间形成与之平行的预定面积的所得间隔13。
在每一第一引线12的上表面的中心设置导电粘结剂14，把第二引线15粘接到导电粘结剂14的上表面。用双面导电带作导电粘结剂14，牢固粘结第一引线12和第二引线15。第一引线12和第二引线15间存在预定的高度差T1。
图3A至3D是半导体封装制造方法的剖面图。如图3A所示，有一种引线框架，其中将导电粘结剂14设置于第一引线12的上表面的中心，第二引线15形成于导电粘结剂14的上表面上。
然后，如图3B所示，在引线框架的第一引线12的底表面上粘结双面绝缘带。借助双面带的粘结力，把有中心焊盘的半导体芯片粘结到第一引线12的底表面上，以便通过多根第一引线12(即，图2A和2B中的间隔13)暴露其中心焊盘。用多根导电连线21连接半导体芯片20的中心焊盘与第一引线12。可通过焊料凸起或任何其它已知装置连接中心/接合焊盘与第一引线，这相当于已有普通技术中的一种。
如图3C所示，用模制树脂30模制和包封半导体芯片20、多根引线12和15、及导线21。如图3D所示，切掉从模制树脂的边缘部分突出的第一引线12，从而完成底部引线半导体封装。为了把半导体芯片20的电信号传输出到外部，进行模制工艺，暴露第二引线15的上表面，以在其上安装基片(未示出)。
如图3D所示，按本发明的一个实施例的底部引线半导体封装包括：有多个形成于其上的中心焊盘的半导体芯片20；和粘结在半导体芯片20的上表面的两侧的多根第一引线12。多根连线连接第一引线12，在第一引线12的上表面的中心设置多个导电粘结剂14。把多根第二引线15粘结到导电粘结剂14上，用模制树脂30模制半导体芯片20，暴露第二引线15的上表面。
图4A是本发明的另一个实施例的引线框架的平面图，图4B是沿图4A中B-B线的剖面图。一种引线框架包括：一对彼此平行地形成的导轨10a和10b，它们之间有预定间隔；垂直连接于导轨10a和10b间的多个阻拦条11。与阻拦条11侧边的导轨10a、10b平行地形成多根第一引线12’。引线框架的第一引线12’的中心部分向上突出，且有预定厚度T2，以代替导电粘结剂14和第二引线15。在引线12’中心部分形成比引线12’厚且有预定厚度的凸起15-1，在完成封装时，用它作与基片(未示出)连接的底部引线。
图5A至5D是表示按照本发明的用图4中的引线框架的底部引线半导体封装的制造方法及其结构。首先，如图5A所示，提供与图4A和4B中的引线框架等同的引线框架，该引线框架有在上表面的中心形成突起的多根引线12’。
然后，如图5B所示，把双面绝缘带粘结到引线12’的底表面上。借助于双面带的粘结力，把有中心焊盘(未示出)的半导体芯片20粘结到引线的底表面上，以便通过粘结在半导体芯片20上表面两侧的多根引线12’暴露其中心焊盘。用多根导电连线连接半导体芯片20的中心焊盘和引线12’。显然，也可用焊料凸起连接中心焊盘和引线。
如图5C所示，用模制树脂30模制和包封半导体芯片20、多根引线12’和凸起15-1、及导线21。如图5D所示，切掉从模制树脂的边缘部分突出的第一引线12’的预定部分，从而完成底部引线半导体封装。为了把半导体芯片20的电信号输出到外部，用模制树脂30进行模制工艺，暴露将用作底部引线的凸起15-1的上表面，以在其上安装基片(未示出)。
如图5D所示，按本发明的另一个实施例的底部引线半导体封装包括：有多个中心焊盘的半导体芯片20；和由粘结在半导体芯片20的上表面两侧的多根引线12’构成的引线框架。凸起15-1在引线12’上表面的中心向上突起，多根连线连接形成于半导体芯片20上的芯片焊盘和引线12’。用模制树脂30模制半导体芯片20，只暴露凸起15-1的上表面。
上述实施例仅是例证性的，并不限制本发明。可以容易地将本发明的方案用于引线暴露于封装的底表面或上表面上的其它类型的封装。例如，本发明可以用于公开于美国专利5363279、5428248、5326932、5444301和5471088中的封装，这些申请一般归于与本申请相同的受让者，且可通过引证把它们所公开的内容结合于本申请中。而且，本发明公开了用模制树脂完全封装的芯片。显然，本发明也可用于不完全包封半导体芯片的封装，即，模制树脂封装半导体芯片。在上述实施例中，为了便于用附图说明本发明，称各表面为上和下表面或上和底表面。显然，对表面的引用取决于封装的取向。本发明的说明只是说明性的，并不限制要求书的范围。本领域的技术人员可以对本发明作出许多替换、改型和变化。

Claims (21)

1.一种集成芯片封装的引线框架，包括：
彼此相隔预定距离的一对导轨；
连接所述一对导轨的至少一个阻拦条；
从所述阻拦条上延伸出的多根第一引线，所述第一引线有预定长度；及
多根第二引线，相应的第二引线形成于相应的第一引线的第一表面的预定部位。
2.如权利要求1所述的引线框架，其特征在于：所述一对导轨基本彼此平行，且所述多根第一引线基本平行于所述导轨。
3.如权利要求1所述的引线框架，其特征在于：所述多根第二引线的每一根皆包括：
粘结到所述相应第一引线的所述第一表面的所述预定部位的导电粘结剂；及
粘结到所述第一引线相对的表面上的所述导电粘结剂的导电层。
4.如权利要求1所述的引线框架，其特征在于：所述预定部位是所述第一引线的中心部位。
5.如权利要求3所述的引线框架，其特征在于：所述导电粘结剂为双面导电带。
6.如权利要求1所述的引线框架，其特征在于：在相邻阻拦条间形成预定面积的开口。
7.如权利要求1所述的引线框架，其特征在于：所述多根第二引线的每一根皆是一个从所述第一引线的所述表面延伸出且具有预定形状和厚度的凸起。
8.如权利要求7所述的引线框架，其特征在于：所述预定形状为梯形。
9.如权利要求7所述的引线框架，其特征在于：所述凸起的所述厚度大于所述第一引线的厚度。
10.一种芯片封装，包括：
a)有第一和第二表面及形成于所述第一表面上的多个焊盘的集成芯片；
b)多根引线，每根引线包括：
i)有第一和第二表面的第一引线，所述第一引线的所述第一表面连接到所述集成芯片的所述第一表面，和
ii)形成于所述第一引线的所述第二表面的预定部位的第二引线；
电耦合所述多个接合焊盘与所述多根引线的装置；及
模制所述集成芯片、多根引线和电耦合装置的模制树脂，其中所述第二引线的预定部分暴露于所述模制树脂的外表面。
11.如权利要求10所述的芯片封装，其特征在于：所述第一引线和集成芯片的所述第一和第二表面是相反的表面。
12.如权利要求10所述的芯片封装，其特征在于：所述电耦合装置是多根连线。
13.如权利要求12所述的芯片封装，其特征在于：每根连线连接相应的接合焊盘与相应的第一引线。
14.如权利要求10所述的芯片封装，其特征在于：所述模制树脂包封集成电路。
15.如权利要求10所述的芯片封装，其特征在于：所述第二引线包括：
粘接到所述第一引线的所述第二表面的所述预定部位的导电粘结剂；及
粘接到所述第一引线相对的表面上的导电粘结剂的导电层。
16.如权利要求10所述的芯片封装，其特征在于：所述预定部位是第一引线的中心部位。
17.如权利要求15所述的芯片封装，其特征在于：所述导电粘结剂为双面导电带。
18.如权利要求10所述的芯片封装，其特征在于：所述第二引线是一个从所述第一引线的所述表面延伸出且具有预定形状和厚度的凸起。
19.如权利要求18所述的芯片封装，其特征在于：所述预定形状为梯形。
20.如权利要求18所述的芯片封装，其特征在于：所述凸起的所述厚度大于所述第一引线的厚度。
21.如权利要求10所述的芯片封装，其特征在于：所述多个接合焊盘形成于所述集成芯片的所述第一表面中心部位。
CN96120809A 1996-06-14 1996-11-27 引线框架和半导体封装 Pending CN1169032A (zh)

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KR1019960021536A KR0179925B1 (ko) 1996-06-14 1996-06-14 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100454503C (zh) * 2007-03-21 2009-01-21 宁波康强电子股份有限公司 三极管引线框架的制造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3026426B2 (ja) * 1996-08-29 2000-03-27 沖電気工業株式会社 樹脂封止型半導体装置とその製造方法及びその金型構造
KR100214544B1 (ko) * 1996-12-28 1999-08-02 구본준 볼 그리드 어레이 반도체 패키지
KR19980080551A (ko) * 1997-03-25 1998-11-25 사또아끼오 수지 패키지, 반도체장치 및 수지 패키지의 제조방법
DE19745648A1 (de) * 1997-10-15 1998-11-26 Siemens Ag Trägerelement für einen Halbleiterchip zum Einbau in Chipkarten
JP3420057B2 (ja) * 1998-04-28 2003-06-23 株式会社東芝 樹脂封止型半導体装置
JP3862411B2 (ja) 1998-05-12 2006-12-27 三菱電機株式会社 半導体装置の製造方法及びその構造
KR100293815B1 (ko) * 1998-06-30 2001-07-12 박종섭 스택형 패키지
US6469399B2 (en) * 1999-02-08 2002-10-22 Advanced Semiconductor Engineering, Inc. Semiconductor package
TW404030B (en) * 1999-04-12 2000-09-01 Siliconware Precision Industries Co Ltd Dual-chip semiconductor package device having malposition and the manufacture method thereof
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US6949824B1 (en) * 2000-04-12 2005-09-27 Micron Technology, Inc. Internal package heat dissipator
US6576496B1 (en) 2000-08-21 2003-06-10 Micron Technology, Inc. Method and apparatus for encapsulating a multi-chip substrate array
JP2002093831A (ja) * 2000-09-14 2002-03-29 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US20130249387A1 (en) * 2012-03-20 2013-09-26 Chia-Fen Hsin Light-emitting diodes, packages, and methods of making

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902148A (en) * 1970-11-27 1975-08-26 Signetics Corp Semiconductor lead structure and assembly and method for fabricating same
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지
KR0157857B1 (ko) * 1992-01-14 1998-12-01 문정환 반도체 패키지
KR0128251Y1 (ko) * 1992-08-21 1998-10-15 문정환 리드 노출형 반도체 조립장치
JPH077121A (ja) * 1992-09-18 1995-01-10 Texas Instr Inc <Ti> 多層リードフレームアセンブリを有する半導体デバイスおよびそのパッケージ方法
KR960005042B1 (ko) * 1992-11-07 1996-04-18 금성일렉트론주식회사 반도체 펙케지
KR0152901B1 (ko) * 1993-06-23 1998-10-01 문정환 플라스틱 반도체 패키지 및 그 제조방법
JP3243116B2 (ja) * 1994-05-17 2002-01-07 株式会社日立製作所 半導体装置
JP3279841B2 (ja) * 1994-10-18 2002-04-30 三菱電機株式会社 樹脂封止型半導体装置、その製造方法およびその実施に用いる金型

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100454503C (zh) * 2007-03-21 2009-01-21 宁波康强电子股份有限公司 三极管引线框架的制造方法

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JPH1056124A (ja) 1998-02-24
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US5898212A (en) 1999-04-27
KR0179925B1 (ko) 1999-03-20
DE19651549B4 (de) 2004-03-18

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