KR940007757Y1 - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR940007757Y1
KR940007757Y1 KR2019910019458U KR910019458U KR940007757Y1 KR 940007757 Y1 KR940007757 Y1 KR 940007757Y1 KR 2019910019458 U KR2019910019458 U KR 2019910019458U KR 910019458 U KR910019458 U KR 910019458U KR 940007757 Y1 KR940007757 Y1 KR 940007757Y1
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KR
South Korea
Prior art keywords
lead
semiconductor package
chip
lead frame
package
Prior art date
Application number
KR2019910019458U
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English (en)
Other versions
KR930012117U (ko
Inventor
차기본
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR2019910019458U priority Critical patent/KR940007757Y1/ko
Priority to US07/970,771 priority patent/US5363279A/en
Priority to JP078208U priority patent/JPH0546045U/ja
Priority to DE4238646A priority patent/DE4238646B4/de
Publication of KR930012117U publication Critical patent/KR930012117U/ko
Application granted granted Critical
Publication of KR940007757Y1 publication Critical patent/KR940007757Y1/ko
Priority to US08/748,460 priority patent/USRE36097E/en
Priority to JP9254578A priority patent/JPH1093001A/ja
Priority to US09/152,702 priority patent/USRE37413E1/en

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material

Abstract

내용 없음.

Description

반도체 패키지
제 1a, b 도는 종래의 기술에 의한 일반적인 반도체 패키지의 외부 형상을 보이는 도면으로서, (a)는 SOP(Small Outline Package)의 외형을 보인 것이고, (b)는 SOJ(Small Outline J-Lead)의 외형을 보인 것이다.
제 2 도 및 제 3 도는 종래 기술에 의한 일반적인 LOC형 반도체 패키지의 내부 구성을 보인 단면도 및 내부 평면도.
제 4a,b 도는 본 고안에 의한 반도체 패키지의 외부형상을 보이는 정면도 및 저면도.
제 5 도 및 제 6 도는 본 고안에 의한 반도체 패키지의 내부 구성을 보인 단면도 및 내부 저면도.
* 도면의 주요부분에 대한 부호의 설명
3 : 반도체 칩 3a : 본드패드
5 : 버스바리드 6 : 절연접착제
7 : 금속와이어 8 : 몰딩컴파운드
10 : 리드프레임 10a : 인너리드
10b : 아웃리드
본 고안은 반도체 패키지 구조에 관한 것으로, 특히 리드프레임의 패들을 제거하고, 반도체 패키지의 몰딩수지 저면 부위에 리드프레임의 아웃리드 끝부분을 노출시켜 인쇄회로기판에 표면실장(SMT)할 수 있도록 함으로써 센터 패드 레이 아웃(Center Pad Lay Out)형태의 메모리 칩 패키징에 적합 하도록 한 반도체 패키지에 관한 것이다.
종래 기술에 의한 일반적인 반도체 패키지는 리드 프레임의 패들위에 반도체 칩을 탑재하여 와이어 본딩 공정을 수행하고 몰딩한 후, 외부로 돌출된 리드프레임의 아웃리드를 소정의 모양으로 절곡형성하는 포밍공정 및 통상적인 플래팅 공정의 순으로 제작되며, 상기 아웃리드의 절곡형태에 따라 제 1a 도와 같은 SOP(Small Outline Package)와, (b)와 같은 SOJ(Small Outline J-Lead)타입 반도체 패키지등으로 구분된다. 이와같이 제작된 반도체 패키지는 통상 기판에 SMT(Surface Mounted Technology)방법으로 실장되어 동작하게 된다.
도면에서 1은 패키지 몸체, 2는 기판과의 접속을 위한 아웃리드를 보인 것이다.
또한 최근에는 메모리칩의 센터(Center) 부분에 외부연결단자인 본드패드(bond pad)를 형성하여 패들(paddle)이 없는 리드프레임(Lead Frame)으로 상기와 같은 반도체 패키지를 제작하는 이른바 LOC(Lead On Chip)라는 반도체패키지가 알려지고 있는 바, 이를 간단히 설명하면 다음과 같다.
즉, 종래의 LOC타입 반도체 패키지는, 제 2 도 및 제 3 도에 도시한 바와같이, 중간 부분에 복수개의 본드패드(3a)가 구비된 칩(3)의 상면에 인너리드(4a)와 아웃리드(4b)로 형성된 리드프레임(4)과, 전원 입출력 패드와의 연결을 위한 버스바리드(5)가 절연테이프(6)등에 의해 부착되어 있고, 칩(3)의 본드패드(3a)과 리드프레임(4)의 인너리드(4a)는 금속와이어(7)에 의해 전기적으로 접속 연결되어 있으며, 에폭시 수지등과 같은 몰딩 컴파운드(8)에 의해 상기 칩(3)과 아웃리드(4b)를 포함하는 일정부위가 몰딩(Molding)된 구성으로 되어 있다.
이와같이 구성되는 반도체 패키지는 칩(3)을 개개로 분리하는 소잉(Sawing)공정과, 분리된 칩(3)에 리드프레임(4)을 부착하는 다이본딩(Die bonding) 공정과, 다이본딩 공정이 끝난 칩(3)과 리드프레임(4)의 인너리드(4a)를 전기적으로 접속 연결하는 와이어 본딩공정과, 와이어 본딩이 끝난 칩(3)을 밀폐시키는 몰딩공정과 통상적인 디플레쉬(Deflash)공정 및 솔더 플래팅(Sollder Plating)공정과, 리드프레임(4)의 댐바(Damber)(도시되지 않음)를 절단하는 트리밍(Trimming)공정과, 아웃리드(4b)를 소정의 모양으로 절곡하는 포밍(Forming)공정과, 마킹(Marking)공정의 순으로 제작되며, 상기 포밍공정에 따라 아웃리드(4b)가 걸(gull) 폼형태인 SOP타입, 또는 아웃리드(4b)가 J-폼 형태인 SOJ타입 반도체 패키지 등으로 구분된다.
이와같이 구성된 종래 기술에 의한 반도체 패키지는, 몰드수지 외부로 아웃리드(4b)들이 돌출형성되어 있고, 그 아웃리드(4b)들을 소정형태로 포밍시켜 인쇄회로기판(PCB)상에 장착시키게 되어 있다.
그러나, 이와같은 종래 기술에 반도체 패키지는 아웃리드(4b)가 패키지의 몰드수지의 외부로 돌출형성되어 있으므로, 반도체 패키지를 인쇄회로기판 위에 탑재시킬때에 그 패키지가 차지하는 면적이 커서 실장율이 떨어지는 문제점이 있다.
또, 반도체 패키지의 포밍공정시에 외부의 기계적인 충격을 주게 되므로, 패키지의 외부로 돌출된 아웃리드(4b)와 몰드수지와의 접촉부분에 미세한 틈이 생겨 내습성이 떨어지는 결함이 발생된다.
또, 패키지 제작시에 몰딩공정 이후에 트리밍(Trimming)공정 및 포밍공정등이 필요하기 때문에 제조공정이 복잡하여 제조비용이 상승되고, 공정불량율이 높아지는 문제점이 있다.
또, 패들이 없는 리드프레임을 이용한 LOC타입 패키지에서는 아웃리드(4b)까지의 길이가 길어서 전기적 특성이 저하되는 문제점이 있다.
또한, 패키지 테스트시에 리드 콘텍트(Lead Contact)의 불량으로 인하여 불량패키지로 판명된 제품중에 실제로는 양호한 제품이 속해 있는 비율인 굳 레이트(Good Rate)가 높아지는 문제점이 있다.
본 고안의 목적은 인쇄회로기판상에 반도체 패키지를 장착시키는 실장율을 향상시키고, 몰딩공정 이후의 반도체 제조공정을 생략하여 제조원가를 줄일수 있도록 한 반도체 패키지를 제공함에 있다.
본 고안의 다른 목적은, 리드프레임의 인너리드에서 아웃리드까지의 길이를 짧게 형성하여 리드 컨덕턴스(Conductance)를 향상 시키고 전기적 특성을 개선시킨 반도체 패키지를 제공함에 있다.
이와같은 목적을 달성시키기 위한 본 고안에 의한 반도체 패키지는, 반도체 칩의 저면 중앙부위에 복수개의 본드패드가 형성되고, 그들 본드패드의 양쪽 상기 반도체 칩의 저면에 패들이 생략된 짧은 리드프레임의 인너리드가 각각 접착되고, 그들 본드패드와 인너리드가 각각 금속와이어에 의해 전기적으로 접속연결되고, 상기 리드프레임의 아웃리드가 돌출되지 않고 패키지 표면에 단지 노출되도록 그들 반도체 칩과 리드프레임이 몰딩 되어서 반도체 패키지가 구성되어 있다.
여기서, 본 고안에 의한 반도체 패키지는, 반도체 칩의 본드패드와 본딩되는 인너리드에서 패키지의 외부와 콘택할수 있게 노출되는 아웃리드 단부까지의 리드길이를 짧게 구성하여 종래 LOC 구조에서 문제가 되는 리드콘덕턴스를 개선하고, 칩의 기능동작시에 발생되는 열을 짧은 리드를 통해 외부로 쉽게 방출시킬 수 있게 구성하여 특히, 16메가디램(16M DRAM)급 이상의 메모리칩중 센터부분에 본드패드가 형성된 반도체 칩을 패키징화 하는데에 매우 적합하게 하였다.
또한, 그들 리드프레임의 아웃리드를 일정하게 구부린 후, 정렬시켜 폴리이미드계(thermo plastic계)의 접착테이프에 부착고정하고, 그들 리드프레임의 인너리드 부분에 절연필름 또는 절연 페이스트(paste)를 사용하여 반도체 칩을 접착시키고, 그들 리드프레임의 아웃리드가 외측으로 돌출되지 않고 다만 노출되게 반도체 칩과 리드프레임을 몰딩시켜서 반도체 패키지를 구성하고 있다.
이하에서는 이러한 본 고안을 첨부한 도면에 의하여 보다 상세히 설명하겠다.
제 4a, b 도는 본 고안에 의한 반도체 패키지의 외부형상도 및 저면도로서, 이에 도시한 바와같이, 본 고안에 의한 반도체 패키지는 기판(도시되지 않음)과의 접속을 위한 복수개의 아웃리드(10b)의 절곡 끝부위가 패키지의 저면 즉, 몰딩 컴파운드(8)의 저면 내측에 노출형성되어 있다.
이와같이 복수개의 아웃리드(10b)를 패키지의 저면으로 노출시켜 기판에 표면 실장할 수 있도록 함으로써 실장율을 높일 수 있는 것인바, 이의 상세한 구성을 제 5 도 및 제 6 도를 참조하여 설명하면 다음과 같다.
즉, 본고안에 의한 반도체 패키지는, 제 5 도 및 제 6 도에 도시한 바와같이, 중간부에 복수개의 본드패드(3a)가 형성된 반도체 칩(3)과, 상기 본드패드(3a)와 접속연결되는 인너리드(10a)와 기판(도시되지 않음)과의 접속을 위한 아웃리드(10b)가 구비된 리드프레임(10)과, 상기 칩(3)에 리드프레임(10)을 부착하게 위한 절연접착제(6)와, 상기 반도체 칩(3)의 본드패드(3a)와 리드프레임(10)의 인너리드(10a) 및 버스바리드(5)를 전기적으로 접속 연결시키는 금속 와이어(7)와, 그들을 밀폐시키는 에폭시 수지등과 같은 몰딩 컴파운드(8)의 구성은 종래와 동일하나, 기판과의 접속을 위한 아웃리드(10b)를 패지지의 저면내측에 형성하여 외부로 노출시킴과 아울러 인너리드(10a)와 아웃리드(10b)와의 길이를 짧게 형성하여 구성한 것으로, 도면에서 종래구성과 동일한 부분에 대해서는 동일부호를 부여 하였다.
상기 리드프레임(10)은 고온, 고압에 견딜 수 있는 폴리이미드계(thermo Plastic계) 접착테이프에 복수개의 신호리드들을 정렬하여 부착한 구성으로 되어 있으며, 절연필름 또는 절연 페이스트(Paste)를 이용하여 리드프레임(10)의 인너리드(10a) 부분에 반도체 칩(3)을 부착 고정하게 되어 있다.
이와같이 구성된 본 고안에 의한 반도체 패키지의 제조공정을 살펴보면, 먼저 소잉(Sawing)공정에 의해 개개로 분리된 칩(3)을 리드프레임(10)의 인너리드(10a) 부분에 절연 필름이나 절연 페이스트등과 같은 절연접착제(6)를 이용하여 뒤집어서 부착 고정한 다음, 와이어 본더(Wire Bonder)에 다이 어태치(die attach)된 리드프레임(10)을 다시 뒤집어 놓고 골드(Au)나 알루미늄(Al)등과 같은 금속와이어(7)로 칩의 본드패드(3a)와 인너리드(10a) 및 버스바스리드(5)를 전기적으로 접속 연결하는 와이어본딩 공정을 수행한다.
이와같이 하여 와이어 본딩 공정이 완료되면 종래의 트랜스퍼 몰딩 방식과 동일하게 몰딩공정을 수행하여 밀폐시킨 후, 그 저면에 부착된 접착 테이프를 제거하면, 리드프레임(10)의 아웃리드(10b)가 패키지의 저면으로 노출되는 것이다.
이러한 상태에서 패키지의 외부 및 리드부분을 간단히 디스플래쉬(Deflash)함으로써 패키지가 완료된다.
이와같은 본 고안에 의한 반도체 패키지는, 인쇄회로기판에 형성된 접속패턴에 상기 반도체 패키지의 표면에 노출된 아웃리드들을 솔더링등에 의해 연결 접속시켜 인쇄회로기판에서 탑재시켜 사용된다.
이상에서 설명한 바와같이 본 고안에 의한 반도체 패키지는, 몰딩 이후의 공정을 줄일 수 있다. 즉, 종래의 반도체 패키지에 있어서는 패키지의 외부로 아웃리드들이 돌출형성되므로 이들을 적절하게 구부리는 포밍공정 및 프레임을 형성시킨 댐버를 절단하는 트림공정등이 필요하나, 본 고안에서는 리드들을 접착테이프에 부착시켜 프레임으로 구성되고, 아웃리드가 패키지의 표면에 노출되게 구성하므로, 트림공정 및 포밍공정등이 불필요하게 된다. 이에따라 작업공정을 줄일 수 있는 효과와, 제조원가를 절감할 수 있는 효과 및 공정수가 줄어들기 때문에 패키지의 불량을 줄일 수 있는 효과가 있다.
또, 패키지의 외부로 돌출되는 아웃리드가 없으므로, 패키지를 기판에 탑재시킬 때에 그 패키지가 차지하는 면적이 줄어들어 고밀도의 실장에 적합한 효과가 있다.
또, 패키지 내부에서 리드의 길이를 최단길이로 형성시킬 수 있게되어 전기적인 특성을 향상시킬 수 있고, 아울러 종래에 비해 쉽게 열이 방출되는 효과가 있다.
또, 종래에는 트림공정이나 포밍공정시 아웃리드들에 충격이 가해져서 몰딩부분과의 틈이 발생될 염려가 있으나, 본 고안에서는 아웃리드들을 패키지 표면에 노출시켜 구성하고, 트림공정 및 포밍공정등이 불필요하기 때문에 충격을 주지않아 충격에 의한 틈발생을 방지할 수 있어서 내습성을 향상시키는 효과가 있고, 패키지의 테스트시 컨태치(Contach)를 팁(tip)상태로 테스트할 수 있으므로, 특별한 테스트 소켓 없이도 정확한 테스트를 할 수 있는 효과가 있다.

Claims (5)

  1. 중간부에 복수개의 본드패드(3a)가 형성된 반도체 칩(3)고, 그 칩(3)의 본드패드(3a)에 연결되는 인너리드(10a)와 기판과의 접속을 위한 아웃리드(10b)가 구비된 리드프레임(10)과, 그 리드프레임(10)에 칩(3)을 부착고정하기 위한 절연접착제(6)와, 상기 칩(3)의 본드패드(3a)와 인너리드(10a) 및 버스바리드(5)를 전기적으로 접속연결시키는 금속와이어(7)와, 그들을 밀폐시키는 몰딩컴파운드(8)로 구성된 반도체 패키지에 있어서, 상기 아웃리드(10b)의 절곡 끝부위를 몰딩컴파운드(8)의 저면 내측에 노출시켜 실장율을 높임과 아울러 패키지의 전기적 특성을 향상시킬 수 있도록 구성함을 특징으로 하는 반도체 패키지.
  2. 제 1 항에 있어서, 상기 리드프레임(10)은 폴리아미드계 접착테이프에 인너리드(10a)와 아웃리드(10b)가 구비된 복수개의 신호리드들을 정렬하여 부착고정한 것임을 특징으로 하는 반도체 패키지.
  3. 제 1 항에 있어서, 상기 반도체 칩(3)을 리드프레임(10)의 인너리드(10a)부분에 절연접착제(6)를 이용하여 뒤집어서 부착고정함을 특징으로 하는 반도체 패키지.
  4. 제 3 항에 있어서, 상기 절연접착제(6)는 절연필름인 것을 특징으로하는 반도체 패키지.
  5. 제 3 항에 있어서, 상기 절연접착제(6)는 절연페이스트인 것을 특징으로 하는 반도체 패키지.
KR2019910019458U 1991-11-14 1991-11-14 반도체 패키지 KR940007757Y1 (ko)

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KR2019910019458U KR940007757Y1 (ko) 1991-11-14 1991-11-14 반도체 패키지
US07/970,771 US5363279A (en) 1991-11-14 1992-11-03 Semiconductor package for a semiconductor chip having centrally located bottom bond pads
JP078208U JPH0546045U (ja) 1991-11-14 1992-11-13 半導体パツケージ
DE4238646A DE4238646B4 (de) 1991-11-14 1992-11-16 Halbleiter-Bauelement mit spezieller Anschlusskonfiguration
US08/748,460 USRE36097E (en) 1991-11-14 1996-11-08 Semiconductor package for a semiconductor chip having centrally located bottom bond pads
JP9254578A JPH1093001A (ja) 1991-11-14 1997-09-19 半導体パッケージおよびその製造方法
US09/152,702 USRE37413E1 (en) 1991-11-14 1998-09-14 Semiconductor package for a semiconductor chip having centrally located bottom bond pads

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KR2019910019458U KR940007757Y1 (ko) 1991-11-14 1991-11-14 반도체 패키지

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US5363279A (en) 1994-11-08
JPH0546045U (ja) 1993-06-18
USRE36097E (en) 1999-02-16
DE4238646B4 (de) 2006-11-16
USRE37413E1 (en) 2001-10-16
JPH1093001A (ja) 1998-04-10
KR930012117U (ko) 1993-06-25

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