JPH01161724A - 表面実装用半導体装置の製造方法 - Google Patents

表面実装用半導体装置の製造方法

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Publication number
JPH01161724A
JPH01161724A JP62318500A JP31850087A JPH01161724A JP H01161724 A JPH01161724 A JP H01161724A JP 62318500 A JP62318500 A JP 62318500A JP 31850087 A JP31850087 A JP 31850087A JP H01161724 A JPH01161724 A JP H01161724A
Authority
JP
Japan
Prior art keywords
substrate
resin
pattern
semiconductor device
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62318500A
Other languages
English (en)
Inventor
Masayasu Kizaki
木崎　正康
Kazuo Inoue
和夫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP62318500A priority Critical patent/JPH01161724A/ja
Publication of JPH01161724A publication Critical patent/JPH01161724A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は小型・薄型な表面実装用半導体装置の製造およ
び生産性向上に関するものである。
〔従来技術と問題点〕
表面実装用半導体装置の代表的なものとしてスモールア
ウトラインパッケージ（ｓｏｐ　）、ファラドフラット
パッケージ（ＱＦＰ）、プラスチックリープイツトチッ
プキャリア（ＰＬＣＣ）等が挙げられるが、どれもリー
ドフレームを使用して電極を取り出し、高価な金型を用
いトランスファーモールド法により樹脂封止される。さ
らに外部リードを切り離してリードを独立させた後、リ
ードを所定の形に折り曲げる工程を経ている。
以上の如〈従来技術においてはリードフレームを使用す
るために、表面実装用半導体装置の小型化φ薄型化が困
難であり、さらに高価な金型を用いる樹脂封止やリード
加工の工程を有するために生産性、製品の不均一性など
の問題点がある。
〔発明の目的〕
本発明はこのような欠点を解消させ、小型・薄型で生産
性の高い表面実装用半導体装置の製造方法を提供するこ
とを目的とするものである。
〔発明の構成〕
本発明の構成は、所定のパターンを形成した樹脂系基板
上に、半導体素子の電極を導電性物質を用いて接続し、
封止樹脂により樹脂系基板の片面をパターンと半導体素
子を覆うように封止した後。
樹脂系基板を除去し前記パターンを半導体装置の電極と
する工程を有することを特徴とする表面実装用半導体装
置の製造方法である。
本発明によると従来技術では必要とされたリードフレー
ムが不要となり従来よりも小型で薄型な表面実装用半導
体装置が得られ、さらに樹脂系基板の片面のみの樹脂封
止により従来技術に比べ金型が安価となること、リード
加工工程も不要であることから、生産性の向上、製品の
均一化が計れる。
以下図面を用いて本発明の詳細な説明する。
〔実施例〕
実施例１ 本発明の表面実装用半導体装置における第１の実施例を
第１図（ａ）、（ｂ）を用いて説明する。
第１図［ａ）に示すように、銅を材料とし所定のパター
ン１２を形成したポリイミド系の・基板１４上に突起電
極１６を設けた半導体素子１８を導電性物質２０例えば
導電ペーストを用いてフェイスダウンボンディングする
。その後、封止樹脂２２として例えばエポキシ系封止樹
脂を使用しトランス　′ファーモールド法によりポリイ
ミド系の基板１４０片側に位置する半導体素子１８とポ
リイミド系の基板１４との空隙および半導体素子１８の
表面を樹脂封止する。
次に第１図（ｂ）に示すよ５にポリイミド系の基板１４
を剥離する。
第１図（ａ）の断面構造において、ポリイミド系の基板
１４のパターン１２を形成すえ側の表面を鏡面にし、こ
の面に無電界メツキ法等によって銅を所定めパターン１
２に形成する。
さらにパターン１２の封止樹脂２２のエポキシ系封止樹
脂と接する側は機械的処理や化学的処理により粗面にす
ることによって、ポリイミド系の基板１４を剥離する際
パターン１２は、封止樹脂２２に接合したまま、ポリイ
ミド系の基板１４のみが剥離され第１図（ｂ）の断面構
造および第２図の底面を有する表面実装用半導体装置を
完成する。
実施例１ではポリイミド系基板１４と半導体素子１８の
突起電極１６との接続に導電性ペーストを、また樹脂封
止法としてトランスファーモールド法を用いたが、基板
１４と半導体素子１８の電極との接続には一般的なワイ
ヤボンディング法やフリップチップ法を、また樹脂封止
法として注型法や滴下法を用いても同じ効果がある。
第３図は、ワイヤボンディング法によりポリイミド基板
１４上に半導体素子１８を接続し、実施例１と同様に完
成した表面実装用半導体装置の断面図である。
実施例２ 本発明の表面実装用半導体装置における第２の実施例を
第４図（ａ）、（ｂ）を用いて説明する。
第４図（ａ）に示すように表面に高さ５０μｍ程度の突
起を半導体素子１８の電極と対応する位置に設けたポリ
イミド系の基板２４上に、導電性物質２６として例えば
エポキシ系導電ペーストを所定のパターンにスクリーン
印刷し、半導体素子１８の電極がポリイミド系の基板２
４表面の突起上の導電性物質２６のエポキシ系導電ペー
ストにより機械的かつ電気的に接続されるよう半導体素
子１８をフェイスダウンボンディングする。その後、エ
ポキシ系の封止樹脂２２を使用しトランスファーモール
ド法によりポリイミド系の基板２４０片側に位置する半
導体素子１８と基板２４との空隙および半導体素子１８
の表面を樹脂封止する。
次に第４図（ｂ）に示すようにポリイミド系の基板２４
を剥離する。
第４図（ａ）の断面構造において、ポリイミド系の基板
２４の突起を設けた側の表面を鏡面にすることにより、
ポリイミド系基板２４を剥離する際エポキシ系導電ペー
スト２６はエポキシ系封止樹脂２２に接合したまま、ポ
リイミド系基板２４のみが容易に剥離され、第４図（ｂ
）の断面構造および第５図の底面を有する表面実装用半
導体装置が完成する。
実施例２では樹脂封止法としてトランスファーモールド
法を用いたが、注型法や滴下法を用いても同じ効果があ
る。
〔発明の効果〕
以上の説明で明らかなように、本発明によれば、従来技
術では必要とされたリードフレームが不要となり従来よ
りも小型で薄型な表面実装用半導体装置が得られ、さら
に樹脂系基板の片面の為の樹脂封止で済むために従来技
術に比べ金型が安価となること、リード加工工程も不要
であることから、生産性の向上、製品の均一化が計れる
。
また実施例２では突起電極が不要であるとともに、ワイ
ヤボンディング法も用いないために製造コストの削減が
計られる。
さらに本発明において樹脂系基板を長い帯状にすること
によって製造ラインを容易に連続化できるため、生産性
をより向上させることができる。
本発明によるところの表面実装用半導体装置の薄さは、
例えば実施例１において半導体素子の厚さを４００μｍ
、突起電極の高さを５０μｍ、パターンの厚さを７０μ
ｍ１半導体素子上層の封止樹脂の厚さを１００μｍとし
たとき、□全体の厚さは６２０μｍとなる。
【図面の簡単な説明】
第１図（ａ）、ｌｂｌは本発明における第１の実施例を
示す工程断面図、第２図は第１図（ｂ）に対応する平面
図、第３図は本発明の第１の実施例における半導体素子
と基板をワイヤボンディングにより接続した状態を示す
断面図、第４図（ａ）、（ｂ）は本発明における第２の
実施例を示す工程断面図、第５図は第４図（ｂ）に対応
する平面図である。 １２・・・・・・パターン、 １４．２４・・・・・・基板、 １８・・・・・・半導体素子、 ２０．２６・・・・・・導電性物質、 ２２・・・・・・封止樹脂。 第１図 第２図 第５図

Claims (1)

    【特許請求の範囲】
  1. 　所定のパターンを形成した樹脂系基板上に、半導体素
    子の電極を導電性物質を用いて接続し、封止樹脂により
    前記樹脂系基板の片面を前記パターンと半導体素子を覆
    うように封止した後、前記樹脂系基板を除去し前記パタ
    ーンを半導体装置の電極とする工程を有することを特徴
    とする表面実装用半導体装置の製造方法。
JP62318500A 1987-12-18 1987-12-18 表面実装用半導体装置の製造方法 Pending JPH01161724A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62318500A JPH01161724A (ja) 1987-12-18 1987-12-18 表面実装用半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62318500A JPH01161724A (ja) 1987-12-18 1987-12-18 表面実装用半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH01161724A true JPH01161724A (ja) 1989-06-26

Family

ID=18099814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62318500A Pending JPH01161724A (ja) 1987-12-18 1987-12-18 表面実装用半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPH01161724A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
US5554887A (en) * 1993-06-01 1996-09-10 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package
US5963433A (en) * 1996-12-28 1999-10-05 Lg Semicon Co., Ltd. Bottom lead semiconductor package with recessed leads and fabrication method thereof
EP0773584A3 (en) * 1995-11-08 2000-02-02 Fujitsu Limited Device having resin package and method of producing the same
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
USRE37413E1 (en) * 1991-11-14 2001-10-16 Hyundai Electronics Industries Co., Ltd. Semiconductor package for a semiconductor chip having centrally located bottom bond pads
US6329711B1 (en) * 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
US6573121B2 (en) 1995-11-08 2003-06-03 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
DE4421077B4 (de) * 1993-06-23 2007-01-04 Goldstar Electron Co., Ltd., Cheongju Halbleitergehäuse und Verfahren zu dessen Herstellung
JP2014140080A (ja) * 2014-05-07 2014-07-31 Rohm Co Ltd 高効率モジュール

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
USRE37413E1 (en) * 1991-11-14 2001-10-16 Hyundai Electronics Industries Co., Ltd. Semiconductor package for a semiconductor chip having centrally located bottom bond pads
US5554887A (en) * 1993-06-01 1996-09-10 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package
US5710062A (en) * 1993-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US5834340A (en) * 1993-06-01 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US6046071A (en) * 1993-06-01 2000-04-04 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
DE4421077B4 (de) * 1993-06-23 2007-01-04 Goldstar Electron Co., Ltd., Cheongju Halbleitergehäuse und Verfahren zu dessen Herstellung
US6573121B2 (en) 1995-11-08 2003-06-03 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
US6329711B1 (en) * 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
EP1284501A1 (en) * 1995-11-08 2003-02-19 Fujitsu Limited Device having resin package and method of producing the same
EP1291911A1 (en) * 1995-11-08 2003-03-12 Fujitsu Limited Method having resin package and method of producing the same
EP0773584A3 (en) * 1995-11-08 2000-02-02 Fujitsu Limited Device having resin package and method of producing the same
US6856017B2 (en) 1995-11-08 2005-02-15 Fujitsu Limited Device having resin package and method of producing the same
US7144754B2 (en) 1995-11-08 2006-12-05 Fujitsu Limited Device having resin package and method of producing the same
US5963433A (en) * 1996-12-28 1999-10-05 Lg Semicon Co., Ltd. Bottom lead semiconductor package with recessed leads and fabrication method thereof
JP2014140080A (ja) * 2014-05-07 2014-07-31 Rohm Co Ltd 高効率モジュール

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