JPH0722474A - 半導体パッケージおよびその製造方法 - Google Patents
半導体パッケージおよびその製造方法Info
- Publication number
- JPH0722474A JPH0722474A JP13981294A JP13981294A JPH0722474A JP H0722474 A JPH0722474 A JP H0722474A JP 13981294 A JP13981294 A JP 13981294A JP 13981294 A JP13981294 A JP 13981294A JP H0722474 A JPH0722474 A JP H0722474A
- Authority
- JP
- Japan
- Prior art keywords
- signal transmission
- semiconductor package
- semiconductor chip
- leads
- sided tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
実装させて、生産性の向上および原価の低廉化を図り得
るようにした半導体パッケージおよびその製造方法を提
供する。 【構成】 半導体チップ11下面に接続され形成体底面
に露出される信号伝達用リード13と、該信号伝達用リ
ード13上面と半導体チップ11下面間にそれぞれ接着
および接続される絶縁性両面テープ16,26および導
電バンプ18,28と、それら信号伝達用リード13、
絶縁性両面テープ16,26、導電バンプ18,28お
よび半導体チップ11外方側周囲に形成される成形用モ
ールド樹脂14と、を備える半導体パッケージが構成さ
れる。
Description
びその製造方法に関するものであり、特に、半導体パッ
ケージの軽薄短小化を図り、高密度に実装し得るプラス
チック半導体パッケージおよびその製造方法に関するも
のである。
おいては、図4に示したように、半導体チップ1と、該
半導体チップ1の底面がエポキシ接着剤5により接着さ
れるパッド2aと、前記半導体チップ1にワイヤ3によ
りボンディングされるインナーリード2bと該インナー
リード2bから延長されるアウトリード2cとでなるリ
ードフレーム2と、それら半導体チップ1、インナーリ
ード2bおよびワイヤ3の成形されるモールド樹脂4
と、により構成されていた。
ッケージの製造方法においては、ウェハから分離された
半導体チップ1をエポキシ接着剤5によりリードフレー
ム2のパッド2aに接着させるダイアタッチング(di
e attaching)工程と、該ダイアタッチング
された半導体チップ1のパッド2aとリードフレーム2
のインナーリード2bとを金属ワイヤ3により電気的に
接続連結させるワイヤボンディング(wire bon
ding)工程と、それら半導体チップ1、リードフレ
ーム2のインナーリードおよびワイヤをモールド樹脂に
より成形しパッケージ本体を形成するモールディング
(molding)工程と、前記リードフレーム2の端
部位を切断し該リードフレーム2のアウトリード2cを
所定形態に折曲形成するトリミング/フォーミング工程
と、を順次行なうようになっていた。
うな従来のプラスチック半導体パッケージにおいては、
半導体チップとインナーリードとをワイヤによりボンデ
ィングした後成形させ、該成形本体外方側にアウトリー
ドを突成させているため、半導体の占める占有面積が大
きくなり、基板上に半導体パッケージを実装する場合、
実装率が低下されるという不都合な点があった。
リードをトリミング/フォーミングする際、機械的スト
レスによりリード側にマイクロギャップが形成され、水
分が浸透して不良品が発生しやすいという不都合な点が
あった。
薄短小化して高密度の実装率を図り、電気的特性を改善
させたプラスチック半導体パッケージを提供することに
ある。
の製造工程を簡略化して生産性を向上し、原価を低廉に
し得るプラスチック半導体パッケージの製造方法を提供
することにある。
ック半導体パッケージは、半導体チップとインナーリー
ドとを電気的に連結する金属ワイヤが省かれたプラスチ
ック半導体パッケージであって、半導体チップ下面に電
気的に接続され、成形後底面が外部に露出される複数個
の信号伝達用リードと、それら信号伝達用リードの上面
内方側に接着され、それら信号伝達用リードを半導体チ
ップ下面にそれぞれ接着させる複数個の絶縁性両面テー
プと、各信号伝達用リードの底面が列状に接着されるポ
リイミド系絶縁テープと、各信号伝達用リードの上面外
方側と半導体チップ下面所定部位とをそれぞれ電気的に
接続する複数個の導電バンプと、それら信号伝達用リー
ド、絶縁性両面テープ、導電バンプおよび半導体チップ
の外方側周囲に形成される、形成用モールド樹脂と、を
備えている。
チップ下面縁部内方面に、50ないし100μm程度に
それぞれダウンセットされるといよい。
熱硬化性または熱可塑性のテープであるとよい。
は、70ないし150μm程度の厚さを有するとよい。
ーまたは金にてなるとよい。さらに、好ましくは、導電
バンプは、高さが20ないし50μmにて形成されると
よい。
面外方側と半導体チップ下面間に絶縁性両面テープがそ
れぞれ接着され、それら信号伝達用リード上面内方側と
半導体チップ下面間に導電バンプがそれぞれ接続される
とよい。
ージの製造方法は、ポリイミド系の絶縁テープ上に複数
個の半導体パッケージチップ信号伝達用リードをそれぞ
れ接着し、それら信号伝達用リード上面に導電バンプを
それぞれ配置する手段と、それら信号伝達用リード上面
の導電バンプ側方に絶縁性両面テープをそれぞれ接着
し、それら絶縁性両面テープ上面に半導体チップ下面を
接着する段階と、該半導体チップ下面と各信号伝達用リ
ード上面とを各導電バンプにより熱圧着ボンディング
し、半導体チップを各信号伝達リードに電気的に接続す
る手段と、それら信号伝達用リード底面が露出されるよ
うに、それら信号伝達用リード、導電バンプ、絶縁性両
面テープおよび半導体チップの外方側周囲をモールド樹
脂により成形する手段と、それら信号伝達用リード底面
に接着されたポリイミド系絶縁テープを剥離した後、ケ
ミカルデフラッシュ工程にてフラッシュを除去し、各信
号伝達用リードの露出面にソルダーを鍍金する段階と、
を順次行なうことを特徴としている。
導体チップ下面とを絶縁性両面テープにより接着した
後、該絶縁性両面テープが熱硬化性テープの場合は、オ
ーブン内で150〜200℃に硬化させるとよい。
面と半導体チップ下面とを絶縁性両面テープにより接着
した後、該絶縁性両面テープが熱可塑性テープの場合
は、オーブン内で150〜450℃に硬化させるといよ
い。
面に露出された各信号伝達用リードを印刷回路基板上の
各パターンに合わせ、ソルダーリングを施して該半導体
パッケージを基板上に接続し、実装させる。
詳細に説明する。
パッケージの構成を示す縦断面図であり、(A)は一実
施例表示図を示し、(B)は他の実施例表示図を示す。
パッケージの底面図である。図3は、本発明に係るチッ
プ信号伝達用リードの配列状態を示す平面図である。
よび長さを有した2つのポリイミド系テープ15,25
が所定間隔をおいてそれぞれ2列に配列され、それらテ
ープ15,25上に所定間隔をおいて複数個の信号伝達
用リード13が接着され、それら信号伝達用リード13
の上面内方側にそれぞれ所定大きさの絶縁性両面テープ
16,26が接着され、それら絶縁性両面テープ16,
26によりそれら信号伝達用リード13上面に前記半導
体チップ11下面が接着され、それら信号伝達用リード
13上面外方側にそれぞれ所定大きさの導電バンプ1
8,28が配置されてそれらバンプ18,28により前
記各信号伝達用リード13上に前記半導体チップ11が
熱圧着され、該半導体チップ11が各信号伝達用リード
13上面に電気的に接続された後、それら信号伝達用リ
ード13、導電バンプ18,28、絶縁性両面テープ1
6,26および半導体チップ11の外方側周囲がモール
ド樹脂14により成形されて本発明に係るプラスチック
半導体パッケージの一実施例が構成されている(図1
(A)参照)。
(B)に示したように、各信号伝達用リード13上面外
方側と半導体チップ11下面間にそれぞれ絶縁性両面テ
ープ16,26が接着され、各信号伝達用リード13上
面内方側と半導体チップ11下面とをそれぞれ導電バン
プ18,28により熱圧着して半導体パッケージを構成
することもできる。
は、前記半導体チップ11の底面縁部内方側にそれぞれ
配列接着され、50ないし100μm程度にダウンセッ
ト(down−set)される。かつ、前記各絶縁性両
面テープ16,26は、70ないし150μm程度の厚
さを有する熱硬化性または熱可塑性のテープが使用され
る。また、前記各導電バンプ18,28は、ソルダーま
たは金が使用され、高さは20ないし50μm程度に形
成される。
パッケージの製造方法を説明すると次のようである。
た複数個の半導体パッケージのチップ信号伝達用リード
13底面にポリイミド系の絶縁テープ15,25をその
2列に合わせて接着し、それら信号伝達用リード13上
面に導電バンプ18,28をそれぞれ配置する段階と、
それら信号伝達用リード13上面の前記導電バンプ1
8,28の側方にそれぞれ絶縁性両面テープ16,26
を接着し、それら絶縁性両面テープ16,26上に半導
体チップ11下面を接着する段階と、それら半導体チッ
プ11下面を各導電バンプ18,28によりそれぞれ信
号伝達用リード13に熱圧着ボンディングし、半導体チ
ップ11を各信号伝達用リード13に電気的に接続する
段階と、それら信号伝達用リード13底面が外部に露出
されるようにそれら信号伝達用リード13、各導電バン
プ18,28、各絶縁性両面テープ16,26および半
導体チップ11の外方側周囲をモールド樹脂14により
成形する段階と、前記各信号伝達用リード13の底面に
接着されたポリイミド系絶縁テープ15,25を剥離し
た後、ケミカルデフラッシュ(chemical de
flash)工程によりフラッシュを除去し、各信号伝
達用リード13の露出面にソルダー(solder)を
鍍金する段階と、を順次行なうようになっている。
に前記導電バンプ18,28をそれぞれ配置するときは
通常のテープボンディング(Tape Automat
edBonding)方式が利用され、それら信号伝達
用リード13上面に半導体チップ11を接着するときは
LOC(Lead On Chip)パッケージ方式が
利用される。
各信号伝達用リード13と前記半導体チップ11間に接
着された各絶縁性両面テープ16,26を硬化させる
が、この場合、それら絶縁性両面テープ16,26が熱
硬化性テープであれば、半導体チップ11を接着した後
オーブン(oven)内で150〜200℃に硬化さ
せ、それら絶縁性両面テープ16,26が熱可塑性であ
ればオーブン内で150〜450℃に硬化させる。ま
た、前記信号伝達用リード13が半導体パッケージ成形
本体から露出される程度(高さ)は半導体パッケージの
成形面と同様とし、成形後それら露出面にソルダー鍍金
を施して、その鍍金の厚さだけ高く突成させる。
パッケージを基板上に実装する場合は、該半導体パッケ
ージの成形本体下面に露出された各信号伝達用リード1
3を前記基板上の各パターンに合わせ、ソルダーリング
を施して該基板上に接続すればよい。したがって、本発
明に係るプラスチック半導体パッケージは、軽薄短小で
高密度に実装し得るので、各種のカード(sram c
ard,dram card,module等)に適用
することができる。
体パッケージにおいては、半導体チップとインナーリー
ド間のワイヤボンディングが省かれ、半導体パッケージ
本体外方側に突成されるアウトリードが省かれ、複数個
の信号伝達用リードが各絶縁性両面テープおよび導電バ
ンプにより直接半導体チップに接着および接続して構成
されているため、軽薄短小化され、基板上の実装率が向
上されるという効果がある。
ーミング工程が省かれるので、半導体パッケージの割れ
および界面剥離現象が減少され、生産性の向上および原
価の低廉化を図り得る効果がある。
構成を示す縦断面図である。
底面図である。
態を示す平面図である。
示す断面図である。
す。
Claims (10)
- 【請求項1】 半導体チップとインナーリードとを電気
的に連結する金属ワイヤが省かれたプラスチック半導体
パッケージであって、 前記半導体チップ下面に電気的に接続され、成形後底面
が外部に露出される複数個の信号伝達用リードと、 それら信号伝達用リードの上面内方側に接着され、それ
ら信号伝達用リードを前記半導体チップ下面にそれぞれ
接着させる複数個の絶縁性両面テープと、 前記各信号伝達用リードの底面が列状に接着されるポリ
イミド系絶縁テープと、 前記各信号伝達用リードの上面外方側と前記半導体チッ
プ下面所定部位とをそれぞれ電気的に接続する複数個の
導電バンプと、 それら信号伝達用リード、絶縁性両面テープ、導電バン
プおよび半導体チップの外方側周囲に形成される、形成
用モールド樹脂と、 を備えるプラスチック半導体パッケージ。 - 【請求項2】 前記信号伝達用リードは、前記半導体チ
ップ下面縁部内方面に、50ないし100μm程度にそ
れぞれダウンセットされる、請求項1記載のプラスチッ
ク半導体パッケージ。 - 【請求項3】 前記絶縁性両面テープは、熱硬化性また
は熱可塑性のテープである、請求項1記載のプラスチッ
ク半導体パッケージ。 - 【請求項4】 前記絶縁性両面テープは、70ないし1
50μm程度の厚さを有する、請求項1または請求項3
記載のプラスチック半導体パッケージ。 - 【請求項5】 前記導電バンプは、ソルダーまたは金に
てなる、請求項1記載のプラスチック半導体パッケー
ジ。 - 【請求項6】 前記導電バンプは、高さが20ないし5
0μmにて形成される、請求項1または請求項5記載の
プラスチック半導体パッケージ。 - 【請求項7】 前記各信号伝達用リード上面外方側と前
記半導体チップ下面間に前記絶縁性両面テープがそれぞ
れ接着され、それら信号伝達用リード上面内方側と半導
体チップ下面間に前記導電バンプがそれぞれ接続され
る、請求項1記載のプラスチック半導体パッケージ。 - 【請求項8】 ポリイミド系の絶縁テープ上に複数個の
半導体パッケージチップ信号伝達用リードをそれぞれ接
着し、それら信号伝達用リード上面に導電バンプをそれ
ぞれ配置する手段と、 それら信号伝達用リード上面の導電バンプ側方に絶縁性
両面テープをそれぞれ接着し、それら絶縁性両面テープ
上面に半導体チップ下面を接着する段階と、 該半導体チップ下面と各信号伝達用リード上面とを各導
電バンプにより熱圧着ボンディングし、半導体チップを
各信号伝達リードに電気的に接続する手段と、 それら信号伝達用リード底面が露出されるように、それ
ら信号伝達用リード、導電バンプ、絶縁性両面テープお
よび半導体チップの外方側周囲をモールド樹脂により成
形する手段と、 それら信号伝達用リード底面に接着されたポリイミド系
絶縁テープを剥離した後、ケミカルデフラッシュ工程に
てフラッシュを除去し、各信号伝達用リードの露出面に
ソルダーを鍍金する段階と、 を順次行なう、プラスチック半導体パッケージの製造方
法。 - 【請求項9】 前記各信号伝達用リード上面と半導体チ
ップ下面とを前記絶縁性両面テープにより接着した後、
該絶縁性両面テープが熱硬化性テープの場合は、オーブ
ン内で150〜200℃に硬化させる、請求項8記載の
プラスチック半導体パッケージの製造方法。 - 【請求項10】 前記各信号伝達用リード上面と半導体
チップ下面とを絶縁性両面テープにより接着した後、該
絶縁性両面テープが熱可塑性テープの場合は、オーブン
内で150〜450℃に硬化させる、請求項8記載のプ
ラスチック半導体パッケージの製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930011506A KR0152901B1 (ko) | 1993-06-23 | 1993-06-23 | 플라스틱 반도체 패키지 및 그 제조방법 |
KR93P11506 | 1993-06-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0722474A true JPH0722474A (ja) | 1995-01-24 |
JP3454920B2 JP3454920B2 (ja) | 2003-10-06 |
Family
ID=19357883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13981294A Expired - Fee Related JP3454920B2 (ja) | 1993-06-23 | 1994-06-22 | 半導体パッケージおよびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5444301A (ja) |
JP (1) | JP3454920B2 (ja) |
KR (1) | KR0152901B1 (ja) |
DE (1) | DE4421077B4 (ja) |
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1994
- 1994-06-16 DE DE19944421077 patent/DE4421077B4/de not_active Expired - Fee Related
- 1994-06-16 US US08/260,571 patent/US5444301A/en not_active Expired - Lifetime
- 1994-06-22 JP JP13981294A patent/JP3454920B2/ja not_active Expired - Fee Related
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US5554556A (en) * | 1990-07-09 | 1996-09-10 | Fujitsu Limited | Method of making a semiconductor memory device having an increased capacitance of memory cell |
JPH0945818A (ja) * | 1995-08-02 | 1997-02-14 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
US6208021B1 (en) | 1996-03-27 | 2001-03-27 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device |
US6403398B2 (en) | 1996-03-27 | 2002-06-11 | Oki Electric Industry Co, Ltd. | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device |
JPH10116935A (ja) * | 1996-10-08 | 1998-05-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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DE4421077B4 (de) | 2007-01-04 |
JP3454920B2 (ja) | 2003-10-06 |
KR950002000A (ko) | 1995-01-04 |
US5444301A (en) | 1995-08-22 |
KR0152901B1 (ko) | 1998-10-01 |
DE4421077A1 (de) | 1995-01-05 |
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