KR950002000A - 플라스틱 반도체 패키지 및 그 제조방법 - Google Patents
플라스틱 반도체 패키지 및 그 제조방법 Download PDFInfo
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- KR950002000A KR950002000A KR1019930011506A KR930011506A KR950002000A KR 950002000 A KR950002000 A KR 950002000A KR 1019930011506 A KR1019930011506 A KR 1019930011506A KR 930011506 A KR930011506 A KR 930011506A KR 950002000 A KR950002000 A KR 950002000A
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 새로운 타입의 리드 배면 노출형 플라스틱 반도체 패키지의 구조 및 그 제조방법에 관한 것이다. 일반적인 플라스틱 반도체 패키지는 기판연결리드인 아웃리드를 패키지 몸체의 양외측으로 돌출시킴과 아울러 칩과 리드프레임의 인너리드를 금속세선으로 연결하여 구성함으로써 패키지의 크기가 커지게 되고 고밀도 실장을 이룰 수 있으며, 복잡한 제조공정으로 제조원가가 상승하는 등의 단점이 있었다. 이를 감안하여 창안한 본 발명은 반도체 칩(11)을 내장한 패키지 몸체(12)의 하면으로 상기 칩(11)의 외부로의 전기적 접속 경로인 다수개의 칩신호 전달용 리드(13)를 노출시켜 구성하고, 상기 칩(11)과 다수개의 칩신호 전달용 리드(13)를 도전펌프(14)로 전기적으로 접속 연결시켜 구성함으로써 패키지의 경·박·단·소형화 및 고밀도실장을 이루고, 제조공정을 간소화하며, 패키지의 전기적인 특성을 개선함과 아울러 취급이 용이하도록 구성한 것이다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도 내지 제 4 도는 본 발명에 의한 플라스틱 반도체 패키지를 설명하기 위한 도면으로서, 제 2 도의 (가)(나)는 본 발명 플라스틱 반도체 패키지의 구조를 보인 단면도이고, 제 3 도는 본 발명 플라스틱 반도체 패키지의 저면도이며, 제 4 도는 본 발명에 사용되는 칩신호 전달용 리드의 배열상태를 보인 평면도이다.
Claims (6)
- 반도체 칩(11)을 내장한 패키지 몸체(12)의 하면으로 상기 칩(11)의 외부로의 전기적 접속 경로인 다수개의 칩신호 전달용 리드(13)를 노출시켜 구성하고, 상기 칩(11)과 다수개의 칩신호 전달용 리드(13)를 도전범프(14)를 이용하여 전기적을 접속 연결시킨 것을 특징으로 하는 플라스틱 반도체 패키지.
- 제 1 항에 있어서, 다수개의 칩신호 전달용 리드(13)들은 폴리이미드계 테이프(15)(15´)위에 일정간격으로 부착·배열되고, 상기 리드(13)들의 상면에는 반도체칩(11)이 절연성 양면테이프(16)(16´)에 의해 부착·고정됨을 특징으로 하는 플라스틱 반도체 패키지.
- 제 2 항에 있어서, 상기 칩신호 전달용 리드(13)들은 그 위에 탑재되는 칩(11)의 양측 외곽을 벗어나지 않는 크기로 형성되고, 50~100㎛ 정도로 다운-셋(Down-Set)됨을 특징으로 하는 플라스틱 반도체 패키지.
- 제 2 항에 있어서, 상기 절연성 양면테이프(16)(16´)는 70~150㎛ 정도의 두께를 갖는 열경화성 또는 열가소성 테이프인 것을 특징으로 하는 플라스틱 반도체 패키지.
- 제 1 항에 있어서, 상기 도전범프(14)는 솔더, 또는 금을 주성분으로 하여 20~50㎛ 정도의 높이로 형성됨을 특징으로 하는 플라스틱 반도체 패키지.
- 반도체 칩(11)의 각 본드패드위에 도전범프(14)를 형성한 후 이 칩(11)을 폴리이미드계 테이프(15)(15´)위에 일정간격으로 부착 배열된 다수개의 칩신호 전달용 리드(13)위에 절연성 양면 테이프(16)(16´)를 이용하여 부착, 고정함과 아울러 상기 칩(11)의 도전 범프(14)와 이에 대응하는 각각의 칩신호 전달용 리드(13)를 열압착 본딩하여 전기적으로 접속시키는 단계와, 상기 다수개의 칩신호 전달용 리드(13)들이 하면으로 노출되도록 상기 칩(11)을 포함하는 일정면적을 몰드수지로 몰딩하여 패키지 몸체(12)를 형성하는 단계 및, 상기 칩신호 전달용 리드(13)들의 하면에 부착된 폴리이미드계 테이프(15)(15´)를 분리시킨 후 케미컬 디플래쉬 공정을 진행하여 플러쉬를 제러함과 아울러 리드(13) 노출면에 솔더를 플래팅 하는 단계로 진행하여 구성함을 특징으로 하는 플라스틱 반도체 패키지 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930011506A KR0152901B1 (ko) | 1993-06-23 | 1993-06-23 | 플라스틱 반도체 패키지 및 그 제조방법 |
DE19944421077 DE4421077B4 (de) | 1993-06-23 | 1994-06-16 | Halbleitergehäuse und Verfahren zu dessen Herstellung |
US08/260,571 US5444301A (en) | 1993-06-23 | 1994-06-16 | Semiconductor package and method for manufacturing the same |
JP13981294A JP3454920B2 (ja) | 1993-06-23 | 1994-06-22 | 半導体パッケージおよびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930011506A KR0152901B1 (ko) | 1993-06-23 | 1993-06-23 | 플라스틱 반도체 패키지 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950002000A true KR950002000A (ko) | 1995-01-04 |
KR0152901B1 KR0152901B1 (ko) | 1998-10-01 |
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ID=19357883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019930011506A KR0152901B1 (ko) | 1993-06-23 | 1993-06-23 | 플라스틱 반도체 패키지 및 그 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5444301A (ko) |
JP (1) | JP3454920B2 (ko) |
KR (1) | KR0152901B1 (ko) |
DE (1) | DE4421077B4 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100583494B1 (ko) * | 2000-03-25 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
Families Citing this family (173)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0468566A (ja) * | 1990-07-09 | 1992-03-04 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5866951A (en) * | 1990-10-12 | 1999-02-02 | Robert Bosch Gmbh | Hybrid circuit with an electrically conductive adhesive |
US5677566A (en) * | 1995-05-08 | 1997-10-14 | Micron Technology, Inc. | Semiconductor chip package |
JP3565454B2 (ja) * | 1995-08-02 | 2004-09-15 | 大日本印刷株式会社 | 樹脂封止型半導体装置 |
JP3467611B2 (ja) * | 1995-09-29 | 2003-11-17 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
JP3189703B2 (ja) * | 1996-10-08 | 2001-07-16 | 富士通株式会社 | 半導体装置及びその製造方法 |
KR0179803B1 (ko) * | 1995-12-29 | 1999-03-20 | 문정환 | 리드노출형 반도체 패키지 |
JPH09260538A (ja) * | 1996-03-27 | 1997-10-03 | Miyazaki Oki Electric Co Ltd | 樹脂封止型半導体装置及び製造方法とその実装構造 |
JP3427874B2 (ja) * | 1996-05-16 | 2003-07-22 | 沖電気工業株式会社 | 樹脂封止型半導体装置とその製造方法 |
KR0179925B1 (ko) * | 1996-06-14 | 1999-03-20 | 문정환 | 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지 |
KR100206910B1 (ko) * | 1996-06-14 | 1999-07-01 | 구본준 | 반도체 패키지의 디플래쉬 방법 |
KR0179924B1 (ko) * | 1996-06-14 | 1999-03-20 | 문정환 | 버텀리드 반도체 패키지 |
US6881611B1 (en) * | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
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Publication number | Priority date | Publication date | Assignee | Title |
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KR100583494B1 (ko) * | 2000-03-25 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
Also Published As
Publication number | Publication date |
---|---|
DE4421077B4 (de) | 2007-01-04 |
JPH0722474A (ja) | 1995-01-24 |
KR0152901B1 (ko) | 1998-10-01 |
DE4421077A1 (de) | 1995-01-05 |
JP3454920B2 (ja) | 2003-10-06 |
US5444301A (en) | 1995-08-22 |
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