KR950002000A - 플라스틱 반도체 패키지 및 그 제조방법 - Google Patents

플라스틱 반도체 패키지 및 그 제조방법 Download PDF

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KR950002000A
KR950002000A KR1019930011506A KR930011506A KR950002000A KR 950002000 A KR950002000 A KR 950002000A KR 1019930011506 A KR1019930011506 A KR 1019930011506A KR 930011506 A KR930011506 A KR 930011506A KR 950002000 A KR950002000 A KR 950002000A
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chip
leads
signal transfer
package
semiconductor package
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KR1019930011506A
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KR0152901B1 (ko
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윤치중
차기본
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문정환
금성일렉트론 주식회사
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Priority to KR1019930011506A priority Critical patent/KR0152901B1/ko
Priority to DE19944421077 priority patent/DE4421077B4/de
Priority to US08/260,571 priority patent/US5444301A/en
Priority to JP13981294A priority patent/JP3454920B2/ja
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Publication of KR0152901B1 publication Critical patent/KR0152901B1/ko

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    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Abstract

본 발명은 새로운 타입의 리드 배면 노출형 플라스틱 반도체 패키지의 구조 및 그 제조방법에 관한 것이다. 일반적인 플라스틱 반도체 패키지는 기판연결리드인 아웃리드를 패키지 몸체의 양외측으로 돌출시킴과 아울러 칩과 리드프레임의 인너리드를 금속세선으로 연결하여 구성함으로써 패키지의 크기가 커지게 되고 고밀도 실장을 이룰 수 있으며, 복잡한 제조공정으로 제조원가가 상승하는 등의 단점이 있었다. 이를 감안하여 창안한 본 발명은 반도체 칩(11)을 내장한 패키지 몸체(12)의 하면으로 상기 칩(11)의 외부로의 전기적 접속 경로인 다수개의 칩신호 전달용 리드(13)를 노출시켜 구성하고, 상기 칩(11)과 다수개의 칩신호 전달용 리드(13)를 도전펌프(14)로 전기적으로 접속 연결시켜 구성함으로써 패키지의 경·박·단·소형화 및 고밀도실장을 이루고, 제조공정을 간소화하며, 패키지의 전기적인 특성을 개선함과 아울러 취급이 용이하도록 구성한 것이다.

Description

플라스틱 반도체 패키지 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도 내지 제 4 도는 본 발명에 의한 플라스틱 반도체 패키지를 설명하기 위한 도면으로서, 제 2 도의 (가)(나)는 본 발명 플라스틱 반도체 패키지의 구조를 보인 단면도이고, 제 3 도는 본 발명 플라스틱 반도체 패키지의 저면도이며, 제 4 도는 본 발명에 사용되는 칩신호 전달용 리드의 배열상태를 보인 평면도이다.

Claims (6)

  1. 반도체 칩(11)을 내장한 패키지 몸체(12)의 하면으로 상기 칩(11)의 외부로의 전기적 접속 경로인 다수개의 칩신호 전달용 리드(13)를 노출시켜 구성하고, 상기 칩(11)과 다수개의 칩신호 전달용 리드(13)를 도전범프(14)를 이용하여 전기적을 접속 연결시킨 것을 특징으로 하는 플라스틱 반도체 패키지.
  2. 제 1 항에 있어서, 다수개의 칩신호 전달용 리드(13)들은 폴리이미드계 테이프(15)(15´)위에 일정간격으로 부착·배열되고, 상기 리드(13)들의 상면에는 반도체칩(11)이 절연성 양면테이프(16)(16´)에 의해 부착·고정됨을 특징으로 하는 플라스틱 반도체 패키지.
  3. 제 2 항에 있어서, 상기 칩신호 전달용 리드(13)들은 그 위에 탑재되는 칩(11)의 양측 외곽을 벗어나지 않는 크기로 형성되고, 50~100㎛ 정도로 다운-셋(Down-Set)됨을 특징으로 하는 플라스틱 반도체 패키지.
  4. 제 2 항에 있어서, 상기 절연성 양면테이프(16)(16´)는 70~150㎛ 정도의 두께를 갖는 열경화성 또는 열가소성 테이프인 것을 특징으로 하는 플라스틱 반도체 패키지.
  5. 제 1 항에 있어서, 상기 도전범프(14)는 솔더, 또는 금을 주성분으로 하여 20~50㎛ 정도의 높이로 형성됨을 특징으로 하는 플라스틱 반도체 패키지.
  6. 반도체 칩(11)의 각 본드패드위에 도전범프(14)를 형성한 후 이 칩(11)을 폴리이미드계 테이프(15)(15´)위에 일정간격으로 부착 배열된 다수개의 칩신호 전달용 리드(13)위에 절연성 양면 테이프(16)(16´)를 이용하여 부착, 고정함과 아울러 상기 칩(11)의 도전 범프(14)와 이에 대응하는 각각의 칩신호 전달용 리드(13)를 열압착 본딩하여 전기적으로 접속시키는 단계와, 상기 다수개의 칩신호 전달용 리드(13)들이 하면으로 노출되도록 상기 칩(11)을 포함하는 일정면적을 몰드수지로 몰딩하여 패키지 몸체(12)를 형성하는 단계 및, 상기 칩신호 전달용 리드(13)들의 하면에 부착된 폴리이미드계 테이프(15)(15´)를 분리시킨 후 케미컬 디플래쉬 공정을 진행하여 플러쉬를 제러함과 아울러 리드(13) 노출면에 솔더를 플래팅 하는 단계로 진행하여 구성함을 특징으로 하는 플라스틱 반도체 패키지 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930011506A 1993-06-23 1993-06-23 플라스틱 반도체 패키지 및 그 제조방법 KR0152901B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019930011506A KR0152901B1 (ko) 1993-06-23 1993-06-23 플라스틱 반도체 패키지 및 그 제조방법
DE19944421077 DE4421077B4 (de) 1993-06-23 1994-06-16 Halbleitergehäuse und Verfahren zu dessen Herstellung
US08/260,571 US5444301A (en) 1993-06-23 1994-06-16 Semiconductor package and method for manufacturing the same
JP13981294A JP3454920B2 (ja) 1993-06-23 1994-06-22 半導体パッケージおよびその製造方法

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KR1019930011506A KR0152901B1 (ko) 1993-06-23 1993-06-23 플라스틱 반도체 패키지 및 그 제조방법

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KR0152901B1 KR0152901B1 (ko) 1998-10-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지

Families Citing this family (173)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468566A (ja) * 1990-07-09 1992-03-04 Fujitsu Ltd 半導体装置及びその製造方法
US5866951A (en) * 1990-10-12 1999-02-02 Robert Bosch Gmbh Hybrid circuit with an electrically conductive adhesive
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
JP3565454B2 (ja) * 1995-08-02 2004-09-15 大日本印刷株式会社 樹脂封止型半導体装置
JP3467611B2 (ja) * 1995-09-29 2003-11-17 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
JP3189703B2 (ja) * 1996-10-08 2001-07-16 富士通株式会社 半導体装置及びその製造方法
KR0179803B1 (ko) * 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
JPH09260538A (ja) * 1996-03-27 1997-10-03 Miyazaki Oki Electric Co Ltd 樹脂封止型半導体装置及び製造方法とその実装構造
JP3427874B2 (ja) * 1996-05-16 2003-07-22 沖電気工業株式会社 樹脂封止型半導体装置とその製造方法
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
KR100206910B1 (ko) * 1996-06-14 1999-07-01 구본준 반도체 패키지의 디플래쉬 방법
KR0179924B1 (ko) * 1996-06-14 1999-03-20 문정환 버텀리드 반도체 패키지
US6881611B1 (en) * 1996-07-12 2005-04-19 Fujitsu Limited Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device
EP1189271A3 (en) * 1996-07-12 2003-07-16 Fujitsu Limited Wiring boards and mounting of semiconductor devices thereon
JP3284262B2 (ja) * 1996-09-05 2002-05-20 セイコーエプソン株式会社 液晶表示装置及びそれを用いた電子機器
EP0844665A3 (en) * 1996-11-21 1999-10-27 Texas Instruments Incorporated Wafer level packaging
KR100239708B1 (ko) * 1996-11-27 2000-01-15 김영환 비엘피 패키지의 제조방법
DE19708617C2 (de) * 1997-03-03 1999-02-04 Siemens Ag Chipkartenmodul und Verfahren zu seiner Herstellung sowie diesen umfassende Chipkarte
US5777705A (en) * 1997-05-30 1998-07-07 International Business Machines Corporation Wire bond attachment of a liquid crystal display tile to a tile carrier
JP3881751B2 (ja) 1997-08-20 2007-02-14 沖電気工業株式会社 半導体チップの実装構造および実装方法
US7247526B1 (en) 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US8330270B1 (en) 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
US7226811B1 (en) 1998-06-10 2007-06-05 Asat Ltd. Process for fabricating a leadless plastic chip carrier
US7270867B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier
US6635957B2 (en) * 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6872661B1 (en) 1998-06-10 2005-03-29 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US7271032B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6989294B1 (en) 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6933594B2 (en) * 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7071541B1 (en) 1998-06-24 2006-07-04 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7112474B1 (en) 1998-06-24 2006-09-26 Amkor Technology, Inc. Method of making an integrated circuit package
US6893900B1 (en) 1998-06-24 2005-05-17 Amkor Technology, Inc. Method of making an integrated circuit package
US7030474B1 (en) 1998-06-24 2006-04-18 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7005326B1 (en) 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7332375B1 (en) 1998-06-24 2008-02-19 Amkor Technology, Inc. Method of making an integrated circuit package
US6448633B1 (en) * 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
KR20010037247A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
KR100379089B1 (ko) 1999-10-15 2003-04-08 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지
KR100403142B1 (ko) * 1999-10-15 2003-10-30 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR100526844B1 (ko) * 1999-10-15 2005-11-08 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US20070176287A1 (en) * 1999-11-05 2007-08-02 Crowley Sean T Thin integrated circuit device packages for improved radio frequency performance
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
DE19955537B4 (de) * 1999-11-18 2006-04-13 Orga Kartensysteme Gmbh Verfahren zur Herstellung eines Trägerelementes für einen IC-Baustein
KR100421774B1 (ko) 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
US6639308B1 (en) * 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
US7042068B2 (en) * 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6300674B1 (en) * 2000-06-19 2001-10-09 Harvatek Corp. Flat package for semiconductor diodes
US6840777B2 (en) * 2000-11-30 2005-01-11 Intel Corporation Solderless electronics packaging
KR20020058209A (ko) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 반도체패키지
KR100731007B1 (ko) * 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지
US6657132B2 (en) * 2001-03-15 2003-12-02 Micron Technology, Inc. Single sided adhesive tape for compound diversion on BOC substrates
US6967395B1 (en) 2001-03-20 2005-11-22 Amkor Technology, Inc. Mounting for a package containing a chip
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
KR100393448B1 (ko) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7045883B1 (en) 2001-04-04 2006-05-16 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US7064009B1 (en) 2001-04-04 2006-06-20 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US7485952B1 (en) 2001-09-19 2009-02-03 Amkor Technology, Inc. Drop resistant bumpers for fully molded memory cards
US6900527B1 (en) 2001-09-19 2005-05-31 Amkor Technology, Inc. Lead-frame method and assembly for interconnecting circuits within a circuit module
US6630726B1 (en) 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US7732914B1 (en) 2002-09-03 2010-06-08 Mclellan Neil Cavity-type integrated circuit package
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7190062B1 (en) 2004-06-15 2007-03-13 Amkor Technology, Inc. Embedded leadframe semiconductor package
US7361533B1 (en) 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6927483B1 (en) 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US7001799B1 (en) 2003-03-13 2006-02-21 Amkor Technology, Inc. Method of making a leadframe for semiconductor devices
US7095103B1 (en) 2003-05-01 2006-08-22 Amkor Technology, Inc. Leadframe based memory card
US6879034B1 (en) 2003-05-01 2005-04-12 Amkor Technology, Inc. Semiconductor package including low temperature co-fired ceramic substrate
US7008825B1 (en) 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US6897550B1 (en) 2003-06-11 2005-05-24 Amkor Technology, Inc. Fully-molded leadframe stand-off feature
TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
KR100506035B1 (ko) * 2003-08-22 2005-08-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
US7245007B1 (en) 2003-09-18 2007-07-17 Amkor Technology, Inc. Exposed lead interposer leadframe package
US6921967B2 (en) * 2003-09-24 2005-07-26 Amkor Technology, Inc. Reinforced die pad support structure
US7138707B1 (en) 2003-10-21 2006-11-21 Amkor Technology, Inc. Semiconductor package including leads and conductive posts for providing increased functionality
US7144517B1 (en) 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
US7211879B1 (en) 2003-11-12 2007-05-01 Amkor Technology, Inc. Semiconductor package with chamfered corners and method of manufacturing the same
US7009286B1 (en) 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
US7057268B1 (en) 2004-01-27 2006-06-06 Amkor Technology, Inc. Cavity case with clip/plug for use on multi-media card
US7091594B1 (en) 2004-01-28 2006-08-15 Amkor Technology, Inc. Leadframe type semiconductor package having reduced inductance and its manufacturing method
US20080003722A1 (en) * 2004-04-15 2008-01-03 Chun David D Transfer mold solution for molded multi-media card
US7091581B1 (en) 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
US7411289B1 (en) 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US7202554B1 (en) 2004-08-19 2007-04-10 Amkor Technology, Inc. Semiconductor package and its manufacturing method
US7595225B1 (en) 2004-10-05 2009-09-29 Chun Ho Fan Leadless plastic chip carrier with contact standoff
US7217991B1 (en) 2004-10-22 2007-05-15 Amkor Technology, Inc. Fan-in leadframe semiconductor package
US7645640B2 (en) * 2004-11-15 2010-01-12 Stats Chippac Ltd. Integrated circuit package system with leadframe substrate
US7358119B2 (en) * 2005-01-12 2008-04-15 Asat Ltd. Thin array plastic package without die attach pad and process for fabricating the same
US7038321B1 (en) * 2005-04-29 2006-05-02 Delphi Technologies, Inc. Method of attaching a flip chip device and circuit assembly formed thereby
US7348663B1 (en) 2005-07-15 2008-03-25 Asat Ltd. Integrated circuit package and method for fabricating same
US7410830B1 (en) 2005-09-26 2008-08-12 Asat Ltd Leadless plastic chip carrier and method of fabricating same
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7772047B2 (en) * 2007-06-28 2010-08-10 Sandisk Corporation Method of fabricating a semiconductor die having a redistribution layer
US7763980B2 (en) * 2007-06-28 2010-07-27 Sandisk Corporation Semiconductor die having a distribution layer
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7868362B2 (en) * 2007-10-16 2011-01-11 Honeywell International Inc. SOI on package hypersensitive sensor
JP2009099709A (ja) * 2007-10-16 2009-05-07 Nec Electronics Corp 半導体装置
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8097929B2 (en) * 2008-05-23 2012-01-17 Chia-Sheng Lin Electronics device package and fabrication method thereof
US7791031B2 (en) * 2008-06-09 2010-09-07 Honeywell International Inc. Neutron detection structure
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US7838324B2 (en) * 2008-12-19 2010-11-23 Honeywell International Inc. Neutron detection structure and method of fabricating
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8153985B2 (en) * 2009-01-30 2012-04-10 Honeywell International Inc. Neutron detector cell efficiency
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
TW201311069A (zh) * 2011-08-25 2013-03-01 Hon Hai Prec Ind Co Ltd 晶片封裝件及晶片封裝方法
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
TWI556361B (zh) * 2012-12-11 2016-11-01 鴻海精密工業股份有限公司 鐳射晶片封裝結構
US9041226B2 (en) * 2013-03-13 2015-05-26 Infineon Technologies Ag Chip arrangement and a method of manufacturing a chip arrangement
USD759022S1 (en) 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
USD758372S1 (en) * 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
US9888283B2 (en) 2013-03-13 2018-02-06 Nagrastar Llc Systems and methods for performing transport I/O
USD729808S1 (en) 2013-03-13 2015-05-19 Nagrastar Llc Smart card interface
US9647997B2 (en) 2013-03-13 2017-05-09 Nagrastar, Llc USB interface for performing transport I/O
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
TWI628723B (zh) * 2015-03-10 2018-07-01 精材科技股份有限公司 一種晶片尺寸等級的感測晶片封裝體及其製造方法
USD780763S1 (en) 2015-03-20 2017-03-07 Nagrastar Llc Smart card interface
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface
JP1647727S (ko) * 2018-02-01 2019-12-09
USD930000S1 (en) 2018-10-12 2021-09-07 Huawei Technologies Co., Ltd. Memory card

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6094744A (ja) * 1983-10-27 1985-05-27 Nippon Denso Co Ltd 混成集積回路装置
US4604644A (en) * 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
JPS63254758A (ja) * 1987-04-13 1988-10-21 Tomoegawa Paper Co Ltd 半導体装置
JPH01161724A (ja) * 1987-12-18 1989-06-26 Citizen Watch Co Ltd 表面実装用半導体装置の製造方法
JPH01179334A (ja) * 1988-01-05 1989-07-17 Citizen Watch Co Ltd 半導体素子の実装方法
US4842662A (en) * 1988-06-01 1989-06-27 Hewlett-Packard Company Process for bonding integrated circuit components
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JP2895920B2 (ja) * 1990-06-11 1999-05-31 株式会社日立製作所 半導体装置及びその製造方法
JP2762792B2 (ja) * 1991-08-30 1998-06-04 日本電気株式会社 光半導体装置
KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지

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