JPH09129779A - 超微細電導極を有する半導体パッケージ - Google Patents

超微細電導極を有する半導体パッケージ

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Publication number
JPH09129779A
JPH09129779A JP25296A JP25296A JPH09129779A JP H09129779 A JPH09129779 A JP H09129779A JP 25296 A JP25296 A JP 25296A JP 25296 A JP25296 A JP 25296A JP H09129779 A JPH09129779 A JP H09129779A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor package
semiconductor substrate
fine
conductive electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25296A
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English (en)
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JP2844058B2 (ja
Inventor
Shinsei Kin
振聖 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
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Publication of JPH09129779A publication Critical patent/JPH09129779A/ja
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Publication of JP2844058B2 publication Critical patent/JP2844058B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes

Abstract

(57)【要約】 【課題】本発明の目的は、ソルダーボールを使用せず、
微細電極及びインターフェース電導体を用いて、生産性
を向上し得る超微細電導極を有した半導体パッケージを
提供しようとするものである。 【解決手段】エポキシ成形体の半導体基板下面露出部位
に複数の微細電極が形成され、そえら微細電極下面にイ
ンターフェース電導体が形成され、該インターフェース
電導体により印刷回路基板上の各微細電極に半導体パッ
ケージが電気的連結されるように、超微細電導極を有す
る半導体パッケージが構成される。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、超微細電導極を有
する半導体パッケージに係るもので、詳しくは、従来Ｂ
ＧＡ（Ball Grid Array ）半導体パッケージの電導性ボ
ールの代わりに、微細な電極及びインタフェース伝導体
を用い、生産性を向上させた超微細電導極を有する半導
体パッケージに関するものである。
【０００２】
【従来の技術】従来ＢＧＡ半導体パッケージにおいて
は、文献（１９９４年５月号、NEKKEIELECTRONICS 誌、
Ｐ４２−４５）に記載され、図３に示したように、半導
体基板１上に半導体チップ３を接着剤２により接着し、
該半導体チップ３上両方側部位と前記半導体基板１上の
導電部位（図示されず）とを金属ワイヤー４によりボン
ディングし、それら半導体基板１、半導体チップ３及び
金属ワイヤー４をエポキシ樹脂によりモールディングし
た後、該エポキシ成形体７の半導体基板１下面に電極端
子５を夫々露出させる。次いで、それら電極端子５にソ
ルダーボール６を夫々掛合し、リフロー（reflow）接合
を施してそれらソルダーボール６を半導体基板１下面の
電極端子５に夫々接着させていた。
【０００３】
【発明が解決しようとする課題】然るに、このような従
来ＢＧＡ半導体パッケージにおいては、半導体パッケー
ジの製造後に電気的検査を施し、電気的連結の不良状態
が発生した場合は、半導体パッケージ下面の各ソルダー
ボールを全て除去し、クリーニングを施した後、それら
ソルダーボールの付着工程を再施行するようになるた
め、極めて煩雑になり、生産性が低下するという不都合
な点があった。且つ、半導体パッケージ下面の電極露出
部位に各ソルダーボールを一々付着するようになってい
るため、それらソルダーボールの付着ピッチ間隔が１．
０−１．５ｍｍに制限され、それら付着動作が極めて煩
雑であるという不都合な点があった。
【０００４】
【課題を解決するための手段】本発明の目的は、従来の
ソルダーボールを使用せず、微細電極及びインタフェー
ス伝導体を用いて生産性を向上し得る超微細電導極を有
した半導体パッケージを提供しようとするものである。
叉、本発明の他の目的は、半導体パッケージの製造工程
を簡単化し、原価を減少し得る超微細電導極を有した半
導体パッケージを提供しようとするものである。
【０００５】そして、このような本発明の目的は、半導
体パッケージのエポキシ成形体基板下面露出部位に１．
０ｍｍ以下のピッチ間隔を有する複数の微細電極を形成
し、それら微細電極に対応して印刷回路基板上にも同様
な１．０ｍｍ以下のピッチ間隔を有する複数の微細電極
を形成し、それら微細電極間に厚さ５ー２００μｍ以下
の異方性電導フィールムと厚さ２００μｍ以下の光分解
性接着フィールムとでなるインタフェース伝導体を熱圧
着させ、超微細電極を有する半導体パッケージを構成す
ることにより達成される。
【０００６】
【発明の実施の形態】以下、本発明の実施の形態に対し
図面を用いて説明する。本発明に係る超微細電導極を有
する半導体パッケージにおいては、図１及び図２に示し
たように、先ず、半導体基板１１上中央部位に接着剤２
により半導体チップ３が接着され、それら半導体チップ
３両方側辺部位と半導体基板１１上所定部位とが金属ワ
イヤー４によりボンディングされ、エポキシモールディ
ングされた後該エポキシ成形体基板下面露出部位に複数
の微細電極１２が１ｍｍ以下のピッチ間隔を有し０．０
１ｃｍ2 程度の面積を有して形成される。このとき、そ
れら微細電極１２には金Ａｕ叉は銀Ａｇの鍍金が施され
る。
【０００７】次いで、それら微細電極１２の形成された
半導体基板１１下面叉は半導体下面全ての部位に５ー２
００μｍの厚さの異方性電導フィールム１３を熱圧着し
て複数の微細な可用性電導ボール１８を形成し、再びノ
ーブラックポリエステル系の光分解性接着フィールム１
４をコーティングして該異方性電導フィールム１３の寿
命を延長し得るインタフェース電導体が形成される。次
いで、印刷回路基板２０上に前記各微細電極１２に対応
する複数の微細電極１２ａが夫々所定ピッチ間隔を有し
て形成され、前記半導体パッケージ基板下面の各微細電
極１２を印刷回路基板２０上の各微細電極１２ａに連結
するとき、前記光分解性接着フィールム１４が露光に露
出され、ドライエッチングが施行されて連結される。
【０００８】
【発明の効果】以上説明したように、本発明に係る超微
細電導極を有する半導体パッケージにおいては、従来の
ソルダーボールを使用せず、微細電極とインターフェー
ス電導体とを用いて半導体パッケージを構成し、印刷回
路基板上に電気的連結し得るようになっているため、従
来半導体基板下面に一々ソルダーボールを付着した後、
電気的検査を施してソルダーボールの付着不良が発生し
た時、全てのソルダーボールを除去して再施行していた
煩雑な工程が省かれ、半導体パッケージの製造工程が簡
単化されて生産性が向上し、原価が低廉になるという効
果がある。
【図面の簡単な説明】
【図１】本発明に係る超微細電導極を有する半導体パッ
ケージの構造を示した概略縦断面図である。
【図２】本発明に係るインターフェース電導体を示した
図１Ａ部の縦断面図である。
【図３】従来ＢＧＡ半導体パッケージの構造を示した概
略縦断面図である。
【符号の説明】
１、１１：半導体基板 ３：半導体チップ ６：ソルダーボール ７：エポキシ成形体 １３：異方性電導フィールム １４：光分解性接着フィールム １８：電導ボール ２０：印刷回路基板

Claims (6)

    【特許請求の範囲】
  1. 【請求項１】超微細電導極を有する半導体パッケージで
    あって、 半導体基板上に接着された半導体チップと、該半導体チ
    ップと前記半導体基板上の導電部位とにボンディングさ
    れた金属ワイヤーと、それら半導体チップ、金属ワイヤ
    ー及び半導体基板上部がエポキシモールディングされて
    成形されたエポキシ成形体の半導体基板露出部位に夫々
    形成された複数の微細電極と、それら微細電極下面に形
    成され印刷回路基板上の微細電極に電気的連結されるイ
    ンタフェース伝導体と、を備えた超微細電導極を有する
    半導体パッケージ。
  2. 【請求項２】前記インタフェース伝導体は、前記半導体
    基板の各微細電極下面に熱圧着された異方性電導フィー
    ルムと光分解性接着フィールムとでなる請求項１記載の
    超微細電導極を有する半導体パッケージ。
  3. 【請求項３】前記各微細電極は、前記半導体基板下面に
    １ｍｍ以下のピッチ間隔を有して形成される請求項１記
    載の超微細電導極を有する半導体パッケージ。
  4. 【請求項４】前記各微細電極は、金Ａｎ叉は銀Ａｇにて
    鍍金される請求項１記載の超微細電導極を有する半導体
    パッケージ。
  5. 【請求項５】前記異方性電導フィールムは、５ー２００
    ｍｍの厚さに形成される請求項２記載の超微細電導極を
    有する半導体パッケージ。
  6. 【請求項６】前記光分解性接着フィールムは、２００μ
    ｍ以下の厚さに形成される請求項２記載の超微細電導極
    を有する半導体パッケージ。
JP25296A 1995-10-19 1996-01-05 半導体パッケージ Expired - Fee Related JP2844058B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
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CN103901236B (zh) * 2014-03-06 2016-04-20 广东工业大学 一种超精细无极金属丝栅网封装环

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US5877549A (en) 1999-03-02
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KR100201383B1 (ko) 1999-06-15

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