JP2844058B2 - 半導体パッケージ - Google Patents

半導体パッケージ

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Publication number
JP2844058B2
JP2844058B2 JP25296A JP25296A JP2844058B2 JP 2844058 B2 JP2844058 B2 JP 2844058B2 JP 25296 A JP25296 A JP 25296A JP 25296 A JP25296 A JP 25296A JP 2844058 B2 JP2844058 B2 JP 2844058B2
Authority
JP
Japan
Prior art keywords
semiconductor package
semiconductor
semiconductor substrate
fine electrodes
fine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25296A
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English (en)
Other versions
JPH09129779A (ja
Inventor
振聖 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ERU JII SEMIKON CO Ltd
Original Assignee
ERU JII SEMIKON CO Ltd
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Publication of JPH09129779A publication Critical patent/JPH09129779A/ja
Application granted granted Critical
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Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10719—Land grid array [LGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、微細電導極を有す
る半導体パッケージに係るもので、詳しくは、従来ＢＧ
Ａ（Ball Grid Array ）半導体パッケージの電導性ボー
ルの代わりに、微細な電極及びインタフェース伝導体を
用い、生産性を向上させた微細電導極を有する半導体パ
ッケージに関するものである。
【０００２】
【従来の技術】従来ＢＧＡ半導体パッケージにおいて
は、文献（１９９４年５月号、NEKKEI ELECTRONICS誌、
Ｐ４２−４５）に記載され、図４に示したように、半導
体基板１上に半導体チップ３を接着剤２により接着し、
該半導体チップ３上両側部位と前記半導体基板１上の導
電部位（図示されず）とを金属ワイヤー４によりボンデ
ィングし、それら半導体基板１、半導体チップ３及び金
属ワイヤー４をエポキシ樹脂によりモールディングした
後、該エポキシ成形体７の半導体基板１下面に電極端子
５を夫々露出させる。次いで、それら電極端子５にソル
ダーボール６を夫々掛合し、リフロー（reflow）接合を
施してそれらソルダーボール６を半導体基板１下面の電
極端子５に夫々接着させていた。
【０００３】
【発明が解決しようとする課題】然るに、このような従
来ＢＧＡ半導体パッケージにおいては、半導体パッケー
ジの製造後に電気的検査を施し、電気的連結の不良状態
が発生した場合は、半導体パッケージ下面の各ソルダー
ボール６を全て除去し、クリーニングを施した後、それ
らソルダーボール６の付着工程を再施行するようになる
ため、極めて煩雑になり、生産性が低下するという不都
合な点があった。
【０００４】且つ、半導体パッケージ下面の電極露出部
位５に各ソルダーボール６を一々付着するようになって
いるため、それらソルダーボール６の付着ピッチ間隔が
１．０〜１．５ｍｍに制限され、それら付着動作が極め
て煩雑であるという不都合な点があった。
【０００５】
【課題を解決するための手段】本発明の目的は、従来の
ソルダーボールを使用せず、微細電極及びインタフェー
ス伝導体を用いて生産性を向上し得る微細電導極を有し
た半導体パッケージを提供しようとするものである。
【０００６】また、本発明の他の目的は、半導体パッケ
ージの製造工程を簡単化し、原価を減少し得る微細電導
極を有した半導体パッケージを提供しようとするもので
ある。
【０００７】そして、このような本発明の目的は、半導
体パッケージのエポキシ成形体基板下面露出部位に１．
０ｍｍ以下のピッチ間隔を有する複数の微細電極を形成
し、それら微細電極に対応して印刷回路基板上にも同様
な１．０ｍｍ以下のピッチ間隔を有する複数の微細電極
を形成し、エポキシ成形体基板の微細電極に接する厚さ
５〜２００μｍ以下の異方性電導フィルムとその表面を
覆う厚さ２００μｍ以下の光分解性接着フィルムとでな
るインタフェース伝導体を熱圧着させて微細電極を有す
る半導体パッケージを構成することにより達成される。
【０００８】
【発明の実施の形態】以下、本発明の実施の形態に対し
図面を用いて説明する。本発明に係る微細電導極を有す
る半導体パッケージにおいては、図１から図３に示した
ように、先ず、半導体基板１１上中央部位に接着剤２に
より半導体チップ３が接着され、それら半導体チップ３
の両側辺部位と半導体基板１１上の所定部位とが金属ワ
イヤー４によりボンディングされ、エポキシモールディ
ングされた後該エポキシ成形体７の基板１１の下面露出
部位に複数の微細電極１２が１ｍｍ以下のピッチ間隔を
有しかつ０．０１ｃｍ2 程度の面積を有して形成され
る。このとき、それら微細電極１２には金（Ａｕ）また
は銀（Ａｇ）の鍍金が施される。
【０００９】次いで、半導体基板１１の下面でそれら微
細電極１２の形成された領域または半導体基板１１の下
面全ての領域に５〜２００μｍの厚さを有しかつ微細な
可溶性電導ボール（図３参照）を含む異方性電導フィル
ム１３を熱圧着し、さらにノボラックポリエステル系の
光分解性接着フィルム１４をコーティングして該異方性
電導フィルム１３の変質が防止され得るインタフェース
伝導体１５が形成される。次いで、印刷回路基板２０上
に前記各微細電極１２に対応する複数の微細電極１２ａ
が夫々所定ピッチ間隔を有して形成され、半導体パッケ
ージ基板１１下面の各微細電極１２を異方性電導フィル
ム１３を介して印刷回路基板２０上の各微細電極１２ａ
に連結するとき、前記光分解性接着フィルム１４が露光
に露出されかつ例えばドライエッチングが施行されて除
去された後に連結される。
【００１０】
【発明の効果】以上説明したように、本発明に係る微細
電導極を有する半導体パッケージにおいては、従来のソ
ルダーボールを使用せず、微細電極とインターフェース
伝導体とを用いて半導体パッケージを構成し、印刷回路
基板上に電気的連結し得るようになっているため、従来
半導体基板下面に一々ソルダーボールを付着した後、電
気的検査を施してソルダーボールの付着不良が発生した
時、全てのソルダーボールを除去して再施行していた煩
雑な工程が省かれ、半導体パッケージの製造工程が簡単
化されて生産性が向上し、原価が低廉になるという効果
がある。
【図面の簡単な説明】
【図１】本発明に係る微細電導極を有する半導体パッケ
ージの構造を示した概略縦断面図である。
【図２】本発明に係る微細電導極を有する半導体パッケ
ージを印刷回路基板に接合した状態を示した概略縦断面
図である。
【図３】本発明に係るインターフェース伝導体を示した
図１中のＡ部の拡大縦断面図である。
【図４】従来ＢＧＡ半導体パッケージの構造を示した概
略縦断面図である。
【符号の説明】
１、１１：半導体基板 ３：半導体チップ ６：ソルダーボール ７：エポキシ成形体 １３：異方性電導フィルム １４：光分解性接着フィルム １５：インターフェース伝導体 １８：電導ボール ２０：印刷回路基板

Claims (5)

    (57)【特許請求の範囲】
  1. 【請求項１】 半導体基板上に接着された半導体チップ
    と、該半導体チップと前記半導体基板上の導電部位とに
    ボンディングされた金属ワイヤーと、それら半導体チッ
    プ、金属ワイヤー及び半導体基板上部がエポキシモール
    ディングされて成形されたエポキシ成形体の半導体基板
    露出部位に夫々形成された複数の微細電極と、それら微
    細電極下面に形成されていてかつ印刷回路基板上の微細
    電極に電気的に連結されるべきインタフェース伝導体と
    を備えた半導体パッケージにおいて、 前記インタフェース伝導体は、前記半導体基板の各微細
    電極下面に熱圧着された異方性電導フィルムとその表面
    を覆う光分解性接着フィルムとを含み、前記光分解性接
    着フィルムは前記異方性電導フィルムが前記印刷回路基
    板上の微細電極に電気的に連結されるときには光照射と
    エッチングによって分解除去されるものであることを特
    徴とする半導体パッケージ。
  2. 【請求項２】 前記各微細電極は、前記半導体基板下面
    に１ｍｍ以下のピッチ間隔を有して形成されている請求
    項１に記載の半導体パッケージ。
  3. 【請求項３】 前記各微細電極は、金または銀にて鍍金
    されている請求項１または２に記載の半導体パッケー
    ジ。
  4. 【請求項４】 前記異方性電導フィルムは、５〜２００
    μｍの厚さに形成されている請求項１から３のいずれか
    の項に記載の半導体パッケージ。
  5. 【請求項５】 前記光分解性接着フィルムは、２００μ
    ｍ以下の厚さに形成されている請求項１から４のいずれ
    かの項に記載の半導体パッケージ。
JP25296A 1995-10-19 1996-01-05 半導体パッケージ Expired - Fee Related JP2844058B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950036163A KR100201383B1 (ko) 1995-10-19 1995-10-19 인터페이스 조립체를 구비한 유에프비지에이 패키지
KR95P36163 1995-10-19

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JP2844058B2 true JP2844058B2 (ja) 1999-01-06

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CN103901236B (zh) * 2014-03-06 2016-04-20 广东工业大学 一种超精细无极金属丝栅网封装环

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KR970024032A (ko) 1997-05-30
JPH09129779A (ja) 1997-05-16
KR100201383B1 (ko) 1999-06-15
US5877549A (en) 1999-03-02

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