CN102543767B - 一种在晶圆级封装的塑封工序中避免晶圆破损的方法 - Google Patents

一种在晶圆级封装的塑封工序中避免晶圆破损的方法 Download PDF

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CN102543767B
CN102543767B CN201010590130.7A CN201010590130A CN102543767B CN 102543767 B CN102543767 B CN 102543767B CN 201010590130 A CN201010590130 A CN 201010590130A CN 102543767 B CN102543767 B CN 102543767B
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wafer
plastic packaging
packaging material
grinding
chip
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CN102543767A (zh
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黄平
吴瑞生
陈益
段磊
陈伟
鲍利华
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
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Abstract

本发明涉及一种在晶圆级封装体的制备过程中,避免晶圆在其晶圆级封装的塑封工序中破损的方法。由于晶圆正面的划片槽的存在,固化前具有流动性的塑封料易于从划片槽中溢出,产生位于晶圆边缘处的溢胶,如果外溢的塑封料将晶圆和塑封模具的夹具黏接在一起,一旦将夹具与晶圆进行分离就会导致晶圆的破损。本发明先对晶圆的边缘进行研磨,形成环绕在晶圆边缘处的凹陷于晶圆正面的一环形研磨槽,再进行塑封,能有效防止塑封料溢出。

Description

一种在晶圆级封装的塑封工序中避免晶圆破损的方法
技术领域
本发明一般涉及一种晶圆级封装体的制备方法,更确切的说,本发明涉及一种在晶圆级封装体的制备过程中,避免晶圆在其晶圆级封装的塑封工序中破损的方法。
背景技术
不同于传统的芯片封装方式,晶圆级封装WLCSP(Wafer Level ChipScale Packaging)是先在整片晶圆上进行封装和测试,然后才切割成一个个的IC颗粒,因此封装后的封装体的体积即几乎等同于裸芯片的原尺寸。
通常,通过切割晶圆(Wafer Saw)以将诸多芯片(Die)从晶圆上分离,此过程中切割刀的切割线路是依赖于布置在晶圆上的划片槽(Scribe Line)。
在晶圆级封装的塑封工艺中,塑封料的起始状态为液态或加热后为液态并在冷却后进行固化。为了保障注塑于晶圆表面的塑封料具有预定的塑封密度,液态的塑封料在塑封模具内必须具有一定的注塑压力,然而,划片槽的存在所带来的问题是,固化前具有流动性的塑封料易于从划片槽中溢出,产生位于晶圆边缘处的溢胶(Molding Bleeding),如果外溢的塑封料将晶圆和塑封模具的夹具黏接在一起,则晶圆在完成塑封后,一旦将夹具与晶圆进行分离就会导致晶圆的破损。并且,由于部分塑封料从晶圆的划片槽中溢出,余下的塑封料则不足以完全覆盖晶圆的正面,或是其塑封密度较低。
另一方面,在当前的晶圆级封装的塑封工艺中,塑封模具的环形夹具按压在晶圆正面的边缘处,并用来固定晶圆,塑封完成后环形夹具与晶圆分离。如此,则晶圆正面的边缘部分仍然是裸露的而没有被塑封料覆盖,在随后的晶圆减薄时,该边缘部分极易破碎,并影响邻近晶圆边缘处的正常芯片。
专利号为US6107164的美国专利公开了一种晶圆级封装的半导体器件及半导体器件的制造方法,其制作流程参见本申请附图1A-1D(分别引用原申请附图3B、3D、4B、4C),这种方法是制作晶圆级封装体的例子。产品的电极4是在晶圆10上的焊垫2上制作的,电极4与焊垫2通过铜互连线3连接。带有凸点电极4的晶圆10表面完全被树脂23包封起来,对树脂23抛光直到凸点电极4暴露出来并在凸点电极4上植球。之后,再按照之前的切割槽22将塑封好的晶圆10进行切割分离,形成晶圆级封装体1。此过程中,树脂23完全固化前为液态并具有流动性,易于从切割槽22中溢出,如果溢出的树脂将晶圆10和塑封模具的夹具黏接,则晶圆10和夹具分离即导致晶圆10破损。并且,总量减少的树脂23难以完全覆盖晶圆10。该专利所公开的技术方案无法避免晶圆10在其塑封工序中易于破损的缺陷。
公开号为US20080044984的美国专利申请公开了一种背面发光器件工艺。在一种方法中,其制作流程参见本申请附图2A-2D(分别引用原申请附图4A、4B、4C、4D)。在将晶圆2和承载基板4粘接前,先对晶圆2的边缘13进行处理,将晶圆2的边缘13切削成一个垂直的切面20,避免出现锋利的边缘。在另外一种方法里,晶圆的边缘处理安排在晶圆粘接到承载基板之后,在研磨晶圆背面前,用研磨的方法先去掉晶圆边缘处与承载基板粘接不好的部分。该专利申请的技术方案在于处理晶圆边缘与承载基板之间的粘附不佳的问题,但不涉及在晶圆级封装中对晶圆进行塑封的工艺。
我们所关注的领域:晶圆级封装的塑封工艺中,在减少塑封料溢出、预防晶圆破损,以及在解决晶圆的边缘不完全被塑封料覆盖的问题上,上述专利申请的方案或是当前已有的技术均难以有效的对其作出改善。
发明内容
鉴于上述问题,本发明提出了一种避免晶圆塑封工序中晶圆破损的方法,包括以下步骤:
提供一晶圆,晶圆的正面包含有多颗以划片槽相互界定边界的芯片;
沿划片槽切割晶圆以形成位于划片槽处的切割槽;
于晶圆的正面绕着晶圆的边缘进行研磨,形成环绕在晶圆边缘处的凹陷于晶圆正面的一环形研磨槽;
进行塑封工艺,于晶圆正面塑封晶圆并形成覆盖晶圆正面的塑封料。
上述的方法,还包括以下步骤:
研磨塑封料以减薄塑封料的厚度;
于晶圆背面进行研磨以减薄晶圆的厚度,并于减薄后的晶圆的背面外露出切割槽;
沿切割槽对晶圆及塑封料进行切割,形成多颗以塑封体塑封包覆所述芯片的晶圆级封装体。
上述的方法,在对晶圆的边缘进行研磨过程中,形成的所述研磨槽的深度大于所述划片槽的深度。
上述的方法,任一芯片的顶部均设置有连接芯片内部电路的多个焊垫以及凸出于晶圆正面的多个凸点电极;并且
凸点电极与焊垫通过设置在芯片顶部的金属互联层而电性连接。
上述的方法,进行晶圆级封装的塑封工艺过程中,利用所述塑封料塑封包覆所述凸点电极。
上述的方法,在研磨塑封料的过程中,将所述凸点电极从塑封料中予以外露。
上述的方法,在完成研磨塑封料之后,还包括在外露于塑封料的凸点电极上进行植球和回流的步骤。
上述的方法,在植球前还包括在外露于塑封料的凸点电极上电镀一层底层金属的步骤。
上述的方法,完成晶圆背面的研磨后,芯片的底面形成于减薄后的晶圆的背面,并进一步在芯片的底面进行以下工艺步骤:
进行刻蚀;
进行离子注入及激光退火;
进行金属蒸镀以形成位于芯片底面的连接芯片内部电路的底部金属层。
上述的方法,形成所述底部金属层包括以下工艺步骤:
进行金属蒸镀以形成位于减薄后的晶圆的背面上的一层金属膜;并
进行干膜工艺,通过对粘贴于金属膜上的干膜进行光刻,利用光刻后的干膜作为掩膜刻蚀金属膜,仅保留位于芯片底面的金属膜以构成所述底部金属层。
本领域的技术人员阅读以下较佳实施例的详细说明,并参照附图之后,本发明的这些和其他方面的优势无疑将显而易见。
附图说明
参考所附附图,以更加充分的描述本发明的实施例。然而,所附附图仅用于说明和阐述,并不构成对本发明范围的限制。
图1A-1D是美国专利US6107164公开的晶圆级封装的半导体器件及半导体器件的制造方法。
图2A-2D是公开号为US20080044984的美国专利申请公开的背面发光器件的工艺流程。
图3是本发明的晶圆正面及位于晶圆上的芯片的俯视示意图。
图4是晶圆及芯片的局部结构的截面示意图。
图5是沿着划片槽形成切割槽的截面示意图。
图6是研磨晶圆的边缘部分形成的研磨槽的截面示意图。
图7是晶圆的边缘部分形成的研磨槽的俯视示意图。
图8是塑封模具的夹具按压在研磨槽中并于晶圆的正面形成塑封料的俯视示意图。
图9是塑封模具的夹具位于研磨槽中、塑封料形成在晶圆的正面的截面示意图。
图10是塑封模具的夹具与晶圆分离后的晶圆与塑封料的截面示意图。
图11是研磨塑封料并于塑封料中露出凸点电极的截面示意图。
图12是在塑封料中露出的凸点电极上植球的截面示意图。
图13是于晶圆的背面研磨以减薄晶圆的截面示意图。
图14是金属蒸镀后形成在减薄后的晶圆的背面的金属膜的截面示意图。
图15是沿外露的切割槽对晶圆及塑封料进行切割的截面示意图。
具体实施方式
参见图3所示,晶圆100的正面100a包含有多颗芯片110,多颗芯片110相互彼此铸造连接在一起,相邻的芯片110通过划片槽115相互界定彼此间的边界,晶圆100的圆周边沿部分为边缘120。
参见图4所示,在晶圆100与芯片110的截面示意图中,集成电路形成在晶圆100的正面100a,晶圆100的另一面为背面100b。焊垫(Bond Pad)101作为芯片110内部电路的输入/输出接触端子(I/O Pad),可为信号的输入/输出、或是Power和Ground的接口。在晶圆级封装中,可利用重分布技术RDL(Redistribution Technology)将现有芯片顶部排列在四周的铝垫重新设计成矩阵式排列。在晶圆100中,任一芯片110的顶部均设置有连接芯片110的内部电路的多个焊垫101以及凸出于晶圆100的正面100a的多个凸点电极103,焊垫101通常为铝电极。通过RDL技术,对焊垫101进行重分布形成矩阵式排列式的凸点电极103,并通过设置在芯片110顶部的金属互联层102将凸点电极103与焊垫101电性连接,金属互联层102的路径是经重新分布的金属层。在RDL技术中,金属互联层102的形成常用聚酰亚胺材料先进行曝光显影后再进行金属溅镀,如金属Ti/Cu的合金层。
参见图5所示,通常是利用金刚石切割刀,沿图4中的划片槽115切割晶圆100以形成位于划片槽115处的切割槽115a,芯片110并未完全被切割分离下来,切割槽115a的切割深度为D1。如图3所示,切割槽115a由于是沿划片槽115所切割的,而划片槽115又延伸至晶圆100的边缘120,则切割槽115a也延伸至晶圆100的边缘120处。
参见图6-7所示,利用研磨轮(Grinding Wheel)200,于晶圆100的正面100a绕着晶圆100的边缘120进行研磨,将图5中虚线部分内的边缘120所包含的预研磨部分120A研磨掉,形成图6-7中环绕在晶圆100的边缘120处的凹陷于晶圆正面100a的一环形研磨槽125,被研磨掉的预研磨部分120A原本位于图7中的研磨槽125处。如图7,在晶圆100的正面100a,研磨轮200绕着晶圆100的边缘120研磨,形成如图6中的研磨槽125的一切面125a和一底面125b,切面125a的高度也即研磨槽125的深度D2。此过程中,如图6,边缘120所包含的位于晶圆100背面100b一侧的保留部分120B并未被研磨掉,也即位于研磨槽125的底面125b下方的边缘120所包含的保留部分120B仍然在研磨过程中予以保留。其中,研磨槽125的深度D2大于切割槽115a的深度D1
参见图8-9所示,进行晶圆级封装的塑封工艺(Molding),于晶圆100的正面100a塑封晶圆100并形成覆盖正面100a的塑封料400。塑封设备的塑封模具(未示出)所包含的环形夹具300位于研磨槽125内,夹具300的底部按压在研磨槽125的底面125b上,夹具300的内壁和底部均粘合以未示出的胶带,以防止夹具300直接与塑封料或是晶圆100接触,该胶带易于从塑封料上脱离。
塑封料400的起始状态为液态或加热后为液态并在冷却后固化。由于切割槽115a延伸至晶圆100的边缘120处,则液态的塑封料400容易从切割槽115a中溢出至晶圆100的边缘120外,产生溢胶。一旦溢胶流淌至夹具300的没有粘贴胶带的外侧或是塑封模具其他的部位,则固化后的溢胶将晶圆100与这些部位牢固的黏接在一起,任何试图将夹具300从晶圆100上分离的动作将会导致晶圆碎裂。同时,如果研磨槽125的深度D2小于切割槽115a的深度D1,也会产生上述溢胶问题,只是溢胶量有所差异。而本发明的研磨槽125的设计方案较为理想的解决了此类问题,避免了溢胶的发生,所有流淌出切割槽115a的塑封料均被截止在研磨槽125内。
另一方面,如果没有研磨槽125的存在,夹具300将直接与晶圆100正面100a的边缘120所包含的预研磨部分120A(参照图5)接触,并造成该预研磨部分120A不被塑封料400覆盖。然而,由于预研磨部分120A被研磨掉,预研磨部分120A在后续工艺中不复存在,也即不会再发生该预研磨部分120A由于不被塑封料400覆盖而导致的边缘120易碎问题。
参见图10所示,塑封料400受热完全固化后,夹具300与晶圆100脱离分开,夹具300从研磨槽125中移出。形成覆盖晶圆100正面100a的塑封料400,塑封料400完全塑封包覆凸点电极103,并形成塑封料400的顶面400a。
参见图10-11所示,从顶面400a研磨塑封料400以减薄塑封料400的厚度,形成减薄后的塑封料400的顶面400b,凸点电极103于顶面400b处外露出塑封料400。并且,在完成研磨塑封料400之后,还需要在外露于塑封料400的凸点电极103上进行植球(Solder Balls Attach)和回流(SolderBalls Reflow)。如图12所示,完成植球后,焊锡球104焊接在凸点电极103上。为了保持凸点电极103与焊锡球104之间较好的接着力与低接触阻抗,以及抗氧化和高导电性,凸点电极103与焊锡球104之间还容纳有一层未示出的底层金属,如金属Ti/Ni/Cu的合金层,在植球前,在外露于塑封料400的凸点电极103上电镀上该层底层金属,底层金属的形成采用底部凸点金属化UBM(Under Bump Metallization)工艺。
参见图12-13所示,于晶圆100的背面100b进行研磨以减薄晶圆100的厚度,并于减薄后的晶圆100的背面100c外露出切割槽115a,这也意味着切割槽115a的深度D1超过经减薄后最终晶圆100的厚度D3。此研磨过程中,之前边缘120所包含的位于底面125b下方的保留部分120B此时才被研磨掉。并且,晶圆100的背面100b经过研磨后,芯片110的底面110a形成于减薄后的晶圆100的背面100c,芯片110此时依靠塑封料400相互铸造连接在一起。
参见图13-14所示,完成晶圆100背面100b的研磨,于背面100c获得芯片110的底面110a后,进一步在芯片110的底面110a进行刻蚀,如湿法刻蚀,以除去研磨后芯片110的底面110a上所残留的应力层,修复研磨过程中对芯片110的底面110a所造成的晶格损伤;之后在芯片110的底面110a进行离子注入,同时在离子注入后用以低温退火或激光退火来消除在芯片110的底面110a中产生的一些晶格缺陷;之后进行金属蒸镀,形成位于减薄后的晶圆100的背面100c上的一层金属膜105,如Ti/Ni/Ag的合金,此过程为背面金属化的过程;之后进行干膜工艺,先粘贴一层未示出的干膜(DryFilm Resists)至金属膜105上,再对干膜进行光刻,干膜经过曝光显影后,余下的干膜只存在于底面110a的部分区域的金属膜上,也即利用光刻后的干膜作为掩膜(Mask)来刻蚀金属膜105,仅保留位于芯片110底面110a上的部分金属膜,该部分金属膜构成底部金属层105a(图15所示)。图15中,位于芯片110底面110a上的底部金属层105a与芯片110的内部电路连接。上述步骤中,异于旋转涂胶(Spin-on PR Coating)形成光刻胶过程,在干膜工艺中干胶是直接粘贴在金属膜105上的。
参见图15所示,沿外露于背面100c的切割槽115a对晶圆100及塑封料400进行切割,此时用到的金刚石切割刀的厚度更薄。最终获得多颗以塑封体400a塑封包覆芯片110的晶圆级封装体500,切割沟道116即为在切割槽115a进行切割所留下的切割痕迹,塑封体400a源于对塑封料400的切割,并且底部金属层105a裸露于塑封体400a之外。基于本发明精神,在一种实施方式中,芯片110为垂直器件结构的金属氧化物半导体场效应管(MOSFET),金属层105a构成MOSFET的漏极电极,而多个焊垫101中至少包括栅极电极和源极电极。
通过说明和附图,给出了具体实施方式的特定结构的典型实施例。尽管上述发明提出了现有的较佳实施例,然,这些内容并不作为局限。
对于本领域的技术人员而言,阅读上述说明后,各种变化和修正无疑将显而易见。因此,所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容,都应认为仍属本发明的意图和范围内。

Claims (9)

1.一种避免晶圆塑封工序中晶圆破损的方法,其特征在于,包括以下步骤:
步骤1:提供一晶圆,晶圆的正面包含有多颗以划片槽相互界定边界的芯片;
步骤2:沿划片槽切割晶圆以形成位于划片槽处的切割槽;
步骤3:于晶圆的正面绕着晶圆的边缘进行研磨,形成环绕在晶圆边缘处的凹陷于晶圆正面的一环形研磨槽,形成的所述研磨槽的深度大于所述切割槽的深度;
步骤4:进行塑封工艺,于晶圆的正面塑封晶圆并形成覆盖在晶圆正面的塑封料,在塑封工艺中提供一环形夹具位于研磨槽内,夹具的底部按压在研磨槽的一底面上。
2.如权利要求1所述的方法,其特征在于,还包括以下步骤:
步骤5:研磨塑封料以减薄塑封料的厚度;
步骤6:于晶圆背面进行研磨以减薄晶圆的厚度,并于减薄后的晶圆的背面外露出切割槽;
步骤7:沿切割槽对晶圆及塑封料进行切割,形成多颗以塑封体塑封包覆所述芯片的晶圆级封装体。
3.如权利要求2所述的方法,其特征在于,任一芯片的顶部均设置有连接芯片内部电路的多个焊垫以及凸出于晶圆正面的多个凸点电极;并且
凸点电极与焊垫通过设置在芯片顶部的金属互联层而电性连接。
4.如权利要求3所述的方法,其特征在于,进行塑封工艺过程中,利用所述塑封料塑封包覆所述凸点电极。
5.如权利要求4所述的方法,其特征在于,在研磨塑封料的过程中,将所述凸点电极从塑封料中予以外露。
6.如权利要求5所述的方法,其特征在于,在完成研磨塑封料之后,还包括在外露于塑封料的凸点电极上进行植球和回流的步骤。
7.如权利要求6所述的方法,其特征在于,在植球前还包括在外露于塑封料的凸点电极上电镀一层底层金属的步骤。
8.如权利要求3所述的方法,其特征在于,完成晶圆背面的研磨后,芯片的底面形成于减薄后的晶圆的背面,并进一步在芯片的底面进行以下工艺步骤:
进行刻蚀;
进行离子注入及激光退火;
进行金属蒸镀以形成位于芯片底面上连接芯片内部电路的底部金属层。
9.如权利要求8所述的方法,其特征在于,形成所述底部金属层包括以下工艺步骤:
进行金属蒸镀形成位于减薄后的晶圆的背面上的一层金属膜;并
进行干膜工艺,通过对粘贴于金属膜上的干膜进行光刻,利用光刻后的干膜作为掩膜刻蚀金属膜,仅保留位于芯片底面上的金属膜以构成所述底部金属层。
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CN112992655B (zh) * 2021-02-05 2022-08-16 华虹半导体(无锡)有限公司 控制Taiko晶圆断差的方法
CN112959211B (zh) * 2021-02-22 2021-12-31 长江存储科技有限责任公司 晶圆处理装置和处理方法
DE102021211642A1 (de) * 2021-10-14 2023-04-20 Robert Bosch Gesellschaft mit beschränkter Haftung Leistungshalbleiter, Mold-Modul und Verfahren

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