CN103187314B - 封装载板及其制作方法 - Google Patents

封装载板及其制作方法 Download PDF

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Publication number
CN103187314B
CN103187314B CN201210089136.5A CN201210089136A CN103187314B CN 103187314 B CN103187314 B CN 103187314B CN 201210089136 A CN201210089136 A CN 201210089136A CN 103187314 B CN103187314 B CN 103187314B
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Prior art keywords
layer
patterned line
line layer
insulating barrier
chip
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CN103187314A (zh
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孙世豪
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Subtron Technology Co Ltd
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Subtron Technology Co Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/486—Via connections through the substrate with or without pins
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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Abstract

本发明公开一种封装载板及其制作方法。封装载板的制作方法包括：提供一具有一上表面的支撑板。形成一图案化线路层于支撑板的上表面上。图案化线路层暴露出部分上表面。压合一绝缘层及一位于绝缘层的一第一表面上的导电层于图案化线路层上。绝缘层覆盖图案化线路层与图案化线路层所暴露出的部分上表面。形成多个导电连接结构于图案化线路层上。图案化导电层以定义出多个分别连接导电连接结构且暴露出绝缘层的部分第一表面的接垫。移除支撑板以暴露出绝缘层相对于第一表面的一第二表面。绝缘层的第二表面与图案化线路层的一接合表面齐平。

Description

封装载板及其制作方法
技术领域
本发明涉及一种封装结构及其制作方法，且特别是涉及一种封装载板及其制作方法。
背景技术
芯片封装的目的在于保护裸露的芯片、降低芯片接点的密度及提供芯片良好的散热。常见的封装方法是芯片通过打线接合(wirebonding)或倒装接合(flipchipbonding)等方式而安装至一封装载板，以使芯片上的接点可电连接至封装载板。因此，芯片的接点分布可通过封装载板重新配置，以符合下一层级的外部元件的接点分布。
一般来说，封装载板的制作通常是以核心(core)介电层作为蕊材，并利用全加成法(fullyadditiveprocess)、半加成法(semi-additiveprocess)、减成法(subtractiveprocess)或其他方式，将图案化线路层与图案化介电层交错堆叠于核心介电层上。如此一来，核心介电层在封装载板的整体厚度上便会占着相当大的比例。因此，若无法有效地缩减核心介电层的厚度，势必会使封装结构于厚度缩减上产生极大的障碍。
发明内容
本发明的目的在于提供一种封装载板，适于承载至少一芯片。
本发明的于一目的在于提供一种封装载板的制作方法，用以制作上述的封装载板。
为达上述目的，本发明提出一种封装载板的制作方法，其包括以下步骤。提供一支撑板。支撑板具有一上表面。形成一图案化线路层于支撑板的上表面上，其中图案化线路层暴露出部分上表面。压合一绝缘层及一位于绝缘层的一第一表面上的导电层于图案化线路层上，其中绝缘层覆盖图案化线路层与图案化线路层所暴露出的部分上表面。形成多个导电连接结构于图案化线路层上。图案化上上述的导电层以定义出多个分别连接导电连接结构且暴露出绝缘层的部分第一表面的接垫。移除支撑板，以暴露出绝缘层相对于第一表面的一第二表面，其中绝缘层的第二表面与图案化线路层的一接合表面齐平。
本发明还提出一种封装载板，适于承载至少一芯片。封装载板包括一绝缘层、一图案化线路层、多个导电连接结构以及多个接垫。绝缘层具有彼此相对的一第一表面与一第二表面。图案化线路层内埋于绝缘层的第二表面，且具有一接合表面。绝缘层的第二表面与图案化线路层的接合表面齐平，且芯片配置于图案化线路层上。导电连接结构内埋于绝缘层中，且连接图案化线路层。接垫配置于绝缘层的第一表面上，且分别连接导电连接结构。
基于上述，由于本发明是先以支撑板做为一支撑结构，且将图案化线路层、绝缘层、导电连接结构及接垫形成于支撑板上后，移除支撑板而完成封装载板的制作。因此，相较于现有具有核心介电层的封装结构而言，本发明的封装载板可具有较薄的封装厚度。再者，由于本发明的封装载板的图案化线路层是内埋于绝缘层，因此当芯片配置于图案化线路层上而构成一封装结构时，此封装结构可具有较薄的封装厚度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1E为本发明的一实施例的一种封装载板的制作方法的剖面示意图；
图1F为本发明的一实施例的一种封装载板的剖面示意图；
图1G为本发明的另一实施例的一种封装载板的剖面示意图；
图1H为本发明的又一实施例的一种封装载板的剖面示意图；
图2A为本发明的一实施例的一种封装载板承载多个芯片的剖面示意图；
图2B为本发明另的一实施例的一种封装载板承载多个芯片的剖面示意图；
图2C为本发明又的一实施例的一种封装载板承载多个芯片的剖面示意图；
图2D为本发明再的一实施例的一种封装载板承载多个芯片的剖面示意图。
主要元件符号说明
10：支撑板
12：上表面
100a、100b、100c、100d、100e、100f：封装载板
110：图案化线路层
112：接合表面
114a、114b：芯片接垫
116：接合接垫
120：绝缘层
122：第一表面
124：第二表面
130a、130b：导电层
132：底表面
140a、140b：导电连接结构
142：导电材料
144：下表面
146：表面
150a、150b：接垫
160：防焊层
170：表面处理层
200a、200b：芯片
210：封装胶体
220：焊线
230：焊球
H：盲孔
具体实施方式
图1A至图1E为本发明的一实施例的一种封装载板的制作方法的剖面示意图。请先参考图1A，依照本实施例的封装载板的制作方法，首先，提供一支撑板10，其中支撑板10具有一上表面12。接着，形成一图案化线路层110于支撑板10的上表面12上，其中图案化线路层110暴露出支撑板10的部分上表面12，且图案化线路层110的线宽例如是介于15微米至35微米之间，而图案化线路层110的线距至少大于15微米。意即，于此的图案化线路层110可视为一种细线路。
需说明的是，在本实施例中，形成图案化线路层110的方法是电镀法(plating)，必须先形成一电镀种子层(未绘示)于支撑板10上，之后再以此电镀种子层为电极，电镀形成此图案化线路层110，因此支撑板10的材质可采用绝缘材料或金属材料。
接着，请参考图1B-a，压合一绝缘层120及一位于绝缘层120的一第一表面122上的导电层130a于图案化线路层110上，其中绝缘层120覆盖图案化线路层110与图案化线路层110所暴露出的支撑板10的部分上表面12。
接着，请参考图1C-a，对导电层130a照射一激光光束(未绘示)，以形成多个从导电层130a延伸至图案化线路层110的盲孔H。接着，并填入一导电材料142于盲孔H内，而形成导电连接结构140a，其中导电连接结构140a连接导电层130a与图案化线路层110，且每一导电连接结构140a的一下表面144与导电层130a的一底表面132实质上齐平。
值得一提的是，本发明并不限定压合绝缘层120及其上的导电层130a于图案化线路层110上以及形成导电连接结构140a的顺序，以及导电连接结构140a的结构形态。虽然此处所提及的步骤是先压合绝缘层120及其上的导电层130a于图案化线路层110上之后，再形成导电连接结构140a，且此导电连接结构140a具体化为一导电盲孔连接结构。然而，于其他实施例中，请参考图1B-b，也可先形成导电连接结构140b于图案化线路层110上之后，之后，请参考图1C-b，再压合绝缘层120及其上的导电层130b于图案化线路层110上。此时，导电连接结构140b会穿出绝缘层120且与导电层130b接触，其中导电连接结构140b的一表面146与绝缘层120的第一表面122实质上切齐，且此导电连接结构140b具体化为一导电柱。此外，绝缘层120包覆导电连接结构140b，且导电连接结构140b位于导电层130b与图案化线路层110之间。上述的步骤仍属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。
之后，接续图1C-a的步骤后，请参考图1D，图案化上述的导电层130a，以定义出多个分别连接导电连接结构140a且暴露出绝缘层120的部分第一表面122的接垫150a。
最后，请同时参考图1D与图1E，移除支撑板10，以暴露出绝缘层120相对于第一表面122的一第二表面124，其中绝缘层120的第二表面124与图案化线路层110的一接合表面112实质上齐平。至此，已完成封装载板100a的制作。
在结构上，请再参考图1E，本实施例的封装载板100a包括图案化线路层110、绝缘层120、导电连接结构140a以及接垫150a。绝缘层120具有彼此相对的第一表面122与第二表面124。图案化线路层110内埋于绝缘层120的第二表面124且具有一接合表面112。绝缘层120的第二表面124与图案化线路层110的接合表面112实质上齐平。导电连接结构140a内埋于绝缘层120中且连接图案化线路层110。接垫150a配置于绝缘层120的第一表面122上且分别连接导电连接结构140a。
由于本实施例是先以支撑板10做为一支撑结构，且将图案化线路层110、绝缘层120、导电连接结构140a及接垫150a形成于支撑板10上后，移除支撑板10而完成封装载板100a的制作。因此，相较于现有具有核心介电层的封装结构而言，本实施例的封装载板100a无须支撑结构(即支撑板10或现有的核心介电层)的厚度，可具有较薄的封装厚度。再者，由于本实施例的封装载板100a的图案化线路层110是内埋于绝缘层120，因此当将一芯片(未绘示)配置于封装载板100a的图案化线路层110上而构成一封装结构时，此封装结构可具有较薄的封装厚度，以符合现今薄型化的趋势。
值得一提的是，本发明并不限定绝缘层120、导电层130a(或130b)及导电连接结构140a(或140b)的层数，虽然与此所形成的绝缘层120、导电层130a(或130b)及导电连接结构140a(或140b)的层数实质上各为一层。但于其他未绘示的实施例中，本领域的技术人员当可参照前述实施例的图1B-a、1C-a、1B-b、1C-b说明，依据实际需求，重复前述1B-a、1C-a、1B-b、1C-b的步骤，而形成具有多层导电层的封装载板的结构，以达到所需的技术效果。
在此必须说明的是，下述实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，下述实施例不再重复赘述。
图1F为本发明的一实施例的一种封装载板的剖面示意图。请参考图1F，本实施例的封装载板100b与图1E的封装载板100a相似，惟二者主要差异之处在于：本实施例的封装载板100b更包括一防焊层160，其中防焊层160配置于绝缘层120的第二表面124上，其中防焊层160暴露出图案化线路层110的部分接合表面112。
在制作工艺上，本实施例的封装载板100b可以采用与前述实施例的封装载板100a大致相同的制作方式，并且在图1E的步骤后，即移除支撑板10之后，形成一防焊层160于绝缘层120的第二表面124上，其中防焊层160暴露出图案化线路层110的部分接合表面112，用以可作为后续芯片(未绘示)与焊线(未绘示)的接合位置。此即可大致完成封装载板100b的制作。
图1G为本发明的另一实施例的一种封装载板的剖面示意图。请参考图1G，本实施例的封装载板100c与图1F的封装载板100b相似，惟二者主要差异之处在于：本实施例的封装载板100c更包括一表面处理层170，其中表面处理层170配置于图案化线路层110的接合表面112上，且表面处理层170的材质包括金、银、镍/金、镍/钯/金、镍/银或其他适当的金属材质。
在制作工艺上，本实施例的封装载板100c可以采用与前述实施例的封装载板100b大致相同的制作方式，并且在图1F的步骤后，即形成防焊层160之后，形成一表面处理层170于未被防焊层160所覆盖的图案化线路层110的接合表面112上，用以避免图案化线路层110产生氧化而影响后续芯片(未绘示)与焊线(未绘示)接合的可靠度。此即可大致完成封装载板100c的制作。
图1H为本发明的又一实施例的一种封装载板的剖面示意图。请参考图1H，本实施例的封装载板100d与图1E的封装载板100a相似，惟二者主要差异之处在于：本实施例的封装载板100d更包括一表面处理层170，其中表面处理层170配置于图案化线路层110的接合表面112上，且表面处理层170的材质包括金、银、镍/金、镍/钯/金、镍/银或其他适当的金属材质。
在制作工艺上，本实施例的封装载板100d可以采用与前述实施例的封装载板100a大致相同的制作方式，并且在图1E的步骤后，即移除支撑板10之后，形成一表面处理层170于图案化线路层110的接合表面112上，用以避免图案化线路层110产生氧化而影响后续芯片(未绘示)与焊线(未绘示)接合的可靠度。此即可大致完成封装载板100d的制作。
图2A为为本发明的一实施例的一种封装载板承载多个芯片的剖面示意图。请参考图2A，本实施例的封装载板100c适于承载至少一芯片(图2A中绘示两个芯片200a、200b)，其中芯片200a、200b配置于图案化线路层110上方的表面处理层170上，且芯片200a、200b例如是一集成电路芯片，其例如为一绘图芯片、一记忆体芯片等单一芯片或是一芯片模块，或者是一光电芯片，其例如是一发光二极管(LED)芯片或一激光二极管芯片，于此并不加以限制芯片200a、200b的种类与型态。
详细来说，本实施例的图案化线路层110包括至少一芯片接垫(图2A中示意地绘示二个芯片接垫114a、114b)与多个接合接垫116(图2A中示意地绘示二个)，其中芯片200a、200b分别配置于芯片接垫114a、114b上，且芯片200a、200b分别通过至少一焊线220而连接至接合接垫116上。于此，芯片200a、200b有部分区域是埋入于防焊层160与表面处理层170所构成的一空间中。再者，本实施例可通过一封装胶体210来包倒装芯片200a、200b、焊线220以及部分封装载板100c，用以保护芯片200a、200b、焊线220与封装载板100c之间的电连接关系。此外，本实施例也可通过多个焊球230焊接至接垫150a上，来使封装载板100c通过焊球230与外部电路(未绘示)电连接。
值得一提的是，在其他实施例中，请参考图2B，芯片200a、200b也可配置于具有导电柱形态的导电连接结构140b的封装载板100e上，其中接垫150b是对导电层130b(请参考图1C-b)进行一图案化的步骤所构成；或者是，请参考图2C，芯片200a、200b也可配置封装载板100d上，其中图案化线路层110具有三个接合接垫116；亦或是，请参考图2D，芯片200a、200b也可配置于封装载板100f，且通过焊线220与接合接垫116电连接，其中此封装载板100f与图1E的封装载板100a相似，差异之处在于：封装载板100f具有导电柱形态的导电连接结构140b以及配置于图案化线路层110的接合表面112上的表面处理层170，其中接垫150b是对导电层130b(请参考图1C-b)进行一图案化的步骤所构成。
此外，在其他未绘示的实施例中，在也可选用于如前述实施例所提及的封装载板100a、100b本领域的技术人员当可参照前述实施例的说明，依据实际需求，将芯片200a、200b配置于所选用的前述构件上，以达到所需的技术效果。
综上所述，由于本发明是先以支撑板做为一支撑结构，且将图案化线路层、绝缘层、导电连接结构及接垫形成于支撑板上后，移除支撑板而完成封装载板的制作。因此，相较于现有具有核心介电层的封装结构而言，本发明的封装载板可具有较薄的封装厚度。再者，由于本发明的封装载板的图案化线路层是内埋于绝缘层，因此当芯片配置于图案化线路层上而构成一封装结构时，此封装结构可具有较薄的封装厚度。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (6)

1.一种封装载板的制作方法，包括：
提供一支撑板，该支撑板具有上表面；
形成一图案化线路层于该支撑板的该上表面上，其中该图案化线路层暴露出部分该上表面，其中该图案化线路层包括至少一芯片接垫；
压合一绝缘层及一位于该绝缘层的第一表面上的导电层于该图案化线路层上，其中该绝缘层覆盖该图案化线路层与该图案化线路层所暴露出的部分该上表面；
形成多个导电连接结构于该图案化线路层上；
图案化该导电层，以定义出多个分别连接该些导电连接结构且暴露出该绝缘层的部分该第一表面的接垫；以及
移除该支撑板，以暴露出该绝缘层相对于该第一表面的第二表面，其中该绝缘层的该第二表面与该图案化线路层的一接合表面齐平；
于移除该支撑板之后，形成一防焊层于该绝缘层的该第二表面上，其中该防焊层暴露出该图案化线路层的部分该接合表面；以及
于移除该支撑板之后，形成一表面处理层于该图案化线路层的该接合表面上，且该表面处理层未于该防焊层上，该表面处理层位在一芯片以及该芯片接垫之间，该防焊层的一第一顶表面与该表面处理层的一第二顶表面之间具有一高度差，以定义出位于该防焊层的一侧壁与该表面处理层的该第二顶表面之间的一空间，且该芯片的一部分区域埋入于该防焊层与该表面处理层所构成的该空间中。
2.如权利要求1所述的封装载板的制作方法，其中形成该些导电连接结构于该图案化线路层上的步骤是在压合该绝缘层及其上的该导电层于该图案化线路层上之后，而形成该些导电连接结构于该图案化线路层上的步骤包括：
对该导电层照射一激光光束，以形成多个从该导电层延伸至该图案化线路层的盲孔；以及
填入一导电材料于该些盲孔内，而形成该些导电连接结构，其中该些导电连接结构连接该导电层与该图案化线路层，且各该导电连接结构的一下表面与该导电层的一底表面齐平。
3.如权利要求1所述的封装载板的制作方法，其中形成该些导电连接结构于该图案化线路层上的步骤是在压合该绝缘层及其上的该导电层于该图案化线路层上之前，而压合该绝缘层及其上的该导电层于该图案化线路层上之后，该绝缘层包覆该些导电连接结构，且该些导电连接结构位于该导电层与该图案化线路层之间。
4.一种封装载板，适于承载至少一芯片，该封装载板包括：
绝缘层，具有彼此相对的第一表面与第二表面；
图案化线路层，内埋于该绝缘层的该第二表面，且具有接合表面，其中该绝缘层的该第二表面与该图案化线路层的该接合表面齐平，且该芯片配置于该图案化线路层上，其中该图案化线路层包括至少一芯片接垫，该芯片配置于该芯片接垫上；
多个导电连接结构，内埋于该绝缘层中，且连接该图案化线路层；以及
多个接垫，配置于该绝缘层的该第一表面上，且分别连接该些导电连接结构；
一防焊层，配置于该绝缘层的该第二表面上，其中该防焊层暴露出该图案化线路层的部分该接合表面；以及
一表面处理层，配置于该芯片以及该芯片接垫之间，该表面处理层于该图案化线路层的该接合表面上，且该表面处理层未于该防焊层上，其中该防焊层的一第一顶表面与该表面处理层的一第二顶表面之间具有一高度差，以定义出位于该防焊层的一侧壁与该表面处理层的该第二顶表面之间的一空间，该芯片的一部分区域埋入于该防焊层与该表面处理层所构成的该空间中。
5.如权利要求4所述的封装载板，其中该图案化线路层包括至少一芯片接垫与多个接合接垫，该芯片配置于该芯片接垫上，且该芯片通过至少一焊线连接至该些接合接垫之一上。
6.如权利要求4所述的封装载板，其中该图案化线路层的线宽介于15微米至35微米之间，而该图案化线路层的线距至少大于15微米。
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