CN103489791B - 封装载板及其制作方法 - Google Patents

封装载板及其制作方法 Download PDF

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CN103489791B
CN103489791B CN201210300938.6A CN201210300938A CN103489791B CN 103489791 B CN103489791 B CN 103489791B CN 201210300938 A CN201210300938 A CN 201210300938A CN 103489791 B CN103489791 B CN 103489791B
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layer
metal level
carrier plate
metal
supporting bracket
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CN103489791A (zh
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王金胜
戴暐伦
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Subtron Technology Co Ltd
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Subtron Technology Co Ltd
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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Abstract

本发明公开一种封装载板及其制作方法。该制作方法提供一支撑板。支撑板上已配置有一金属层。在金属层上形成一图案化干膜层。图案化干膜层暴露出部分金属层。以图案化干膜层为一电镀掩模，电镀一表面处理层于图案化干膜层所暴露出的部分金属层上。移除图案化干膜层，以暴露出部分金属层。以表面处理层为一蚀刻掩模，蚀刻金属层未被表面处理层所覆盖的部分，而形成一图案化金属层。

Description

封装载板及其制作方法
技术领域
本发明涉及一种封装结构及其制作方法，且特别是涉及一种封装载板及其制作方法。
背景技术
芯片封装的目的是提供芯片适当的信号路径、导热路径及结构保护。传统的打线（wirebonding）技术通常采用导线架（leadframe）作为芯片的承载器（carrier）。随着芯片的接点密度逐渐提高，导线架已无法再提供更高的接点密度，故可利用具有高接点密度的封装载板（packagecarrier）来取代之，并通过金属导线或凸块（bump）等导电媒体，将芯片封装至封装载板上。
一般来说，封装载板的制作通常是以核心（core）介电层作为蕊材，并利用全加成法（fullyadditiveprocess）、半加成法（semi-additiveprocess）、减成法（subtractiveprocess）或其他方式，将多层的图案化线路层与图案化介电层交错堆叠于核心介电层上。如此一来，核心介电层在封装载板的整体厚度上便会占着相当大的比例。因此，若无法有效地缩减核心介电层的厚度，势必会使封装结构于厚度缩减上产生极大的障碍。
发明内容
本发明的目的在于提供一种封装载板，适于承载一芯片。
本发明的再一目的在于提供一种封装载板的制作方法，用以制作上述的封装载板。
为达上述目的，本发明提出一种封装载板的制作方法，其包括以下步骤。提供一支撑板。支撑板上已配置有一金属层。在金属层上形成一图案化干膜层。图案化干膜层暴露出部分金属层。以图案化干膜层为一电镀掩模，电镀一表面处理层于图案化干膜层所暴露出的部分金属层上。移除图案化干膜层，以暴露出部分金属层。以表面处理层为一蚀刻掩模，蚀刻金属层未被表面处理层所覆盖的部分，而形成一图案化金属层。
在本发明的一实施例中，上述形成支撑板的步骤，包括：提供两个金属层，一金属层通过一胶合剂局部结合于另一金属层上。分别于金属层上形成一导电层。分别压合一粘着层及一位于粘着层上的绝缘层于导电层上。移除胶合剂，而形成两个自独立且其上分别配置有金属层的支撑板，其中每一支撑板包括依序堆叠的绝缘层、粘着层以及导电层，且金属层位于导电层上。
在本发明的一实施例中，上述导电层的材质包括镍。
在本发明的一实施例中，上述形成导电层的方法包括电镀法。
在本发明的一实施例中，上述表面处理层的材质包括镍或银。
本发明提出一种封装载板，其适于承载一芯片。封装载板包括一支撑板、一图案化金属层以及一表面处理层。支撑板具有一上表面。图案化金属层配置于支撑板上，且暴露出部分上表面。表面处理层配置于图案化金属层上，其中芯片配置于表面处理层上且与表面处理层电连接。
在本发明的一实施例中，上述支撑板包括依序堆叠的一绝缘层、一粘着层以及一导电层，而图案化金属层位于导电层上，且暴露出部分导电层。
在本发明的一实施例中，上述表面处理层的材质包括镍或银。
在本发明的一实施例中，上述芯片通过打线接合而电连接至表面处理层。
在本发明的一实施例中，上述芯片通过倒装接合而电连接至表面处理层。
基于上述，本发明的封装载板是由图案化金属层与表面处理层来构成放置芯片的芯片座以及用来电连接的接垫，且于后续完成芯片的封胶制作工艺后，会移除支撑板，而构成一封装厚度较薄的封装结构的成品。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1G为本发明的一实施例的一种封装载板的制作方法的剖面示意图；
图2A至图2C为图1G的封装载板承载一芯片的制作工艺步骤的剖面示意图；
图3为图1G的封装载板承载一芯片的剖面示意图。
主要元件符号说明
10：胶合剂
20、25：芯片
30：粘着层
40：焊线
50：封装胶体
52：下表面
60：凸块
100：封装载板
110a、110b：金属层
110a’：图案化金属层
112：底表面
120a、120b：支撑板
121：上表面
122a、122b：导电层
124a、124b：粘着层
126a、126b：绝缘层
130：图案化干膜层
140：表面处理层
200a、200b：封装结构
具体实施方式
图1A至图1G为本发明的一实施例的一种封装载板的制作方法的剖面示意图。请先参考图1D，依照本实施例的封装载板的制作方法，首先，提供一支撑板120a，其中支撑板120a上已配置有一金属层110a。
详细来说，形成支撑板120a的步骤包括以下步骤。首先，请参考图1A，提供两个金属层110a、110b，其中金属层110a通过一胶合剂10局部结合于金属层110b上，且金属层110a的材质包括铜、铝、银、金或其他具有高导热性质的金属。接着，请参考图1B，于金属层110a上形成一导电层122a，且于金属层110b上形成一导电层122b。于此，形成导电层122a、122b的方法包括电镀法，且导电层122a、122b的材质例如是镍。之后，请参考图1C，压合一粘着层124a及一位于粘着层124a上的绝缘层126a于导电层122a上，且压合一粘着层124b及一位于粘着层124b上的绝缘层126b于导电层122b上，其中绝缘层126a、126b的材质例如是玻纤树脂。于此，绝缘层126a、粘着层124a以及导电层122a构成一支撑板120a，而绝缘层126b、粘着层124b以及导电层122b则构成另一支撑板120b。最后，请参考图1D，移除胶合剂10，而形成两个自独立且其上分别配置有金属层110a（或110b）的支撑板120a（或120b），其中支撑板120a是由依序堆叠的绝缘层126a、粘着层124a以及导电层122a所组成，而金属层110a位于导电层122a上，且暴露出部分导电层122a。至此，已完成支撑板120a及其上的金属层110a的制作。
需说明的是，由于本实施例是采用对称的方式来形成两个支撑板120a、120b及其上的金属层110a、110b，因此于压合粘着层124a、124b及其上的绝缘层126a、126b于金属层110a、110b的过程中，可以有效避免压合后结构呈现弯翘的问题。再者，由于本实施例是采用对称的方式来形成两个支撑板120a、120b及其上的金属层110a、110b，因此于解板后（即移除胶合剂10之后），可同时得到两个各自独立的结构，可有效节省制作工艺时间，进而提高产能。
接着，请参考图1E，于金属层110a上形成一图案化干膜层130，其中图案化干膜层130暴露出部分金属层110a。
之后，请参考图1F，以图案化干膜层130为一电镀掩模，电镀一表面处理层140于图案化干膜层130所暴露出的部分金属层110a上。于此，表面处理层140的材质例如是镍或银。
最后，请参考图1G，移除图案化干膜层130，以暴露出部分金属层110a。接着，并且以表面处理层140为一蚀刻掩模，蚀刻金属层110a未被表面处理层140所覆盖的部分，而形成一图案化金属层110a’。至此，已完成封装载板100的制作。
在结构上，请再参考图1G，封装载板100包括支撑板120a、图案化金属层110a’以及表面处理层140。支撑板120a包括依序堆叠的绝缘层126a、粘着层124a以及导电层122a，且支撑板120a具有一上表面121。图案化金属层110a’配置于支撑板120a上，且暴露出部分上表面121，其中图案化金属层110a’是位于导电层122a上，且暴露出部分导电层122a。表面处理层140配置于图案化金属层110a’上，其中表面处理层140的材质例如是镍或银。
图2A至图2C为图1G的封装载板承载一芯片的制作工艺步骤的剖面示意图。请先参考图2A，在本实施例中，封装载板100适于承载一芯片20，其中芯片20通过一粘着层30而配置于图案化金属层110a’上方的表面处理层140上，且芯片20通过一焊线40与表面处理层140电连接。也就是说，本实施例的芯片20是通过打线接合而电连接至表面处理层140。于此，芯片20例如是一集成电路芯片，其例如为一绘图芯片、一存储器芯片等单一芯片或是一芯片模块，或一发光二极管（LED）芯片。
接着，请参考图2B，进行一封胶制作工艺，以形成一封装胶体50于封装载板100上，其中封装胶体50包倒装芯片20、粘着层30、焊线40、封装载板100的表面处理层140与图案化金属层110a’，且覆盖支撑板120a的部分上表面121。
最后，请参考图2C，移除封装载板100的支撑板120a，以暴露出图案化金属层110a’的底表面112，其中封装胶体50的一下表面52与图案化金属层110a’的底表面112实质上切齐。至此，已完成封装结构200a的制作，其中封装结构200a例如是一四方扁平无外引脚(quadflatno-lead,QFN)型态的封装结构。
由于本实施例的封装载板100是由图案化金属层110a’与表面处理层140来构成放置芯片20的芯片座（即芯片20所在位置）以及用来电连接的接垫（即焊线40的落点位置），且于后续完成芯片20的封胶制作工艺后，会移除支撑板120a，而构成封装结构200a的成品。也就是说，支撑板120a于封胶制作工艺后会被移除，而使封装结构200a中的封装载板100剩下图案化金属层110a’以及表面处理层140。因此，相较于现有由多层图案化线路层与图案化介电层交错堆叠于核心介电层所构成的封装载板而言，本实施例所采用的封装载板100可使后续完成的封装结构200a具有较薄的封装厚度。再者，由于芯片20是配置于表面处理层140上，因此芯片20所产生的热可直接通过金属材质的表面处理层140与图案化金属层110a’而快速地传递至外界，除了可提高芯片20的使用效率与使用寿命外，也可提高封装结构200a的散热效果。
值得一提的是，本发明并不限定芯片20与封装载板100的接合形态，虽然此处所提及的芯片20具体化是通过打线接合而电连接至封装载板100的表面处理层140。不过，在另一实施例中，请参考图3，芯片25也可通过多个凸块60以倒装接合的方式而电连接至表面处理层140上。也就是说，上述的芯片20与封装载板100的接合形态仅为举例说明之用，并非用以限定本发明。
综上所述，本发明的封装载板是由图案化金属层与表面处理层来构成放置芯片的芯片座以及用来电连接的接垫，且于后续完成芯片的封胶制作工艺后，会移除支撑板，而构成一封装厚度较薄的封装结构的成品。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (4)

1.一种封装载板的制作方法，包括：
提供一支撑板，该支撑板上已配置有一金属层，其中提供该支撑板的步骤，包括：
提供两个该金属层，一该金属层通过一胶合剂局部结合于另一该金属层上；
分别于该些金属层上形成一导电层；
分别压合一粘着层及一位于该粘着层上的绝缘层于该些导电层上；以及
移除该胶合剂，而形成两个自独立且其上分别配置有该些金属层的该些支撑板，其中各该支撑板包括依序堆叠的该绝缘层、该粘着层以及该导电层，且该金属层位于该导电层上；
在该金属层上形成一图案化干膜层，该图案化干膜层暴露出部分该金属层；
以该图案化干膜层为一电镀掩模，电镀一表面处理层于该图案化干膜层所暴露出的部分该金属层上；
移除该图案化干膜层，以暴露出部分该金属层；以及
以该表面处理层为一蚀刻掩模，蚀刻该金属层未被该表面处理层所覆盖的部分，而形成一图案化金属层。
2.如权利要求1所述的封装载板的制作方法，其中该导电层的材质包括镍。
3.如权利要求1所述的封装载板的制作方法，其中形成该些导电层的方法包括电镀法。
4.如权利要求1所述的封装载板的制作方法，其中该表面处理层的材质包括镍或银。
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